WIP: [MachineOperand][MIR] Add isRenamable to MachineOperand.

[gberry]

Summary

Add isRenamable() predicate to MachineOperand. This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand. Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).

[gberry]

Update lit tests.

[gberry]

Ping.
This change should be in pretty good shape now, but the MI interface changes could use a good review.
I had to update quite a few MIR tests to add the 'norename' flag. A lot of these could probably be fixed by getting the relevant passes to set the norename flag more precisely, but I figured it would be better to do that in separate changes.

[MatzeB]

include/llvm/CodeGen/MachineOperand.h

88–89 ↗

(On Diff #121965)

Written like this it'll probably be part of the IsDef comment in doxygen. Maybe just append a "Only valid for MO_Register" to each of the four fields instead?

103 ↗

(On Diff #121965)

The last sentence is not true anymore.

106 ↗

(On Diff #121965)

One interesting discussion here is how "safe" things really are when this bit is set :)
I think AMDGPU for example has some extra constraints on physregs that the register allocator isn't aware of, they fix things in a separate pass after allocation AFAIK and after that you better not rename anymore. I think we currently set the ExtraSrcRegAllocReq and ExtraDefRegAllocReq on those machine instructions to indicate that. Then again we the infrastructure of this of this patch in place we could require them to clear the renamable flag on all affected operands.

107–109 ↗

(On Diff #121965)

Should we state that this bit only affects physical registers? That way we don't need to set this bit everywhere a vreg is used. And I can't imagine any case where we have a non-renamable vreg or put another way: I do not want to add code dealing with non-renamable vregs.

310–311 ↗

(On Diff #121965)

I assume changing this to assert(isReg() && IsDef()) breaks too much code?

368–372 ↗

(On Diff #121965)

See my comment in setReg(), I think we shouldn't have this method.

419 ↗

(On Diff #121965)

Maybe add assert(TargetRegisterInfo::isPhysicalRegister(getReg() && "Renamable flag may only be set for physregs");

lib/CodeGen/MIRParser/MIParser.cpp

1221 ↗

(On Diff #121965)

• "operands" instead of "MIR regs"?

lib/CodeGen/MIRParser/MIRParser.cpp

420–428 ↗

(On Diff #121965)

I'm not a fan of the parsing changing depending on a function property. I think the right thing to do is to encode "renamable" and not "norename" after all.

If you are worried about mir output becoming noisy/hard to read after regalloc with "renamable" flags everywhere, maybe we can shorten "renamable" to some character like ~?

lib/CodeGen/MachineInstr.cpp

90–91 ↗

(On Diff #121965)

I find it surprising that setReg() affects a flag as well. I'd rather just modify the regallocators to set the flag explicitely where possible.

lib/CodeGen/MachineVerifier.cpp

365–366 ↗

(On Diff #121965)

NoVRegs should mean exactly that: We are guaranteed that no vregs are used. It does not mean: We are in a pass after register allocation.

1209–1214 ↗

(On Diff #121965)

As stated above I would go for Renamable only ever being set on physregs. That way the rules don't need to be conditional based on "regsAllocated".

[gberry]

@MatzeB I have a new version that is much simpler that I believe addresses all of your points. I got rid of the context-dependent printing/parsing of the renamable flag (and changed it from 'norename') which ended up reducing the amount of lit test churn. I also restricted it to physical registers and tried to enforce the hasExtraRegAllocReq constraints, though that may not be complete.

include/llvm/CodeGen/MachineOperand.h

310–311 ↗

(On Diff #121965)

Yeah, I tried adding it and gave up after fixing it in about 5 different passes.

[gberry]

New version based on feedback from Matthias

[MatzeB]

Thanks, conditional LGTM.

My only remaining issue here is addOperand() changing operands. If you can easily fix this just commit without further review, otherwise at least write a comment on why you need it.

include/llvm/CodeGen/MachineOperand.h

106 ↗

(On Diff #121965)

I would still vote for a weaker language here by removing the word "safely".

lib/CodeGen/MachineInstr.cpp

263–268 ↗

(On Diff #125424)

Is this a good idea? Intuitively I would not expect an addOperand() function to change the operand. Admittedly someone already broke that rule with the setIsEarlyClobber() above but unless all other solutions are really bad, I'd still prefer not to have this here.

[MatzeB]

It would also be nice to pick a suitable test in test/CodeGen/MIR/X86 and add one line to ensure .mir prints/parses the flag correctly.

[gberry]

I made the comment less strong and added a test case. Let me know what you think about the addOperand issue.

lib/CodeGen/MachineInstr.cpp

263–268 ↗

(On Diff #125424)

Without this every bit of code that is builds an instruction whose opcode hasExtraRegAllocReq would need to remember to clear the appropriate renamable bit. It seems to me that the hasExtraRegAllocReq property is less useful that way. I suppose we could untie these two properties and ask that users check both the renamable bit and the hasExtraRegAllocReq (with a helper function), in which case the verification that the two properties are consistent goes away.

[gberry]

Made comment less strong and added MIR test case

[MatzeB]

lib/CodeGen/MachineInstr.cpp

263–268 ↗

(On Diff #125424)

But unless I miss something, the default is not-renamable anyway so all the random code out there doesn't need to be changed. The only places that set the renamable bit are the regallocators and they already use MO.setIsRenamableIfNoExtraRegAllocReq() in your commit. So what other code is there that would set the renamable bit even though it shouldn't?

[gberry]

lib/CodeGen/MachineInstr.cpp

263–268 ↗

(On Diff #125424)

One example that occurs in the lit tests is code that is constructing a hasExtraReqAllocReq machine instruction after register allocation and copying over operands from an existing instruction. These particular operands are renamable since they were originally virtual regs. Once they are added to the new instruction they remain renamable, but are operands of a hasExtraRegAllocReq opcode so they fail verification.

[MatzeB]

lib/CodeGen/MachineInstr.cpp

263–268 ↗

(On Diff #125424)

I assume that will be mostly (or all) AMDGPU code, is adjusting this code so hard that it justifies extra logic in a core function like addOperand()? At least we have the asserts in place and won't silently miscompile...

[gberry]

New version that doesn't force renamable flag to false for hasExtraRegAlloc opcodes in addOperand

[gberry]

lib/CodeGen/MachineInstr.cpp

263–268 ↗

(On Diff #125424)

I added a new version that removes this change to addOperand and fixes the lit test failures (which only showed up for ARM). I'm a bit concerned that this approach will break other targets/tests, but I suppose we can always revisit this later if it is a problem.

llvm/trunk/docs/MIRLangRef.rst

* - ``internal``
      - ``RegState::InternalRead``
 
    * - ``early-clobber``
      - ``RegState::EarlyClobber``
 
    * - ``debug-use``
      - ``RegState::Debug``
 
+   * - ``renamable``
+     - ``RegState::Renamable``
+
 .. _subregister-indices:
 
 Subregister Indices
 ~~~~~~~~~~~~~~~~~~~
 
 The register machine operands can reference a portion of a register by using
 the subregister indices. The example below shows an instance of the ``COPY``
 pseudo instruction that uses the X86 ``sub_8bit`` subregister index to copy 8

llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h

 #define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBundle.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/InstrTypes.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/Support/ErrorHandling.h"
 #include <cassert>
 #include <cstdint>
 #include <utility>
 
 namespace llvm {
 
 class MCInstrDesc;
 class MDNode;
 
 namespace RegState {
 
   enum {
     Define         = 0x2,
     Implicit       = 0x4,
     Kill           = 0x8,
     Dead           = 0x10,
     Undef          = 0x20,
     EarlyClobber   = 0x40,
     Debug          = 0x80,
     InternalRead   = 0x100,
+    Renamable      = 0x200,
     DefineNoRead   = Define | Undef,
     ImplicitDefine = Implicit | Define,
     ImplicitKill   = Implicit | Kill
   };
 
 } // end namespace RegState
 
 class MachineInstrBuilder {
MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
                                                flags & RegState::Define,
                                                flags & RegState::Implicit,
                                                flags & RegState::Kill,
                                                flags & RegState::Dead,
                                                flags & RegState::Undef,
                                                flags & RegState::EarlyClobber,
                                                SubReg,
                                                flags & RegState::Debug,
-                                               flags & RegState::InternalRead));
+                                               flags & RegState::InternalRead,
+                                               flags & RegState::Renamable));
     return *this;
   }
 
   /// Add a virtual register definition operand.
   const MachineInstrBuilder &addDef(unsigned RegNo, unsigned Flags = 0,
                                     unsigned SubReg = 0) const {
     return addReg(RegNo, Flags | RegState::Define, SubReg);
   }
inline unsigned getUndefRegState(bool B) {
   return B ? RegState::Undef : 0;
 }
 inline unsigned getInternalReadRegState(bool B) {
   return B ? RegState::InternalRead : 0;
 }
 inline unsigned getDebugRegState(bool B) {
   return B ? RegState::Debug : 0;
 }
+inline unsigned getRenamableRegState(bool B) {
+  return B ? RegState::Renamable : 0;
+}
 
 /// Get all register state flags from machine operand \p RegOp.
 inline unsigned getRegState(const MachineOperand &RegOp) {
   assert(RegOp.isReg() && "Not a register operand");
   return getDefRegState(RegOp.isDef())                    |
          getImplRegState(RegOp.isImplicit())              |
          getKillRegState(RegOp.isKill())                  |
          getDeadRegState(RegOp.isDead())                  |
          getUndefRegState(RegOp.isUndef())                |
          getInternalReadRegState(RegOp.isInternalRead())  |
-         getDebugRegState(RegOp.isDebug());
+         getDebugRegState(RegOp.isDebug())                |
+         getRenamableRegState(
+             TargetRegisterInfo::isPhysicalRegister(RegOp.getReg()) &&
+             RegOp.isRenamable());
 }
 
 /// Helper class for constructing bundles of MachineInstrs.
 ///
 /// MIBundleBuilder can create a bundle from scratch by inserting new
 /// MachineInstrs one at a time, or it can create a bundle from a sequence of
 /// existing MachineInstrs in a basic block.
 class MIBundleBuilder {

llvm/trunk/include/llvm/CodeGen/MachineOperand.h

private:
   /// For all other kinds of operands, this field holds target-specific flags.
   unsigned SubReg_TargetFlags : 12;
 
   /// TiedTo - Non-zero when this register operand is tied to another register
   /// operand. The encoding of this field is described in the block comment
   /// before MachineInstr::tieOperands().
   unsigned char TiedTo : 4;
 
-  /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
-  /// operands.
-
   /// IsDef - True if this is a def, false if this is a use of the register.
+  /// This is only valid on register operands.
   ///
   bool IsDef : 1;
 
   /// IsImp - True if this is an implicit def or use, false if it is explicit.
+  /// This is only valid on register opderands.
   ///
   bool IsImp : 1;
 
-  /// IsKill - True if this instruction is the last use of the register on this
-  /// path through the function.  This is only valid on uses of registers.
-  bool IsKill : 1;
-
-  /// IsDead - True if this register is never used by a subsequent instruction.
-  /// This is only valid on definitions of registers.
-  bool IsDead : 1;
+  /// IsDeadOrKill
+  /// For uses: IsKill - True if this instruction is the last use of the
+  /// register on this path through the function.
+  /// For defs: IsDead - True if this register is never used by a subsequent
+  /// instruction.
+  /// This is only valid on register operands.
+  bool IsDeadOrKill : 1;
+
+  /// IsRenamable - True if this register may be renamed, i.e. it does not
+  /// generate a value that is somehow read in a way that is not represented by
+  /// the Machine IR (e.g. to meet an ABI or ISA requirement).  This is only
+  /// valid on physical register operands.  Virtual registers are assumed to
+  /// always be renamable regardless of the value of this field.
+  bool IsRenamable : 1;
 
   /// IsUndef - True if this register operand reads an "undef" value, i.e. the
   /// read value doesn't matter.  This flag can be set on both use and def
   /// operands.  On a sub-register def operand, it refers to the part of the
   /// register that isn't written.  On a full-register def operand, it is a
   /// noop.  See readsReg().
   ///
   /// This is only valid on registers.
public:
 
   bool isImplicit() const {
     assert(isReg() && "Wrong MachineOperand accessor");
     return IsImp;
   }
 
   bool isDead() const {
     assert(isReg() && "Wrong MachineOperand accessor");
-    return IsDead;
+    return IsDeadOrKill & IsDef;
   }
 
   bool isKill() const {
     assert(isReg() && "Wrong MachineOperand accessor");
-    return IsKill;
+    return IsDeadOrKill & !IsDef;
   }
 
   bool isUndef() const {
     assert(isReg() && "Wrong MachineOperand accessor");
     return IsUndef;
   }
 
+  bool isRenamable() const;
+
   bool isInternalRead() const {
     assert(isReg() && "Wrong MachineOperand accessor");
     return IsInternalRead;
   }
 
   bool isEarlyClobber() const {
     assert(isReg() && "Wrong MachineOperand accessor");
     return IsEarlyClobber;
public:
   void setImplicit(bool Val = true) {
     assert(isReg() && "Wrong MachineOperand mutator");
     IsImp = Val;
   }
 
   void setIsKill(bool Val = true) {
     assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
     assert((!Val || !isDebug()) && "Marking a debug operation as kill");
-    IsKill = Val;
+    IsDeadOrKill = Val;
   }
 
   void setIsDead(bool Val = true) {
     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
-    IsDead = Val;
+    IsDeadOrKill = Val;
   }
 
   void setIsUndef(bool Val = true) {
     assert(isReg() && "Wrong MachineOperand mutator");
     IsUndef = Val;
   }
 
+  void setIsRenamable(bool Val = true);
+
+  /// Set IsRenamable to true if there are no extra register allocation
+  /// requirements placed on this operand by the parent instruction's opcode.
+  void setIsRenamableIfNoExtraRegAllocReq();
+
   void setIsInternalRead(bool Val = true) {
     assert(isReg() && "Wrong MachineOperand mutator");
     IsInternalRead = Val;
   }
 
   void setIsEarlyClobber(bool Val = true) {
     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
     IsEarlyClobber = Val;
static MachineOperand CreateFPImm(const ConstantFP *CFP) {
     return Op;
   }
 
   static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
                                   bool isKill = false, bool isDead = false,
                                   bool isUndef = false,
                                   bool isEarlyClobber = false,
                                   unsigned SubReg = 0, bool isDebug = false,
-                                  bool isInternalRead = false) {
+                                  bool isInternalRead = false,
+                                  bool isRenamable = false) {
     assert(!(isDead && !isDef) && "Dead flag on non-def");
     assert(!(isKill && isDef) && "Kill flag on def");
     MachineOperand Op(MachineOperand::MO_Register);
     Op.IsDef = isDef;
     Op.IsImp = isImp;
-    Op.IsKill = isKill;
-    Op.IsDead = isDead;
+    Op.IsDeadOrKill = isKill | isDead;
+    Op.IsRenamable = isRenamable;
     Op.IsUndef = isUndef;
     Op.IsInternalRead = isInternalRead;
     Op.IsEarlyClobber = isEarlyClobber;
     Op.TiedTo = 0;
     Op.IsDebug = isDebug;
     Op.SmallContents.RegNo = Reg;
     Op.Contents.Reg.Prev = nullptr;
     Op.Contents.Reg.Next = nullptr;

llvm/trunk/lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     kw_def,
     kw_dead,
     kw_dereferenceable,
     kw_killed,
     kw_undef,
     kw_internal,
     kw_early_clobber,
     kw_debug_use,
+    kw_renamable,
     kw_tied_def,
     kw_frame_setup,
     kw_debug_location,
     kw_cfi_same_value,
     kw_cfi_offset,
     kw_cfi_def_cfa_register,
     kw_cfi_def_cfa_offset,
     kw_cfi_def_cfa,
bool isRegister() const {
     return Kind == NamedRegister || Kind == underscore ||
            Kind == VirtualRegister;
   }
 
   bool isRegisterFlag() const {
     return Kind == kw_implicit || Kind == kw_implicit_define ||
            Kind == kw_def || Kind == kw_dead || Kind == kw_killed ||
            Kind == kw_undef || Kind == kw_internal ||
-           Kind == kw_early_clobber || Kind == kw_debug_use;
+           Kind == kw_early_clobber || Kind == kw_debug_use ||
+           Kind == kw_renamable;
   }
 
   bool isMemoryOperandFlag() const {
     return Kind == kw_volatile || Kind == kw_non_temporal ||
            Kind == kw_dereferenceable || Kind == kw_invariant ||
            Kind == StringConstant;
   }
 

llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp

return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("implicit-def", MIToken::kw_implicit_define)
       .Case("def", MIToken::kw_def)
       .Case("dead", MIToken::kw_dead)
       .Case("killed", MIToken::kw_killed)
       .Case("undef", MIToken::kw_undef)
       .Case("internal", MIToken::kw_internal)
       .Case("early-clobber", MIToken::kw_early_clobber)
       .Case("debug-use", MIToken::kw_debug_use)
+      .Case("renamable", MIToken::kw_renamable)
       .Case("tied-def", MIToken::kw_tied_def)
       .Case("frame-setup", MIToken::kw_frame_setup)
       .Case("debug-location", MIToken::kw_debug_location)
       .Case("same_value", MIToken::kw_cfi_same_value)
       .Case("offset", MIToken::kw_cfi_offset)
       .Case("def_cfa_register", MIToken::kw_cfi_def_cfa_register)
       .Case("def_cfa_offset", MIToken::kw_cfi_def_cfa_offset)
       .Case("def_cfa", MIToken::kw_cfi_def_cfa)

llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp

case MIToken::kw_internal:
     Flags |= RegState::InternalRead;
     break;
   case MIToken::kw_early_clobber:
     Flags |= RegState::EarlyClobber;
     break;
   case MIToken::kw_debug_use:
     Flags |= RegState::Debug;
     break;
+  case MIToken::kw_renamable:
+    Flags |= RegState::Renamable;
+    break;
   default:
     llvm_unreachable("The current token should be a register flag");
   }
   if (OldFlags == Flags)
     // We know that the same flag is specified more than once when the flags
     // weren't modified.
     return error("duplicate '" + Token.stringValue() + "' register flag");
   lex();
if ((Flags & RegState::Define) == 0) {
     if (RegInfo->Kind == VRegInfo::GENERIC ||
         RegInfo->Kind == VRegInfo::REGBANK)
       return error("generic virtual registers must have a type");
   }
   Dest = MachineOperand::CreateReg(
       Reg, Flags & RegState::Define, Flags & RegState::Implicit,
       Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
       Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug,
-      Flags & RegState::InternalRead);
+      Flags & RegState::InternalRead, Flags & RegState::Renamable);
+
   return false;
 }
 
 bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
   assert(Token.is(MIToken::IntegerLiteral));
   const APSInt &Int = Token.integerValue();
   if (Int.getMinSignedBits() > 64)
     return error("integer literal is too large to be an immediate operand");
bool MIParser::parseMachineOperand(MachineOperand &Dest,
   case MIToken::kw_implicit_define:
   case MIToken::kw_def:
   case MIToken::kw_dead:
   case MIToken::kw_killed:
   case MIToken::kw_undef:
   case MIToken::kw_internal:
   case MIToken::kw_early_clobber:
   case MIToken::kw_debug_use:
+  case MIToken::kw_renamable:
   case MIToken::underscore:
   case MIToken::NamedRegister:
   case MIToken::VirtualRegister:
     return parseRegisterOperand(Dest, TiedDefIdx);
   case MIToken::IntegerLiteral:
     return parseImmediateOperand(Dest);
   case MIToken::IntegerType:
     return parseTypedImmediateOperand(Dest);

llvm/trunk/lib/CodeGen/MachineOperand.cpp

 }
 
 /// Change a def to a use, or a use to a def.
 void MachineOperand::setIsDef(bool Val) {
   assert(isReg() && "Wrong MachineOperand accessor");
   assert((!Val || !isDebug()) && "Marking a debug operation as def");
   if (IsDef == Val)
     return;
+  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
   // MRI may keep uses and defs in different list positions.
   if (MachineFunction *MF = getMFIfAvailable(*this)) {
     MachineRegisterInfo &MRI = MF->getRegInfo();
     MRI.removeRegOperandFromUseList(this);
     IsDef = Val;
     MRI.addRegOperandToUseList(this);
     return;
   }
   IsDef = Val;
 }
 
+bool MachineOperand::isRenamable() const {
+  assert(isReg() && "Wrong MachineOperand accessor");
+  assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
+         "isRenamable should only be checked on physical registers");
+  return IsRenamable;
+}
+
+void MachineOperand::setIsRenamable(bool Val) {
+  assert(isReg() && "Wrong MachineOperand accessor");
+  assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
+         "setIsRenamable should only be called on physical registers");
+  if (const MachineInstr *MI = getParent())
+    if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
+        (isUse() && MI->hasExtraSrcRegAllocReq()))
+      assert(!Val && "isRenamable should be false for "
+                     "hasExtraDefRegAllocReq/hasExtraSrcRegAllocReq opcodes");
+  IsRenamable = Val;
+}
+
+void MachineOperand::setIsRenamableIfNoExtraRegAllocReq() {
+  if (const MachineInstr *MI = getParent())
+    if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
+        (isUse() && MI->hasExtraSrcRegAllocReq()))
+      return;
+
+  setIsRenamable(true);
+}
+
 // If this operand is currently a register operand, and if this is in a
 // function, deregister the operand from the register's use/def list.
 void MachineOperand::removeRegFromUses() {
   if (!isReg() || !isOnRegUseList())
     return;
 
   if (MachineFunction *MF = getMFIfAvailable(*this))
     MF->getRegInfo().removeRegOperandFromUseList(this);
if (MachineFunction *MF = getMFIfAvailable(*this))
     RegInfo = &MF->getRegInfo();
   // If this operand is already a register operand, remove it from the
   // register's use/def lists.
   bool WasReg = isReg();
   if (RegInfo && WasReg)
     RegInfo->removeRegOperandFromUseList(this);
 
   // Change this to a register and set the reg#.
+  assert(!(isDead && !isDef) && "Dead flag on non-def");
+  assert(!(isKill && isDef) && "Kill flag on def");
   OpKind = MO_Register;
   SmallContents.RegNo = Reg;
   SubReg_TargetFlags = 0;
   IsDef = isDef;
   IsImp = isImp;
-  IsKill = isKill;
-  IsDead = isDead;
+  IsDeadOrKill = isKill | isDead;
+  IsRenamable = false;
   IsUndef = isUndef;
   IsInternalRead = false;
   IsEarlyClobber = false;
   IsDebug = isDebug;
   // Ensure isOnRegUseList() returns false.
   Contents.Reg.Prev = nullptr;
   // Preserve the tie when the operand was already a register.
   if (!WasReg)
case MachineOperand::MO_Register: {
     if (isKill())
       OS << "killed ";
     if (isUndef())
       OS << "undef ";
     if (isEarlyClobber())
       OS << "early-clobber ";
     if (isDebug())
       OS << "debug-use ";
+    if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
+      OS << "renamable ";
     OS << printReg(Reg, TRI);
     // Print the sub register.
     if (unsigned SubReg = getSubReg()) {
       if (TRI)
         OS << '.' << TRI->getSubRegIndexName(SubReg);
       else
         OS << ".subreg" << SubReg;
     }

llvm/trunk/lib/CodeGen/MachineVerifier.cpp

if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
               TII->getRegClass(MCID, MONum, TRI, *MF)) {
           if (!DRC->contains(Reg)) {
             report("Illegal physical register for instruction", MO, MONum);
             errs() << printReg(Reg, TRI) << " is not a "
                    << TRI->getRegClassName(DRC) << " register.\n";
           }
         }
       }
+      if (MO->isRenamable() &&
+          ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||
+           (MO->isUse() && MI->hasExtraSrcRegAllocReq()))) {
+        report("Illegal isRenamable setting for opcode with extra regalloc "
+               "requirements",
+               MO, MONum);
+        return;
+      }
     } else {
       // Virtual register.
       const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
       if (!RC) {
         // This is a generic virtual register.
 
         // If we're post-Select, we can't have gvregs anymore.
         if (isFunctionSelected) {

llvm/trunk/lib/CodeGen/RegAllocFast.cpp

 /// may invalidate any operand pointers.  Return true if the operand kills its
 /// register.
 bool RegAllocFast::setPhysReg(MachineInstr &MI, unsigned OpNum,
                               MCPhysReg PhysReg) {
   MachineOperand &MO = MI.getOperand(OpNum);
   bool Dead = MO.isDead();
   if (!MO.getSubReg()) {
     MO.setReg(PhysReg);
+    MO.setIsRenamableIfNoExtraRegAllocReq();
     return MO.isKill() || Dead;
   }
 
   // Handle subregister index.
   MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
+  MO.setIsRenamableIfNoExtraRegAllocReq();
   MO.setSubReg(0);
 
   // A kill flag implies killing the full register. Add corresponding super
   // register kill.
   if (MO.isKill()) {
     MI.addRegisterKilled(PhysReg, TRI, true);
     return true;
   }

llvm/trunk/lib/CodeGen/VirtRegMap.cpp

for (MachineBasicBlock::instr_iterator
           // PhysReg operands cannot have subregister indexes.
           PhysReg = TRI->getSubReg(PhysReg, SubReg);
           assert(PhysReg && "Invalid SubReg for physical register");
           MO.setSubReg(0);
         }
         // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
         // we need the inlining here.
         MO.setReg(PhysReg);
+        MO.setIsRenamableIfNoExtraRegAllocReq();
       }
 
       // Add any missing super-register kills after rewriting the whole
       // instruction.
       while (!SuperKills.empty())
         MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
 
       while (!SuperDeads.empty())

llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
   bool isThumb2 = Subtarget.isThumb2();
   const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
 
   DebugLoc dl = MI->getDebugLoc();
   MachineBasicBlock *BB = MI->getParent();
 
   MachineInstrBuilder LDM, STM;
   if (isThumb1 || !MI->getOperand(1).isDead()) {
+    MachineOperand LDWb(MI->getOperand(1));
+    LDWb.setIsRenamable(false);
     LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
                                                  : isThumb1 ? ARM::tLDMIA_UPD
                                                             : ARM::LDMIA_UPD))
-              .add(MI->getOperand(1));
+              .add(LDWb);
   } else {
     LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
   }
 
   if (isThumb1 || !MI->getOperand(0).isDead()) {
+    MachineOperand STWb(MI->getOperand(0));
+    STWb.setIsRenamable(false);
     STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
                                                  : isThumb1 ? ARM::tSTMIA_UPD
                                                             : ARM::STMIA_UPD))
-              .add(MI->getOperand(0));
+              .add(STWb);
   } else {
     STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
   }
 
-  LDM.add(MI->getOperand(3)).add(predOps(ARMCC::AL));
-  STM.add(MI->getOperand(2)).add(predOps(ARMCC::AL));
+  MachineOperand LDBase(MI->getOperand(3));
+  LDBase.setIsRenamable(false);
+  LDM.add(LDBase).add(predOps(ARMCC::AL));
+
+  MachineOperand STBase(MI->getOperand(2));
+  STBase.setIsRenamable(false);
+  STM.add(STBase).add(predOps(ARMCC::AL));
 
   // Sort the scratch registers into ascending order.
   const TargetRegisterInfo &TRI = getRegisterInfo();
   SmallVector<unsigned, 6> ScratchRegs;
   for(unsigned I = 5; I < MI->getNumOperands(); ++I)
     ScratchRegs.push_back(MI->getOperand(I).getReg());
   std::sort(ScratchRegs.begin(), ScratchRegs.end(),
             [&TRI](const unsigned &Reg1,

llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
   MachineInstr &MI = *MBBI;
   MachineBasicBlock &MBB = *MI.getParent();
 
   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
   unsigned OpIdx = 0;
 
   // Transfer the destination register operand.
   MIB.add(MI.getOperand(OpIdx++));
-  if (IsExt)
-    MIB.add(MI.getOperand(OpIdx++));
+  if (IsExt) {
+    MachineOperand VdSrc(MI.getOperand(OpIdx++));
+    VdSrc.setIsRenamable(false);
+    MIB.add(VdSrc);
+  }
 
   bool SrcIsKill = MI.getOperand(OpIdx).isKill();
   unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
   unsigned D0, D1, D2, D3;
   GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
   MIB.addReg(D0);
 
   // Copy the other source register operand.
-  MIB.add(MI.getOperand(OpIdx++));
+  MachineOperand VmSrc(MI.getOperand(OpIdx++));
+  VmSrc.setIsRenamable(false);
+  MIB.add(VmSrc);
 
   // Copy the predicate operands.
   MIB.add(MI.getOperand(OpIdx++));
   MIB.add(MI.getOperand(OpIdx++));
 
   // Add an implicit kill and use for the super-reg.
   MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
   TransferImpOps(MI, MIB, MIB);

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   switch (MI.getOpcode()) {
   default: {
     MI.print(errs());
     llvm_unreachable("Unexpected instr type to insert");
   }
 
   // Thumb1 post-indexed loads are really just single-register LDMs.
   case ARM::tLDR_postidx: {
+    MachineOperand Def(MI.getOperand(1));
+    if (TargetRegisterInfo::isPhysicalRegister(Def.getReg()))
+      Def.setIsRenamable(false);
     BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))
-        .add(MI.getOperand(1))  // Rn_wb
+        .add(Def)  // Rn_wb
         .add(MI.getOperand(2))  // Rn
         .add(MI.getOperand(3))  // PredImm
         .add(MI.getOperand(4))  // PredReg
         .add(MI.getOperand(0)); // Rt
     MI.eraseFromParent();
     return BB;
   }
 

llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 
 
 @G1 = common global [100 x i32] zeroinitializer, align 4
 @G2 = common global [100 x i32] zeroinitializer, align 4
 
 ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
 ;
 ; CHECK-LABEL: # Machine code for function foo:
-; CHECK: SU(2):   %w{{[0-9]+}}, %w{{[0-9]+}} = LDPWi
+; CHECK: SU(2):   renamable %w{{[0-9]+}}, renamable %w{{[0-9]+}} = LDPWi
 ; CHECK: Successors:
 ; CHECK-NOT: ch SU(4)
 ; CHECK: SU(3)
-; CHECK: SU(4):   STRWui %wzr, %x{{[0-9]+}}
+; CHECK: SU(4):   STRWui %wzr, renamable %x{{[0-9]+}}
 define i32 @foo() {
 entry:
   %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4
   %1 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 1), align 4
   store i32 0, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G1, i64 0, i64 0), align 4
   %add = add nsw i32 %1, %0
   ret i32 %add
 }

llvm/trunk/test/CodeGen/AMDGPU/shrink-carry.mir

 # RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: subbrev{{$}}
-# GCN:       V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec
+# GCN:       V_SUBBREV_U32_e64 0, undef %vgpr0, killed renamable %vcc, implicit %exec
 
 ---
 name:            subbrev
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
   - { id: 5, class: sreg_64_xexec }
 body:             |
   bb.0:
 
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
     %4, %5 = V_SUBBREV_U32_e64 0, %0, %3, implicit %exec
 
 ...
 
 # GCN-LABEL: name: subb{{$}}
-# GCN:       V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec
+# GCN:       V_SUBB_U32_e64 undef %vgpr0, 0, killed renamable %vcc, implicit %exec
 
 ---
 name:            subb
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
   - { id: 5, class: sreg_64_xexec }
 body:             |
   bb.0:
 
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
     %4, %5 = V_SUBB_U32_e64 %0, 0, %3, implicit %exec
 
 ...
 
 # GCN-LABEL: name: addc{{$}}
-# GCN:       V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
+# GCN:       V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
 
 ---
 name:            addc
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }
   - { id: 3, class: sreg_64_xexec }
   - { id: 4, class: vgpr_32 }
   - { id: 5, class: sreg_64_xexec }
 body:             |
   bb.0:
 
     %0 = IMPLICIT_DEF
     %1 = IMPLICIT_DEF
     %2 = IMPLICIT_DEF
     %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec
     %4, %5 = V_ADDC_U32_e64 0, %0, %3, implicit %exec
 
 ...
 
 # GCN-LABEL: name: addc2{{$}}
-# GCN:       V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
+# GCN:       V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
 
 ---
 name:            addc2
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: vgpr_32 }
   - { id: 2, class: vgpr_32 }

llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir

 ---
 # LiveRange splitting should split this into 2 intervals with the second getting
 # allocated to sgpr0_sgpr1 and the first to something else so we see two copies
 # in between for the two subregisters that are alive.
 # CHECK-LABEL: name: func1
 # CHECK: [[REG0:%sgpr[0-9]+]] = COPY %sgpr0
 # CHECK: [[REG1:%sgpr[0-9]+]] = COPY %sgpr2
 # CHECK: S_NOP 0
-# CHECK: S_NOP 0, implicit [[REG0]]
-# CHECK: S_NOP 0, implicit [[REG1]]
-# CHECK: %sgpr0 = COPY [[REG0]]
-# CHECK: %sgpr2 = COPY [[REG1]]
+# CHECK: S_NOP 0, implicit renamable [[REG0]]
+# CHECK: S_NOP 0, implicit renamable [[REG1]]
+# CHECK: %sgpr0 = COPY renamable [[REG0]]
+# CHECK: %sgpr2 = COPY renamable [[REG1]]
 # CHECK: S_NOP
-# CHECK: S_NOP 0, implicit %sgpr0
-# CHECK: S_NOP 0, implicit %sgpr2
+# CHECK: S_NOP 0, implicit renamable %sgpr0
+# CHECK: S_NOP 0, implicit renamable %sgpr2
 name: func1
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: %sgpr0, %sgpr1, %sgpr2
     undef %0.sub0 : sreg_128 = COPY %sgpr0
     %0.sub2 = COPY %sgpr2
 
     S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1
 
     S_NOP 0, implicit %0.sub0
     S_NOP 0, implicit %0.sub2
 
     ; Clobber everything but sgpr0-sgpr3
     S_NOP 0, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11, implicit-def dead %sgpr12, implicit-def dead %sgpr13, implicit-def dead %sgpr14, implicit-def dead %sgpr15, implicit-def dead %vcc_lo, implicit-def dead %vcc_hi
 
     S_NOP 0, implicit %0.sub0
     S_NOP 0, implicit %0.sub2
 ...
 ---
 # Check that copy hoisting out of loops works. This mainly should not crash the
 # compiler when it hoists a subreg copy sequence.
 # CHECK-LABEL: name: splitHoist
-# CHECK: S_NOP 0, implicit-def %sgpr0
-# CHECK: S_NOP 0, implicit-def %sgpr3
+# CHECK: S_NOP 0, implicit-def renamable %sgpr0
+# CHECK: S_NOP 0, implicit-def renamable %sgpr3
 # CHECK-NEXT: SI_SPILL_S128_SAVE
 name: splitHoist
 tracksRegLiveness: true
 body: |
   bb.0:
     successors: %bb.1, %bb.2
     S_NOP 0, implicit-def undef %0.sub0 : sreg_128
     S_NOP 0, implicit-def %0.sub3 : sreg_128

llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir

 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -stress-regalloc=1 -start-before=greedy -stop-after=stack-slot-coloring -o - %s | FileCheck  %s
 ---
 
 # CHECK-LABEL: name: no_merge_sgpr_vgpr_spill_slot{{$}}
 # CHECK: stack:
 # CHECK:   - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
 # CHECK-NEXT: stack-id: 0,
 
 # CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
 # CHECK-NEXT: stack-id: 1,
 
-# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)
+# CHECK: SI_SPILL_V32_SAVE killed renamable %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)
 # CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0)
 
-# CHECK: SI_SPILL_S32_SAVE killed %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)
+# CHECK: SI_SPILL_S32_SAVE killed renamable %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)
 # CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (load 4 from %stack.1)
 
 name: no_merge_sgpr_vgpr_spill_slot
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32 }
   - { id: 1, class: sreg_32_xm0_xexec }
   - { id: 2, class: vgpr_32 }

llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir

 # RUN: llc -o - %s -mtriple=amdgcn--amdhsa -verify-machineinstrs -run-pass=greedy,virtregrewriter | FileCheck %s
 --- |
 
   define amdgpu_kernel void @func0() {
     ret void
   }
 
 ...
 
 ---
 # We should not detect any interference between v0/v1 here and only allocate
 # sgpr0-sgpr3.
 #
 # CHECK-LABEL: func0
-# CHECK: S_NOP 0, implicit-def %sgpr0
-# CHECK: S_NOP 0, implicit-def %sgpr3
-# CHECK: S_NOP 0, implicit-def %sgpr1
-# CHECK: S_NOP 0, implicit-def %sgpr2
-# CHECK: S_NOP 0, implicit %sgpr0, implicit %sgpr3
-# CHECK: S_NOP 0, implicit %sgpr1, implicit %sgpr2
+# CHECK: S_NOP 0, implicit-def renamable %sgpr0
+# CHECK: S_NOP 0, implicit-def renamable %sgpr3
+# CHECK: S_NOP 0, implicit-def renamable %sgpr1
+# CHECK: S_NOP 0, implicit-def renamable %sgpr2
+# CHECK: S_NOP 0, implicit renamable %sgpr0, implicit renamable %sgpr3
+# CHECK: S_NOP 0, implicit renamable %sgpr1, implicit renamable %sgpr2
 name: func0
 body: |
   bb.0:
     S_NOP 0, implicit-def undef %0.sub0 : sreg_128
     S_NOP 0, implicit-def %0.sub3
     S_NOP 0, implicit-def undef %1.sub1 : sreg_128
     S_NOP 0, implicit-def %1.sub2
 
 
     S_NOP 0, implicit %0.sub0, implicit %0.sub3
     S_NOP 0, implicit %1.sub1, implicit %1.sub2
 ...

llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll

 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s
 
 ; GCN-LABEL: name: syncscopes
-; GCN: FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
-; GCN: FLAT_STORE_DWORD killed %vgpr4_vgpr5, killed %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
-; GCN: FLAT_STORE_DWORD killed %vgpr7_vgpr8, killed %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr1_vgpr2, killed renamable %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr4_vgpr5, killed renamable %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr7_vgpr8, killed renamable %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
 define void @syncscopes(
     i32 %agent,
     i32 addrspace(4)* %agent_out,
     i32 %workgroup,
     i32 addrspace(4)* %workgroup_out,
     i32 %wavefront,
     i32 addrspace(4)* %wavefront_out) {
 entry:
   store atomic i32 %agent, i32 addrspace(4)* %agent_out syncscope("agent") seq_cst, align 4
   store atomic i32 %workgroup, i32 addrspace(4)* %workgroup_out syncscope("workgroup") seq_cst, align 4
   store atomic i32 %wavefront, i32 addrspace(4)* %wavefront_out syncscope("wavefront") seq_cst, align 4
   ret void
 }

llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir

bb.0.entry:
     %59 = A2_tfrsi 524288
     undef %32.isub_hi = A2_tfrsi 0
     %8 = S2_extractup undef %9, 6, 25
     %47 = A2_tfrpi 2
     %13 = A2_tfrpi -1
     %13 = S2_asl_r_p_acc %13, %47, %8.isub_lo
     %51 = A2_tfrpi 0
 
-    ; CHECK: %d2 = S2_extractup undef %d0, 6, 25
+    ; CHECK: %d2 = S2_extractup undef renamable %d0, 6, 25
     ; CHECK: %d0 = A2_tfrpi 2
     ; CHECK: %d13 = A2_tfrpi -1
     ; CHECK-NOT: undef %r4
 
   bb.1.for.body:
     successors: %bb.3.for.end, %bb.2.if.end82
 
     ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29

llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir

+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses the 'renamable' register flags
+# correctly.
+
+--- |
+  define void @foo() { ret void }
+...
+---
+name:            foo
+body: |
+  ; CHECK: bb.0:
+  bb.0:
+    ; CHECK: renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    RETQ %eax
+...

llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll

 ; RUN: llc -verify-machineinstrs < %s -print-after=prologepilog >%t 2>&1 && FileCheck <%t %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 %struct.anon = type { i32, i32 }
 
 declare void @foo(%struct.anon* %v)
 define void @test(i32 %a, i32 %b, %struct.anon* byval nocapture %v) {
 entry:
   call void @foo(%struct.anon* %v)
   ret void
 }
 
 ; Make sure that the MMO on the store has no offset from the byval
 ; variable itself (we used to have mem:ST8[%v+64]).
-; CHECK: STD killed %x5, 176, %x1; mem:ST8[%v](align=16)
+; CHECK: STD killed renamable %x5, 176, %x1; mem:ST8[%v](align=16)
 

llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir

 name:            main
 alignment:       2
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: gr128bit }
   - { id: 1, class: gr64bit }
   - { id: 2, class: addr64bit }
 # CHECK: %r0q = L128
-# CHECK-NEXT: %r0l = COPY %r1l
+# CHECK-NEXT: %r0l = COPY renamable %r1l
 # Although R0L partially redefines R0Q, it must not mark R0Q as kill
 # because R1D is still live through that instruction.
 # CHECK-NOT: implicit killed %r0q
-# CHECK-NEXT: %r2d = COPY %r1d
+# CHECK-NEXT: %r2d = COPY renamable %r1d
 # CHECK-NEXT: LARL
 body:             |
   bb.0:
     %0.subreg_hl32 = COPY %0.subreg_l32
     %1 = COPY %0.subreg_l64
     %2 = LARL @g_167
     STC %1.subreg_l32, %2, 8, %noreg
 
 ...

llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll

 ; RUN: llc -stop-after=branch-folder < %s | FileCheck %s
 ;
 ; bb2 and bb3 in the IR below will be tail-merged into a single basic block.
 ; As br instructions in bb2 and bb3 have the same debug location, make sure that
 ; the branch instruction in the merged basic block still maintains the debug 
 ; location info.
 ; 
 ; CHECK:      [[DLOC:![0-9]+]] = !DILocation(line: 2, column: 2, scope: !{{[0-9]+}})
-; CHECK:      TEST64rr{{.*}}%rsi, %rsi, implicit-def %eflags
+; CHECK:      TEST64rr{{.*}}%rsi, renamable %rsi, implicit-def %eflags
 ; CHECK-NEXT: JNE_1{{.*}}, debug-location [[DLOC]]
 
 target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @foo(i1 %b, i8* %p) {
 bb1: 
   br i1 %b, label %bb2, label %bb3
 

llvm/trunk/test/DebugInfo/X86/pr34545.ll

 ; RUN: llc -O1 -filetype=asm -mtriple x86_64-unknown-linux-gnu -mcpu=x86-64 -o - %s -stop-after=livedebugvars | FileCheck %s
 
 ; CHECK: %eax = MOV32rm
 ; CHECK: DBG_VALUE %eax
-; CHECK: %eax = SHL32rCL killed %eax
+; CHECK: %eax = SHL32rCL killed renamable %eax
 ; CHECK: DBG_VALUE %eax
 ; CHECK: DBG_VALUE %rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus)
 ; CHECK: DBG_VALUE %eax
-; CHECK: %eax = SHL32rCL killed %eax
+; CHECK: %eax = SHL32rCL killed renamable %eax
 ; CHECK: DBG_VALUE %eax
 ; CHECK: RETQ %eax
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 @var = local_unnamed_addr global i32 8, !dbg !0
 @sc = local_unnamed_addr global i32 1, !dbg !6

llvm/trunk/test/DebugInfo/X86/sdag-salvage-add.ll

 ; instruction selection as it is folded into the load.
 ;
 ; CHECK:   ![[S4:.*]] = !DILocalVariable(name: "s4", 
 ; CHECK:   ![[MYVAR:.*]] = !DILocalVariable(name: "myVar", 
 ; CHECK:      DBG_VALUE debug-use %rax, debug-use %noreg, ![[MYVAR]],
 ; CHECK-SAME:           !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
 ; CHECK-NEXT: DBG_VALUE debug-use %rax, debug-use %noreg, ![[S4]],
 ; CHECK-SAME:           !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
-; CHECK-NEXT: %rdi = MOV64rm killed %rax, 1, %noreg, 4096, %noreg,
+; CHECK-NEXT: %rdi = MOV64rm killed renamable %rax, 1, %noreg, 4096, %noreg,
 
 source_filename = "test.c"
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.13.0"
 
 %struct.S3 = type { i64 }
 %struct.S4 = type opaque
 %struct.S0 = type opaque