WIP: [MachineOperand][MIR] Add isRenamable to MachineOperand.

[gberry]

Summary

Add isRenamable() predicate to MachineOperand. This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand. Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).

[gberry]

Update lit tests.

[gberry]

Ping.
This change should be in pretty good shape now, but the MI interface changes could use a good review.
I had to update quite a few MIR tests to add the 'norename' flag. A lot of these could probably be fixed by getting the relevant passes to set the norename flag more precisely, but I figured it would be better to do that in separate changes.

[MatzeB]

include/llvm/CodeGen/MachineOperand.h

88–90

Written like this it'll probably be part of the IsDef comment in doxygen. Maybe just append a "Only valid for MO_Register" to each of the four fields instead?

103

The last sentence is not true anymore.

106–110

One interesting discussion here is how "safe" things really are when this bit is set :)
I think AMDGPU for example has some extra constraints on physregs that the register allocator isn't aware of, they fix things in a separate pass after allocation AFAIK and after that you better not rename anymore. I think we currently set the ExtraSrcRegAllocReq and ExtraDefRegAllocReq on those machine instructions to indicate that. Then again we the infrastructure of this of this patch in place we could require them to clear the renamable flag on all affected operands.

107–109

Should we state that this bit only affects physical registers? That way we don't need to set this bit everywhere a vreg is used. And I can't imagine any case where we have a non-renamable vreg or put another way: I do not want to add code dealing with non-renamable vregs.

310–311

I assume changing this to assert(isReg() && IsDef()) breaks too much code?

368–372

See my comment in setReg(), I think we shouldn't have this method.

419

Maybe add assert(TargetRegisterInfo::isPhysicalRegister(getReg() && "Renamable flag may only be set for physregs");

lib/CodeGen/MIRParser/MIParser.cpp

1221

• "operands" instead of "MIR regs"?

lib/CodeGen/MIRParser/MIRParser.cpp

420–428

I'm not a fan of the parsing changing depending on a function property. I think the right thing to do is to encode "renamable" and not "norename" after all.

If you are worried about mir output becoming noisy/hard to read after regalloc with "renamable" flags everywhere, maybe we can shorten "renamable" to some character like ~?

lib/CodeGen/MachineInstr.cpp

90–91

I find it surprising that setReg() affects a flag as well. I'd rather just modify the regallocators to set the flag explicitely where possible.

lib/CodeGen/MachineVerifier.cpp

365–366

NoVRegs should mean exactly that: We are guaranteed that no vregs are used. It does not mean: We are in a pass after register allocation.

1209–1214

As stated above I would go for Renamable only ever being set on physregs. That way the rules don't need to be conditional based on "regsAllocated".

[gberry]

@MatzeB I have a new version that is much simpler that I believe addresses all of your points. I got rid of the context-dependent printing/parsing of the renamable flag (and changed it from 'norename') which ended up reducing the amount of lit test churn. I also restricted it to physical registers and tried to enforce the hasExtraRegAllocReq constraints, though that may not be complete.

include/llvm/CodeGen/MachineOperand.h

310–311

Yeah, I tried adding it and gave up after fixing it in about 5 different passes.

[gberry]

New version based on feedback from Matthias

[MatzeB]

Thanks, conditional LGTM.

My only remaining issue here is addOperand() changing operands. If you can easily fix this just commit without further review, otherwise at least write a comment on why you need it.

include/llvm/CodeGen/MachineOperand.h

106–110

I would still vote for a weaker language here by removing the word "safely".

lib/CodeGen/MachineInstr.cpp

1013–1018

Is this a good idea? Intuitively I would not expect an addOperand() function to change the operand. Admittedly someone already broke that rule with the setIsEarlyClobber() above but unless all other solutions are really bad, I'd still prefer not to have this here.

[MatzeB]

It would also be nice to pick a suitable test in test/CodeGen/MIR/X86 and add one line to ensure .mir prints/parses the flag correctly.

[gberry]

I made the comment less strong and added a test case. Let me know what you think about the addOperand issue.

lib/CodeGen/MachineInstr.cpp

1013–1018

Without this every bit of code that is builds an instruction whose opcode hasExtraRegAllocReq would need to remember to clear the appropriate renamable bit. It seems to me that the hasExtraRegAllocReq property is less useful that way. I suppose we could untie these two properties and ask that users check both the renamable bit and the hasExtraRegAllocReq (with a helper function), in which case the verification that the two properties are consistent goes away.

[gberry]

Made comment less strong and added MIR test case

[MatzeB]

lib/CodeGen/MachineInstr.cpp

1013–1018

But unless I miss something, the default is not-renamable anyway so all the random code out there doesn't need to be changed. The only places that set the renamable bit are the regallocators and they already use MO.setIsRenamableIfNoExtraRegAllocReq() in your commit. So what other code is there that would set the renamable bit even though it shouldn't?

[gberry]

lib/CodeGen/MachineInstr.cpp

1013–1018

One example that occurs in the lit tests is code that is constructing a hasExtraReqAllocReq machine instruction after register allocation and copying over operands from an existing instruction. These particular operands are renamable since they were originally virtual regs. Once they are added to the new instruction they remain renamable, but are operands of a hasExtraRegAllocReq opcode so they fail verification.

[MatzeB]

lib/CodeGen/MachineInstr.cpp

1013–1018

I assume that will be mostly (or all) AMDGPU code, is adjusting this code so hard that it justifies extra logic in a core function like addOperand()? At least we have the asserts in place and won't silently miscompile...

[gberry]

New version that doesn't force renamable flag to false for hasExtraRegAlloc opcodes in addOperand

[gberry]

lib/CodeGen/MachineInstr.cpp

1013–1018

I added a new version that removes this change to addOperand and fixes the lit test failures (which only showed up for ARM). I'm a bit concerned that this approach will break other targets/tests, but I suppose we can always revisit this later if it is a problem.

include/llvm/CodeGen/MachineOperand.h

private:
   /// For all other kinds of operands, this field holds target-specific flags.
   unsigned SubReg_TargetFlags : 12;
 
   /// TiedTo - Non-zero when this register operand is tied to another register
   /// operand. The encoding of this field is described in the block comment
   /// before MachineInstr::tieOperands().
   unsigned char TiedTo : 4;
 
-  /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
-  /// operands.
+  /// IsDef/IsImp/IsDeadOrKill/IsRenamable flags - These are
+  /// only valid for MO_Register opderands.
 
   /// IsDef - True if this is a def, false if this is a use of the register.
   ///
   bool IsDef : 1;
 
   /// IsImp - True if this is an implicit def or use, false if it is explicit.
   ///
   bool IsImp : 1;
 
-  /// IsKill - True if this instruction is the last use of the register on this
-  /// path through the function.  This is only valid on uses of registers.
-  bool IsKill : 1;
-
-  /// IsDead - True if this register is never used by a subsequent instruction.
-  /// This is only valid on definitions of registers.
-  bool IsDead : 1;
+  /// IsDeadOrKill
+  /// For uses: IsKill - True if this instruction is the last use of the
+  /// register on this path through the function.
+  /// For defs: IsDead - True if this register is never used by a subsequent
+  /// instruction.  This is only valid on definitions of registers.
+  bool IsDeadOrKill : 1;
+
+  /// IsRenamable - True if this register may be safely renamed,
+  /// i.e. that it does not generate a value that is somehow read in a way that
+  /// is not represented by the Machine IR (e.g. to meet an ABI or ISA
+  /// requirement).
+  bool IsRenamable : 1;
 
   /// IsUndef - True if this register operand reads an "undef" value, i.e. the
   /// read value doesn't matter.  This flag can be set on both use and def
   /// operands.  On a sub-register def operand, it refers to the part of the
   /// register that isn't written.  On a full-register def operand, it is a
   /// noop.  See readsReg().
   ///
   /// This is only valid on registers.
public:
   }
 
   bool isImplicit() const {
     assert(isReg() && "Wrong MachineOperand accessor");
     return IsImp;
   }
 
   bool isDead() const {
     assert(isReg() && "Wrong MachineOperand accessor");
-    return IsDead;
+    return IsDeadOrKill & IsDef;
   }
 
   bool isKill() const {
     assert(isReg() && "Wrong MachineOperand accessor");
-    return IsKill;
+    return IsDeadOrKill & !IsDef;
   }
 
   bool isUndef() const {
     assert(isReg() && "Wrong MachineOperand accessor");
     return IsUndef;
   }
 
+  bool isRenamable() const {
+    assert(isReg() && "Wrong MachineOperand accessor");
+    return IsRenamable;
+  }
+
   bool isInternalRead() const {
     assert(isReg() && "Wrong MachineOperand accessor");
     return IsInternalRead;
   }
 
   bool isEarlyClobber() const {
     assert(isReg() && "Wrong MachineOperand accessor");
     return IsEarlyClobber;
public:
 
   //===--------------------------------------------------------------------===//
   // Mutators for Register Operands
   //===--------------------------------------------------------------------===//
 
   /// Change the register this operand corresponds to.
   ///
   void setReg(unsigned Reg);
+  /// Same as setReg() above, but preserves the current value of isRenamable().
+  /// This allows e.g. the register allocators to create physical register
+  /// operands that are marked as being renamable if they were virtual registers
+  /// before allocation.
+  void setRegKeepRenamable(unsigned Reg);
 
   void setSubReg(unsigned subReg) {
     assert(isReg() && "Wrong MachineOperand mutator");
     SubReg_TargetFlags = subReg;
     assert(SubReg_TargetFlags == subReg && "SubReg out of range");
   }
 
   /// substVirtReg - Substitute the current register with the virtual
public:
   void setImplicit(bool Val = true) {
     assert(isReg() && "Wrong MachineOperand mutator");
     IsImp = Val;
   }
 
   void setIsKill(bool Val = true) {
     assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
     assert((!Val || !isDebug()) && "Marking a debug operation as kill");
-    IsKill = Val;
+    IsDeadOrKill = Val;
   }
 
   void setIsDead(bool Val = true) {
     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
-    IsDead = Val;
+    IsDeadOrKill = Val;
   }
 
   void setIsUndef(bool Val = true) {
     assert(isReg() && "Wrong MachineOperand mutator");
     IsUndef = Val;
   }
 
+  void setIsRenamable(bool Val = true) {
+    assert(isReg() && "Wrong MachineOperand mutator");
+    IsRenamable = Val;
+  }
+
   void setIsInternalRead(bool Val = true) {
     assert(isReg() && "Wrong MachineOperand mutator");
     IsInternalRead = Val;
   }
 
   void setIsEarlyClobber(bool Val = true) {
     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
     IsEarlyClobber = Val;
public:
   }
 
   static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
                                   bool isKill = false, bool isDead = false,
                                   bool isUndef = false,
                                   bool isEarlyClobber = false,
                                   unsigned SubReg = 0,
                                   bool isDebug = false,
-                                  bool isInternalRead = false) {
-    assert(!(isDead && !isDef) && "Dead flag on non-def");
-    assert(!(isKill && isDef) && "Kill flag on def");
-    MachineOperand Op(MachineOperand::MO_Register);
-    Op.IsDef = isDef;
-    Op.IsImp = isImp;
-    Op.IsKill = isKill;
-    Op.IsDead = isDead;
-    Op.IsUndef = isUndef;
-    Op.IsInternalRead = isInternalRead;
-    Op.IsEarlyClobber = isEarlyClobber;
-    Op.TiedTo = 0;
-    Op.IsDebug = isDebug;
-    Op.SmallContents.RegNo = Reg;
-    Op.Contents.Reg.Prev = nullptr;
-    Op.Contents.Reg.Next = nullptr;
-    Op.setSubReg(SubReg);
-    return Op;
-  }
+                                  bool isInternalRead = false);
   static MachineOperand CreateMBB(MachineBasicBlock *MBB,
                                   unsigned char TargetFlags = 0) {
     MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
     Op.setMBB(MBB);
     Op.setTargetFlags(TargetFlags);
     return Op;
   }
   static MachineOperand CreateFI(int Idx) {

lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
 
     // Keywords
     kw_implicit,
     kw_implicit_define,
     kw_def,
     kw_dead,
     kw_dereferenceable,
     kw_killed,
+    kw_norename,
     kw_undef,
     kw_internal,
     kw_early_clobber,
     kw_debug_use,
     kw_tied_def,
     kw_frame_setup,
     kw_debug_location,
     kw_cfi_same_value,
public:
   bool isRegister() const {
     return Kind == NamedRegister || Kind == underscore ||
            Kind == VirtualRegister;
   }
 
   bool isRegisterFlag() const {
     return Kind == kw_implicit || Kind == kw_implicit_define ||
            Kind == kw_def || Kind == kw_dead || Kind == kw_killed ||
-           Kind == kw_undef || Kind == kw_internal ||
+           Kind == kw_norename || Kind == kw_undef || Kind == kw_internal ||
            Kind == kw_early_clobber || Kind == kw_debug_use;
   }
 
   bool isMemoryOperandFlag() const {
     return Kind == kw_volatile || Kind == kw_non_temporal ||
            Kind == kw_dereferenceable || Kind == kw_invariant ||
            Kind == StringConstant;
   }

lib/CodeGen/MIRParser/MILexer.cpp

 static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
   return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("_", MIToken::underscore)
       .Case("implicit", MIToken::kw_implicit)
       .Case("implicit-def", MIToken::kw_implicit_define)
       .Case("def", MIToken::kw_def)
       .Case("dead", MIToken::kw_dead)
       .Case("killed", MIToken::kw_killed)
+      .Case("norename", MIToken::kw_norename)
       .Case("undef", MIToken::kw_undef)
       .Case("internal", MIToken::kw_internal)
       .Case("early-clobber", MIToken::kw_early_clobber)
       .Case("debug-use", MIToken::kw_debug_use)
       .Case("tied-def", MIToken::kw_tied_def)
       .Case("frame-setup", MIToken::kw_frame_setup)
       .Case("debug-location", MIToken::kw_debug_location)
       .Case("same_value", MIToken::kw_cfi_same_value)

lib/CodeGen/MIRParser/MIParser.cpp

public:
   bool parseBasicBlock(MachineBasicBlock &MBB,
                        MachineBasicBlock *&AddFalthroughFrom);
   bool parseBasicBlockLiveins(MachineBasicBlock &MBB);
   bool parseBasicBlockSuccessors(MachineBasicBlock &MBB);
 
   bool parseNamedRegister(unsigned &Reg);
   bool parseVirtualRegister(VRegInfo *&Info);
   bool parseRegister(unsigned &Reg, VRegInfo *&VRegInfo);
-  bool parseRegisterFlag(unsigned &Flags);
+  bool parseRegisterFlag(unsigned &Flags, bool &NoRename);
   bool parseRegisterClassOrBank(VRegInfo &RegInfo);
   bool parseSubRegisterIndex(unsigned &SubReg);
   bool parseRegisterTiedDefIndex(unsigned &TiedDefIdx);
   bool parseRegisterOperand(MachineOperand &Dest,
                             Optional<unsigned> &TiedDefIdx, bool IsDef = false);
   bool parseImmediateOperand(MachineOperand &Dest);
   bool parseIRConstant(StringRef::iterator Loc, StringRef Source,
                        const Constant *&C);
case VRegInfo::REGBANK:
     return false;
 
   case VRegInfo::NORMAL:
     return error(Loc, "register bank specification on normal register");
   }
   llvm_unreachable("Unexpected register kind");
 }
 
-bool MIParser::parseRegisterFlag(unsigned &Flags) {
+bool MIParser::parseRegisterFlag(unsigned &Flags, bool &NoRename) {
   const unsigned OldFlags = Flags;
   switch (Token.kind()) {
   case MIToken::kw_implicit:
     Flags |= RegState::Implicit;
     break;
   case MIToken::kw_implicit_define:
     Flags |= RegState::ImplicitDefine;
     break;
   case MIToken::kw_def:
     Flags |= RegState::Define;
     break;
   case MIToken::kw_dead:
     Flags |= RegState::Dead;
     break;
   case MIToken::kw_killed:
     Flags |= RegState::Kill;
     break;
+  case MIToken::kw_norename:
+    NoRename = true;
+    break;
   case MIToken::kw_undef:
     Flags |= RegState::Undef;
     break;
   case MIToken::kw_internal:
     Flags |= RegState::InternalRead;
     break;
   case MIToken::kw_early_clobber:
     Flags |= RegState::EarlyClobber;
bool MIParser::assignRegisterTies(MachineInstr &MI,
   for (const auto &TiedPair : TiedRegisterPairs)
     MI.tieOperands(TiedPair.first, TiedPair.second);
   return false;
 }
 
 bool MIParser::parseRegisterOperand(MachineOperand &Dest,
                                     Optional<unsigned> &TiedDefIdx,
                                     bool IsDef) {
+  bool NoRename = false;
   unsigned Flags = IsDef ? RegState::Define : 0;
   while (Token.isRegisterFlag()) {
-    if (parseRegisterFlag(Flags))
+    if (parseRegisterFlag(Flags, NoRename))
       return true;
   }
   if (!Token.isRegister())
     return error("expected a register after register flags");
   unsigned Reg;
   VRegInfo *RegInfo;
   if (parseRegister(Reg, RegInfo))
     return true;
if (RegInfo->Kind == VRegInfo::GENERIC ||
         RegInfo->Kind == VRegInfo::REGBANK)
       return error("generic virtual registers must have a type");
   }
   Dest = MachineOperand::CreateReg(
       Reg, Flags & RegState::Define, Flags & RegState::Implicit,
       Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
       Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug,
       Flags & RegState::InternalRead);
+
+  // Mark MIR regs as renamable unless they are explicitly marked norename.  We
+  // will later go back through and fix up all the physical regs to be marked as
+  // not renamable if we are reading a MIR file with NoVRegs not set (i.e. from
+  // before register allocation.
+  if (!NoRename)
+    Dest.setIsRenamable(true);
   return false;
 }
 
 bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
   assert(Token.is(MIToken::IntegerLiteral));
   const APSInt &Int = Token.integerValue();
   if (Int.getMinSignedBits() > 64)
     return error("integer literal is too large to be an immediate operand");

 bool MIParser::parseMachineOperand(MachineOperand &Dest,
                                    Optional<unsigned> &TiedDefIdx) {
   switch (Token.kind()) {
   case MIToken::kw_implicit:
   case MIToken::kw_implicit_define:
   case MIToken::kw_def:
   case MIToken::kw_dead:
   case MIToken::kw_killed:
+  case MIToken::kw_norename:
   case MIToken::kw_undef:
   case MIToken::kw_internal:
   case MIToken::kw_early_clobber:
   case MIToken::kw_debug_use:
   case MIToken::underscore:
   case MIToken::NamedRegister:
   case MIToken::VirtualRegister:
     return parseRegisterOperand(Dest, TiedDefIdx);

lib/CodeGen/MIRParser/MIRParser.cpp

MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
   }
   PFS.SM = &SM;
 
   if (setupRegisterInfo(PFS, YamlMF))
     return true;
 
   computeFunctionProperties(MF);
 
+  // Fix up physical registers to be marked as norename if we are reading a
+  // MIR file with NoVRegs not set (i.e. from before register allocation).
+  if (!MF.getProperties().hasProperty(
+          MachineFunctionProperties::Property::NoVRegs))
+    for (auto &MBB : MF)
+      for (auto &MI : MBB.instrs())
+        for (auto &MO : MI.operands())
+          if (MO.isReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
+            MO.setIsRenamable(false);
+
   MF.verify();
   return false;
 }
 
 bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
                                       const yaml::MachineFunction &YamlMF) {
   MachineFunction &MF = PFS.MF;
   MachineRegisterInfo &RegInfo = MF.getRegInfo();

lib/CodeGen/MIRPrinter.cpp

 /// This class prints out the machine functions using the MIR serialization
 /// format.
 class MIRPrinter {
   raw_ostream &OS;
   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
   /// Maps from stack object indices to operand indices which will be used when
   /// printing frame index machine operands.
   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
+  bool ShouldPrintIsRenamable;
 
 public:
-  MIRPrinter(raw_ostream &OS) : OS(OS) {}
+  MIRPrinter(raw_ostream &OS) : OS(OS), ShouldPrintIsRenamable(false) {}
 
   void print(const MachineFunction &MF);
 
   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
                const TargetRegisterInfo *TRI);
   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
                const MachineFrameInfo &MFI);
   void convert(yaml::MachineFunction &MF,

 /// format.
 class MIPrinter {
   raw_ostream &OS;
   ModuleSlotTracker &MST;
   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
   /// Synchronization scope names registered with LLVMContext.
   SmallVector<StringRef, 8> SSNs;
+  bool ShouldPrintIsRenamable;
 
   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
 
 public:
   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
-            const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
+            const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping,
+            bool ShouldPrintIsRenamable)
       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
-        StackObjectOperandMapping(StackObjectOperandMapping) {}
+        StackObjectOperandMapping(StackObjectOperandMapping),
+        ShouldPrintIsRenamable(ShouldPrintIsRenamable) {}
 
   void print(const MachineBasicBlock &MBB);
 
   void print(const MachineInstr &MI);
   void printMBBReference(const MachineBasicBlock &MBB);
   void printIRBlockReference(const BasicBlock &BB);
   void printIRValueReference(const Value &V);
   void printStackObjectReference(int FrameIndex);
void MIRPrinter::print(const MachineFunction &MF) {
   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
 
   YamlMF.Legalized = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Legalized);
   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::RegBankSelected);
   YamlMF.Selected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Selected);
+  ShouldPrintIsRenamable = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::NoVRegs);
 
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   ModuleSlotTracker MST(MF.getFunction()->getParent());
   MST.incorporateFunction(*MF.getFunction());
   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
   convertStackObjects(YamlMF, MF, MST);
   if (const auto *ConstantPool = MF.getConstantPool())
     convert(YamlMF, *ConstantPool);
   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
   bool IsNewlineNeeded = false;
   for (const auto &MBB : MF) {
     if (IsNewlineNeeded)
       StrOS << "\n";
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+              ShouldPrintIsRenamable)
         .print(MBB);
     IsNewlineNeeded = true;
   }
   StrOS.flush();
   yaml::Output Out(OS);
   if (!SimplifyMIR)
       Out.setWriteDefaultValues(true);
   Out << YamlMF;
void MIRPrinter::convert(ModuleSlotTracker &MST,
   YamlMFI.HasCalls = MFI.hasCalls();
   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
     ? MFI.getMaxCallFrameSize() : ~0u;
   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
   YamlMFI.HasVAStart = MFI.hasVAStart();
   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
   if (MFI.getSavePoint()) {
     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+              ShouldPrintIsRenamable)
         .printMBBReference(*MFI.getSavePoint());
   }
   if (MFI.getRestorePoint()) {
     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+              ShouldPrintIsRenamable)
         .printMBBReference(*MFI.getRestorePoint());
   }
 }
 
 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
                                      const MachineFunction &MF,
                                      ModuleSlotTracker &MST) {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
   }
 
   // Print the stack object references in the frame information class after
   // converting the stack objects.
   if (MFI.hasStackProtectorIndex()) {
     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+              ShouldPrintIsRenamable)
         .printStackObjectReference(MFI.getStackProtectorIndex());
   }
 
   // Print the debug variable information.
   for (const MachineFunction::VariableDbgInfo &DebugVar :
        MF.getVariableDbgInfo()) {
     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
void MIRPrinter::convert(ModuleSlotTracker &MST,
   YamlJTI.Kind = JTI.getEntryKind();
   unsigned ID = 0;
   for (const auto &Table : JTI.getJumpTables()) {
     std::string Str;
     yaml::MachineJumpTable::Entry Entry;
     Entry.ID = ID++;
     for (const auto *MBB : Table.MBBs) {
       raw_string_ostream StrOS(Str);
-      MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+      MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+                ShouldPrintIsRenamable)
           .printMBBReference(*MBB);
       Entry.Blocks.push_back(StrOS.str());
       Str.clear();
     }
     YamlJTI.Entries.push_back(Entry);
   }
 }
 
else if (!IsDef && Op.isDef())
       // Print the 'def' flag only when the operand is defined after '='.
       OS << "def ";
     if (Op.isInternalRead())
       OS << "internal ";
     if (Op.isDead())
       OS << "dead ";
     if (Op.isKill())
       OS << "killed ";
+    if (ShouldPrintIsRenamable && !Op.isRenamable())
+      OS << "norename ";
     if (Op.isUndef())
       OS << "undef ";
     if (Op.isEarlyClobber())
       OS << "early-clobber ";
     if (Op.isDebug())
       OS << "debug-use ";
     printReg(Reg, OS, TRI);
     // Print the sub register.

lib/CodeGen/MachineInstr.cpp

 
 //===----------------------------------------------------------------------===//
 // MachineOperand Implementation
 //===----------------------------------------------------------------------===//
 
 void MachineOperand::setReg(unsigned Reg) {
   if (getReg() == Reg) return; // No change.
 
+  IsRenamable = !TargetRegisterInfo::isPhysicalRegister(Reg);
+
   // Otherwise, we have to change the register.  If this operand is embedded
   // into a machine function, we need to update the old and new register's
   // use/def lists.
   if (MachineInstr *MI = getParent())
     if (MachineBasicBlock *MBB = MI->getParent())
       if (MachineFunction *MF = MBB->getParent()) {
         MachineRegisterInfo &MRI = MF->getRegInfo();
         MRI.removeRegOperandFromUseList(this);
         SmallContents.RegNo = Reg;
         MRI.addRegOperandToUseList(this);
         return;
       }
 
   // Otherwise, just change the register, no problem.  :)
   SmallContents.RegNo = Reg;
 }
 
+void MachineOperand::setRegKeepRenamable(unsigned Reg) {
+  bool SaveIsRenamable = IsRenamable;
+  setReg(Reg);
+  IsRenamable = SaveIsRenamable;
+}
+
 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
                                   const TargetRegisterInfo &TRI) {
   assert(TargetRegisterInfo::isVirtualRegister(Reg));
   if (SubIdx && getSubReg())
     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
   setReg(Reg);
   if (SubIdx)
     setSubReg(SubIdx);

 }
 
 /// Change a def to a use, or a use to a def.
 void MachineOperand::setIsDef(bool Val) {
   assert(isReg() && "Wrong MachineOperand accessor");
   assert((!Val || !isDebug()) && "Marking a debug operation as def");
   if (IsDef == Val)
     return;
+  assert(!IsDeadOrKill && "Changing operand from def to use or vice-versa "
+                          "destroys IsDead/IsKill setting");
   // MRI may keep uses and defs in different list positions.
   if (MachineInstr *MI = getParent())
     if (MachineBasicBlock *MBB = MI->getParent())
       if (MachineFunction *MF = MBB->getParent()) {
         MachineRegisterInfo &MRI = MF->getRegInfo();
         MRI.removeRegOperandFromUseList(this);
         IsDef = Val;
         MRI.addRegOperandToUseList(this);
if (MachineBasicBlock *MBB = MI->getParent())
         RegInfo = &MF->getRegInfo();
   // If this operand is already a register operand, remove it from the
   // register's use/def lists.
   bool WasReg = isReg();
   if (RegInfo && WasReg)
     RegInfo->removeRegOperandFromUseList(this);
 
   // Change this to a register and set the reg#.
+  assert(!(isDead && !isDef) && "Dead flag on non-def");
+  assert(!(isKill && isDef) && "Kill flag on def");
   OpKind = MO_Register;
   SmallContents.RegNo = Reg;
   SubReg_TargetFlags = 0;
   IsDef = isDef;
   IsImp = isImp;
-  IsKill = isKill;
-  IsDead = isDead;
+  IsDeadOrKill = isKill | isDead;
+  IsRenamable = !TargetRegisterInfo::isPhysicalRegister(Reg);
   IsUndef = isUndef;
   IsInternalRead = false;
   IsEarlyClobber = false;
   IsDebug = isDebug;
   // Ensure isOnRegUseList() returns false.
   Contents.Reg.Prev = nullptr;
   // Preserve the tie when the operand was already a register.
   if (!WasReg)
     TiedTo = 0;
 
   // If this operand is embedded in a function, add the operand to the
   // register's use/def list.
   if (RegInfo)
     RegInfo->addRegOperandToUseList(this);
 }
 
+MachineOperand MachineOperand::CreateReg(unsigned Reg, bool isDef, bool isImp,
+                                         bool isKill, bool isDead, bool isUndef,
+                                         bool isEarlyClobber, unsigned SubReg,
+                                         bool isDebug, bool isInternalRead) {
+  assert(!(isDead && !isDef) && "Dead flag on non-def");
+  assert(!(isKill && isDef) && "Kill flag on def");
+  MachineOperand Op(MachineOperand::MO_Register);
+  Op.IsDef = isDef;
+  Op.IsImp = isImp;
+  Op.IsDeadOrKill = isKill | isDead;
+  Op.IsRenamable = !TargetRegisterInfo::isPhysicalRegister(Reg);
+  Op.IsUndef = isUndef;
+  Op.IsInternalRead = isInternalRead;
+  Op.IsEarlyClobber = isEarlyClobber;
+  Op.TiedTo = 0;
+  Op.IsDebug = isDebug;
+  Op.SmallContents.RegNo = Reg;
+  Op.Contents.Reg.Prev = nullptr;
+  Op.Contents.Reg.Next = nullptr;
+  Op.setSubReg(SubReg);
+  return Op;
+}
+
 /// isIdenticalTo - Return true if this operand is identical to the specified
 /// operand. Note that this should stay in sync with the hash_value overload
 /// below.
 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
   if (getType() != Other.getType() ||
       getTargetFlags() != Other.getTargetFlags())
     return false;
 

 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
                            const TargetRegisterInfo *TRI,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
   switch (getType()) {
   case MachineOperand::MO_Register:
     OS << PrintReg(getReg(), TRI, getSubReg());
 
     if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
-        isInternalRead() || isEarlyClobber() || isTied()) {
+        isInternalRead() || isEarlyClobber() || isTied() || !isRenamable()) {
       OS << '<';
       bool NeedComma = false;
       if (isDef()) {
         if (NeedComma) OS << ',';
         if (isEarlyClobber())
           OS << "earlyclobber,";
         if (isImplicit())
           OS << "imp-";
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
         OS << "kill";
         NeedComma = true;
       }
       if (isDead()) {
         if (NeedComma) OS << ',';
         OS << "dead";
         NeedComma = true;
       }
+      if (!isRenamable()) {
+        if (NeedComma) OS << ',';
+        OS << "norename";
+        NeedComma = true;
+      }
       if (isUndef() && isUse()) {
         if (NeedComma) OS << ',';
         OS << "undef";
         NeedComma = true;
       }
       if (isInternalRead()) {
         if (NeedComma) OS << ',';
         OS << "internal";
if (!isImpReg) {
         int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
         if (DefIdx != -1)
           tieOperands(DefIdx, OpNo);
       }
       // If the register operand is flagged as early, mark the operand as such.
       if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
         NewMO->setIsEarlyClobber(true);
     }
   }
 }
 
 /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
 /// fewer operand than it started with.
 ///
 void MachineInstr::RemoveOperand(unsigned OpNo) {
   assert(OpNo < getNumOperands() && "Invalid operand number");
   untieRegOperand(OpNo);
 
 #ifndef NDEBUG
   // Moving tied operands would break the ties.
   for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
     if (Operands[i].isReg())

lib/CodeGen/MachineVerifier.cpp

struct MachineVerifier {
     const TargetRegisterInfo *TRI;
     const MachineRegisterInfo *MRI;
 
     unsigned foundErrors;
 
     // Avoid querying the MachineFunctionProperties for each operand.
     bool isFunctionRegBankSelected;
     bool isFunctionSelected;
+    bool areRegsAllocated;
 
     using RegVector = SmallVector<unsigned, 16>;
     using RegMaskVector = SmallVector<const uint32_t *, 4>;
     using RegSet = DenseSet<unsigned>;
     using RegMap = DenseMap<unsigned, const MachineInstr *>;
     using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
 
     const MachineInstr *FirstTerminator;
for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
     Last = I->first;
   }
 }
 
 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
   // If a pass has introduced virtual registers without clearing the
   // NoVRegs property (or set it without allocating the vregs)
   // then report an error.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::NoVRegs) &&
-      MRI->getNumVirtRegs())
+  if (areRegsAllocated && MRI->getNumVirtRegs())
     report("Function has NoVRegs property but there are VReg operands", &MF);
 }
 
 unsigned MachineVerifier::verify(MachineFunction &MF) {
   foundErrors = 0;
 
   this->MF = &MF;
   TM = &MF.getTarget();
   TII = MF.getSubtarget().getInstrInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
 
   isFunctionRegBankSelected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::RegBankSelected);
   isFunctionSelected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Selected);
+  areRegsAllocated = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::NoVRegs);
 
   LiveVars = nullptr;
   LiveInts = nullptr;
   LiveStks = nullptr;
   Indexes = nullptr;
   if (PASS) {
     LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
     // We don't want to verify LiveVariables if LiveIntervals is available.
if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
             report("Illegal virtual register for instruction", MO, MONum);
             errs() << "Expected a " << TRI->getRegClassName(DRC)
                 << " register, but got a " << TRI->getRegClassName(RC)
                 << " register\n";
           }
         }
       }
     }
+
+    // Check isRenamable is correct if we're before RA.
+    if (!areRegsAllocated)
+      if (MO->isRenamable() != TargetRegisterInfo::isVirtualRegister(Reg))
+        report("Virtual registers should be marked isRenamable and physical "
+               "registers should not be.",
+               MO, MONum);
+
     break;
   }
 
   case MachineOperand::MO_RegisterMask:
     regMasks.push_back(MO->getRegMask());
     break;
 
   case MachineOperand::MO_MachineBasicBlock:

lib/CodeGen/RegAllocFast.cpp

 /// Changes operand OpNum in MI the refer the PhysReg, considering subregs. This
 /// may invalidate any operand pointers.  Return true if the operand kills its
 /// register.
 bool RegAllocFast::setPhysReg(MachineInstr &MI, unsigned OpNum,
                               MCPhysReg PhysReg) {
   MachineOperand &MO = MI.getOperand(OpNum);
   bool Dead = MO.isDead();
   if (!MO.getSubReg()) {
-    MO.setReg(PhysReg);
+    MO.setRegKeepRenamable(PhysReg);
     return MO.isKill() || Dead;
   }
 
   // Handle subregister index.
-  MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
+  MO.setRegKeepRenamable(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
   MO.setSubReg(0);
 
   // A kill flag implies killing the full register. Add corresponding super
   // register kill.
   if (MO.isKill()) {
     MI.addRegisterKilled(PhysReg, TRI, true);
     return true;
   }

lib/CodeGen/VirtRegMap.cpp

for (MachineBasicBlock::instr_iterator
 
           // PhysReg operands cannot have subregister indexes.
           PhysReg = TRI->getSubReg(PhysReg, SubReg);
           assert(PhysReg && "Invalid SubReg for physical register");
           MO.setSubReg(0);
         }
         // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
         // we need the inlining here.
-        MO.setReg(PhysReg);
+        MO.setRegKeepRenamable(PhysReg);
       }
 
       // Add any missing super-register kills after rewriting the whole
       // instruction.
       while (!SuperKills.empty())
         MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
 
       while (!SuperDeads.empty())

test/CodeGen/AArch64/arm64-csldst-mmo.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ; REQUIRES: asserts
 
 @G = external global [0 x i32], align 4
 
 ; Check that MMOs are added to epilogue calle-save restore loads so
 ; that the store to G is not considered dependant on the callee-save
 ; loads.
 ;
 ; CHECK: Before post-MI-sched:
 ; CHECK-LABEL: # Machine code for function test1:
 ; CHECK: SU(2):   STRWui %WZR
-; CHECK: SU(3):   %X21<def>, %X20<def> = LDPXi %SP
+; CHECK: SU(3):   %X21<def,norename>, %X20<def,norename> = LDPXi %SP
 ; CHECK:  Predecessors:
 ; CHECK-NEXT:   SU(0): Out
 ; CHECK-NEXT:   SU(0): Out
 ; CHECK-NEXT:   SU(0): Ord
 ; CHECK-NEXT:  Successors:
 define void @test1() {
 entry:
   tail call void asm sideeffect "nop", "~{x20},~{x21},~{x22},~{x23}"() nounwind
   store i32 0, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @G, i64 0, i64 0), align 4
   ret void
 }

test/CodeGen/AArch64/arm64-misched-memdep-bug.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ;
 ; Test for bug in misched memory dependency calculation.
 ;
 ; CHECK: ********** MI Scheduling **********
 ; CHECK: misched_bug:BB#0 entry
 ; CHECK: SU(2):   %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0
 ; CHECK:   Successors:
 ; CHECK-NEXT:    SU(5): Data Latency=4 Reg=%vreg2
 ; CHECK-NEXT:    SU(4): Ord  Latency=0
-; CHECK: SU(3):   STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
+; CHECK: SU(3):   STRWui %WZR<norename>, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
 ; CHECK:   Successors:
 ; CHECK: SU(4): Ord  Latency=0
-; CHECK: SU(4):   STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
-; CHECK: SU(5):   %W0<def> = COPY %vreg2; GPR32:%vreg2
+; CHECK: SU(4):   STRWui %WZR<norename>, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
+; CHECK: SU(5):   %W0<def,norename> = COPY %vreg2; GPR32:%vreg2
 ; CHECK: ** ScheduleDAGMI::schedule picking next node
 define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
 entry:
   %ptr1_plus1 = getelementptr inbounds i32, i32* %ptr1, i64 1
   %val1 = load i32, i32* %ptr1_plus1, align 4
   store i32 0, i32* %ptr1, align 4
   store i32 0, i32* %ptr2, align 4
   ret i32 %val1
 }

test/CodeGen/AArch64/arm64-misched-multimmo.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 
 
 @G1 = common global [100 x i32] zeroinitializer, align 4
 @G2 = common global [100 x i32] zeroinitializer, align 4
 
 ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
 ;
 ; CHECK-LABEL: # Machine code for function foo:
 ; CHECK: SU(2):   %W{{[0-9]+}}<def>, %W{{[0-9]+}}<def> = LDPWi
 ; CHECK: Successors:
 ; CHECK-NOT: ch SU(4)
 ; CHECK: SU(3)
-; CHECK: SU(4):   STRWui %WZR, %X{{[0-9]+}}
+; CHECK: SU(4):   STRWui %WZR<norename>, %X{{[0-9]+}}
 define i32 @foo() {
 entry:
   %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4
   %1 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 1), align 4
   store i32 0, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G1, i64 0, i64 0), align 4
   %add = add nsw i32 %1, %0
   ret i32 %add
 }

test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll

 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -print-before=post-RA-sched %s -o - 2>&1 \
 ; RUN:  | FileCheck %s
 
 define void @vst(i8* %m, [4 x i64] %v) {
 entry:
 ; CHECK: vst:
-; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill>
+; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}<norename>, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill,norename>
 
   %v0 = extractvalue [4 x i64] %v, 0
   %v1 = extractvalue [4 x i64] %v, 1
   %v2 = extractvalue [4 x i64] %v, 2
   %v3 = extractvalue [4 x i64] %v, 3
 
   %t0 = bitcast i64 %v0 to <8 x i8>
   %t1 = bitcast i64 %v1 to <8 x i8>
; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}<norename>, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill,norename>
   call void @bar(<2 x i64> %n1)
 
   ret void
 }
 
 %struct.__neon_int8x8x4_t = type { <8 x i8>,  <8 x i8>,  <8 x i8>, <8 x i8> }
 define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
 ; CHECK: vtbx4:
-; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
+; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,norename>
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
         %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
         %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
         %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
   %tmp7 = load <8 x i8>, <8 x i8>* %C
   %tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
   call void @bar2(%struct.__neon_int8x8x4_t %tmp2, <8 x i8> %tmp8)
   ret <8 x i8> %tmp8
 }
 
 declare void @llvm.arm.neon.vst4.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32)
 declare <8 x i8>  @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
 declare void @bar2(%struct.__neon_int8x8x4_t, <8 x i8>)
 declare void @bar(<2 x i64> %arg)

test/CodeGen/ARM/Windows/vla-cpsr.ll

 ; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-machineinstrs=expand-isel-pseudos 2>&1 | FileCheck %s
 
 declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr
 
 define arm_aapcs_vfpcc void @f(i32 %i) local_unnamed_addr {
 entry:
   %vla = alloca i8, i32 %i, align 1
   call arm_aapcs_vfpcc void @g(i8* nonnull %vla)
   ret void
 }
 
-; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %LR<imp-def>, %SP<imp-use>, %R4<imp-use,kill>, %R4<imp-def>, %R12<imp-def,dead>, %CPSR<imp-def,dead>
+; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %LR<imp-def,norename>, %SP<imp-use,norename>, %R4<imp-use,kill,norename>, %R4<imp-def,norename>, %R12<imp-def,dead,norename>, %CPSR<imp-def,dead,norename>
 

test/CodeGen/PowerPC/byval-agg-info.ll

 ; RUN: llc -verify-machineinstrs < %s -print-after=prologepilog >%t 2>&1 && FileCheck <%t %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 %struct.anon = type { i32, i32 }
 
 declare void @foo(%struct.anon* %v)
 define void @test(i32 %a, i32 %b, %struct.anon* byval nocapture %v) {
 entry:
   call void @foo(%struct.anon* %v)
   ret void
 }
 
 ; Make sure that the MMO on the store has no offset from the byval
 ; variable itself (we used to have mem:ST8[%v+64]).
-; CHECK: STD %X5<kill>, 176, %X1; mem:ST8[%v](align=16)
+; CHECK: STD %X5<kill>, 176, %X1<norename>; mem:ST8[%v](align=16)
 

test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll

 ; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
 
 ; CHECK-LABEL: fn1
 define signext i32 @fn1(i32 %baz) {
   %1 = mul nsw i32 %baz, 208
   %2 = zext i32 %1 to i64
   %3 = shl i64 %2, 48
   %4 = ashr exact i64 %3, 48
-; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>;
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead,norename>;
 ; CHECK: CMPLDI
 ; CHECK: BCC
 
-; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>;
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,norename>;
 ; CHECK: COPY %CR0
 ; CHECK: BCC
   %5 = icmp eq i64 %4, 0
   br i1 %5, label %foo, label %bar
 
 foo:
   ret i32 1
 
 bar:
   ret i32 0
 }
 
 ; CHECK-LABEL: fn2
 define signext i32 @fn2(i64 %a, i64 %b) {
-; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def>;
+; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def,norename>;
 ; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
 ; CHECK: BCC 12, [[CREG]]<kill>
   %1 = or i64 %b, %a
   %2 = icmp sgt i64 %1, -1
   br i1 %2, label %foo, label %bar
 
 foo:
   ret i32 1
 
 bar:
   ret i32 0
 }
 
 ; CHECK-LABEL: fn3
 define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def>;
+; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def,norename>;
 ; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
 ; CHECK: BCC 76, [[CREG]]<kill>
   %1 = and i32 %a, 10
   %2 = icmp ne i32 %1, 0
   br i1 %2, label %foo, label %bar
 
 foo:
   ret i32 1

test/CodeGen/PowerPC/quadint-return.ll

 ; REQUIRES: asserts
 ; RUN: llc -verify-machineinstrs -O0 -debug -o - < %s 2>&1 | FileCheck %s
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define i128 @foo() nounwind {
 entry:
   %x = alloca i128, align 16
   store i128 27, i128* %x, align 16
   %0 = load i128, i128* %x, align 16
   ret i128 %0
 }
 
 ; CHECK: ********** Function: foo
 ; CHECK: ********** FAST REGISTER ALLOCATION **********
-; CHECK: %X3<def> = COPY %vreg
-; CHECK-NEXT: %X4<def> = COPY %vreg
+; CHECK: %X3<def,norename> = COPY %vreg
+; CHECK-NEXT: %X4<def,norename> = COPY %vreg
 ; CHECK-NEXT: BLR

test/CodeGen/X86/misched-copy.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -verify-machineinstrs -mtriple=i686-- -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ;
 ; Test scheduling of copy instructions.
 ;
 ; Argument copies should be hoisted to the top of the block.
 ; Return copies should be sunk to the end.
 ; MUL_HiLo PhysReg use copies should be just above the mul.
 ; MUL_HiLo PhysReg def copies should be just below the mul.
 ;
 ; CHECK: *** Final schedule for BB#1 ***
-; CHECK:      %EAX<def> = COPY
-; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>;
+; CHECK:      %EAX<def,norename> = COPY
+; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def,norename>, %EDX<imp-def,norename>, %EFLAGS<imp-def,dead,norename>, %EAX<imp-use,norename>;
 ; CHECK-NEXT: COPY %E{{[AD]}}X
 ; CHECK-NEXT: COPY %E{{[AD]}}X
 ; CHECK:      DIVSSrm
 define i64 @mulhoist(i32 %a, i32 %b) #0 {
 entry:
   br label %body
 
 body:

test/CodeGen/X86/pr28560.ll

 ; RUN: llc -mtriple=i686-pc-linux -print-after=postrapseudos < %s 2>&1 | FileCheck %s
 
-; CHECK: MOV8rr %{{[A-D]}}L, %E[[R:[A-D]]]X<imp-use,kill>, %E[[R]]X<imp-def>
+; CHECK: MOV8rr %{{[A-D]}}L<norename>, %E[[R:[A-D]]]X<imp-use,kill,norename>, %E[[R]]X<imp-def,norename>
 define i32 @foo(i32 %i, i32 %k, i8* %p) {
   %f = icmp ne i32 %i, %k
   %s = zext i1 %f to i8
   %ret = zext i1 %f to i32
   br label %next
 next:
   %d = add i8 %s, 5
   store i8 %d, i8* %p
   ret i32 %ret
 }

test/CodeGen/X86/remat-phys-dead.ll

 ; REQUIRES: asserts
 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-apple-darwin -debug -o /dev/null < %s 2>&1 | FileCheck %s
 
 ; We need to make sure that rematerialization into a physical register marks the
 ; super- or sub-register as dead after this rematerialization since only the
 ; original register is actually used later. Largely irrelevant for a trivial
 ; example like this, since EAX is never used again, but easy to test.
 
 define i8 @test_remat() {
   ret i8 0
 ; CHECK: REGISTER COALESCING
-; CHECK: Remat: %EAX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %AL<imp-def>
+; CHECK: Remat: %EAX<def,dead,norename> = MOV32r0 %EFLAGS<imp-def,dead,norename>, %AL<imp-def,norename>
 }
 
 ; On the other hand, if it's already the correct width, we really shouldn't be
 ; marking the definition register as dead.
 
 define i32 @test_remat32() {
   ret i32 0
 ; CHECK: REGISTER COALESCING
-; CHECK: Remat: %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
+; CHECK: Remat: %EAX<def,norename> = MOV32r0 %EFLAGS<imp-def,dead,norename>
 }