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Differential D39016

Add Percent Symbol In PPC Registers for Linux
ClosedPublic

Authored by joerg on Oct 17 2017, 11:56 AM.

Details

Reviewers
echristo
alexandreyy
Commits
rG4b1acff9b392: First step towards more human-friendly PPC assembler output: - add -ppc-reg…
rL319381: First step towards more human-friendly PPC assembler output:
Summary

This patch inserts a percent symbol before the register names on PowerPC
for Linux. This makes easier to recognize the register types in the
assembly code. That improves the syntax of the code disassembled by
LLDB.
Tests were changed to ignore the percent prefixes.

Diff Detail

Event Timeline

alexandreyy created this revision.Oct 17 2017, 11:56 AM
Herald added subscribers: JDevlieghere, kbarton, eraman and 2 others. · View Herald TranscriptOct 17 2017, 11:56 AM
gut added a comment.Oct 18 2017, 4:44 AM

Just to show how much the disassembly is changed. Consider the following instruction:

li %r3,0

currently, it's disassembled by llvm like:

0x20000780 <+0>:  li     3, 0

However this is what it looks like in gdb:

0x0000000020000780 <+0>:     li      r3,0

and in objdump -d:

780:   00 00 60 38     li      r3,0

The code currently disassembled by llvm is not wrong! But it is surely less readable when not placing register type hints.

Now how this patch makes it looks like:

li[0x780] <+0>:  li     %r3, 0

PS: Both %r3 and 3 are valid 1st parameter for li instruction on PowerPC.

alexandreyy added a comment.Oct 20 2017, 4:36 AM

ping

nemanjai added subscribers: hfinkel, echristo.Oct 20 2017, 5:23 AM

A few general comments:

  1. You should add reviewers to this review. At the minimum @hfinkel, @kbarton and @echristo. Maybe someone from FreeBSD if this affects them.
  2. Why do we need to change the default and get the existing behaviour with an option? Why not the other way around?
  3. Is this syntax accepted by all the assemblers (I think LLVM for PPC runs on FreeBSD as well, but I have no idea if FreeBSD returns true for isOSLinux()? We don't want to produce assembly that we can't assemble.
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
45

I'm not a fan of this name. We're not "ignoring" the percent sign here, we're just not printing it, right?

460

Naming convention: variables start with capitals.

489

With this, LLVM will show CR registers as %crN. I am not aware of any other tool that will produce this spelling.

joerg requested changes to this revision.Oct 20 2017, 5:51 AM
joerg added a subscriber: joerg.

The patch is not acceptable in the current form. This includes fixing the memory leaks.

On PowerPC, three different output forms have to be supported:
(1) register name without percent on Darwin
(2) plain register number on AIX
(3) register name with percent OR plain register number on anything else
I don't think there is a big reason for supporting the second option of (3) though. The least amount of change is to introduce a predicate that checks for !Darwin && !AIX and then prints the % in the assembler printer. It is better to just pass down the target directly than deciding in the higher layers which forms should be choosen.

This revision now requires changes to proceed.Oct 20 2017, 5:51 AM
alexandreyy updated this revision to Diff 119850.Oct 23 2017, 7:51 AM
alexandreyy edited edge metadata.

Update according to review comments

Harbormaster completed remote builds in B11378: Diff 119850.Oct 23 2017, 7:54 AM
alexandreyy marked 2 inline comments as done.Oct 23 2017, 8:13 AM
In D39016#902039, @nemanjai wrote:

A few general comments:

  1. You should add reviewers to this review. At the minimum @hfinkel, @kbarton and @echristo. Maybe someone from FreeBSD if this affects them.
  2. Why do we need to change the default and get the existing behaviour with an option? Why not the other way around?
  3. Is this syntax accepted by all the assemblers (I think LLVM for PPC runs on FreeBSD as well, but I have no idea if FreeBSD returns true for isOSLinux()? We don't want to produce assembly that we can't assemble.

1, 3: FreeBSD should return true for isOSFreeBSD. This patch only affects the Linux behavior.
2: The default should be changed to allow LLDB prints the register prefixes. The code is still accepted by the assemblers in Linux.

It is not possible to set this option by LLDB.
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
45

That's right. Fixed variable name to StripRegisterPrefix.

460

Fixed variable names.

alexandreyy marked 2 inline comments as done.Oct 23 2017, 8:17 AM
In D39016#902082, @joerg wrote:

The patch is not acceptable in the current form. This includes fixing the memory leaks.

On PowerPC, three different output forms have to be supported:
(1) register name without percent on Darwin
(2) plain register number on AIX
(3) register name with percent OR plain register number on anything else
I don't think there is a big reason for supporting the second option of (3) though. The least amount of change is to introduce a predicate that checks for !Darwin && !AIX and then prints the % in the assembler printer. It is better to just pass down the target directly than deciding in the higher layers which forms should be choosen.

Fixed memory leak problem.
Changed code to handle target in the assembler printer, passing the target directly in the class constructor.

joerg added a comment.Oct 23 2017, 8:51 AM

This is even worse. You can't new[] and then free(). Please follow the suggestion on just embedding the prefix directly, if desirable.

alexandreyy added a comment.Oct 23 2017, 10:20 AM
In D39016#903648, @joerg wrote:

This is even worse. You can't new[] and then free(). Please follow the suggestion on just embedding the prefix directly, if desirable.

Is the suggestion to keep the default without the prefixes?
Because it is not possible to change the cl option by LLDB.

joerg added a comment.Oct 23 2017, 10:35 AM
In D39016#903937, @alexandreyy wrote:

Because it is not possible to change the cl option by LLDB.

There should be no need to. This is not a public interface anyway. Long term, all sources should be changed to consistently use the human-friendly names, but that's a separate issue.

alexandreyy added a comment.Oct 23 2017, 11:38 AM
In D39016#903973, @joerg wrote:
In D39016#903937, @alexandreyy wrote:

Because it is not possible to change the cl option by LLDB.

There should be no need to. This is not a public interface anyway. Long term, all sources should be changed to consistently use the human-friendly names, but that's a separate issue.

I am confused. Does the LLVM will be changed to support human-friendly names in the future by default?
Is there another way to change it now?
The LLVM interface could be modified to accept an option for printing the prefixes.
But It would require a lot of changes.

nemanjai added a comment.Oct 24 2017, 4:39 AM

If what we want is to name the registers with the percent sign prefix on all non-AIX, non-Darwin systems, why not just change the definitions in the .td files to include the prefix? That way you don't have to worry about this kind of hacky/leaky code to prepend the symbol to the register names. And on AIX/Darwin, we just strip the full prefix (percent symbol and letter). Considering that it is questionable whether LLVM will ever have full support on AIX and that Darwin support is likely to be pulled soon, this seems like the best choice.

Of course, we'd then need to decide how we want to print the CR registers (i.e. if we want to have the ability to print them the way binutils tools print them - 4*cr4+gt, etc.)

alexandreyy updated this revision to Diff 120059.Oct 24 2017, 6:18 AM

Update according to review comments

Harbormaster completed remote builds in B11428: Diff 120059.Oct 24 2017, 6:21 AM
joerg added a comment.Oct 24 2017, 6:58 AM

Almost.

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
489

Should be a static bool showRegistersWithPercentPrefix(RegName(const char *RegName) member of PPCInstPrinter and just return true or false.

539

...and here if (showRegistersWithPercentPrefix(RegName) O << "%";. Rest of the RegName logic can remain.

alexandreyy updated this revision to Diff 120086.Oct 24 2017, 9:30 AM

Changed printRegisterWithPercentPrefix to showRegistersWithPercentPrefix

alexandreyy added a comment.Oct 24 2017, 9:45 AM
In D39016#904944, @nemanjai wrote:

If what we want is to name the registers with the percent sign prefix on all non-AIX, non-Darwin systems, why not just change the definitions in the .td files to include the prefix? That way you don't have to worry about this kind of hacky/leaky code to prepend the symbol to the register names. And on AIX/Darwin, we just strip the full prefix (percent symbol and letter). Considering that it is questionable whether LLVM will ever have full support on AIX and that Darwin support is likely to be pulled soon, this seems like the best choice.

Of course, we'd then need to decide how we want to print the CR registers (i.e. if we want to have the ability to print them the way binutils tools print them - 4*cr4+gt, etc.)

The prefixes are already being printed if they are not stripped in PPCInstPrinter.cpp.
And the default can be changed to include the percent without a option.
However, all the test files should be changed to consider different syntaxes for each OS.

gut added a comment.Oct 24 2017, 10:18 AM
In D39016#903973, @joerg wrote:

Long term, all sources should be changed to consistently use the human-friendly names, but that's a separate issue.

Macro tell_me_more:

What did you mean with "Long term"? I'm interested in having such a human-friendlier disassembler on LLDB and I noticed that this patch is not going to change that.

(I just want to know when this mode would reach LLDB.)

alexandreyy added a comment.Oct 27 2017, 7:54 AM

Hi.
Are these changes ok?

joerg added inline comments.Oct 27 2017, 9:15 AM
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
531

I said make it a member function because the knowledge that Darwin doesn't get the percent should be part of it, not external...

alexandreyy added inline comments.Oct 27 2017, 12:18 PM
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
531

If the OS is Darwin, the register name can't be stripped too.
So, We need to check the OS in the external function printOperand.

Or I can not strip the register prefix in stripRegisterPrefix if the OS is Darwin.

What do you think it is better?

joerg added inline comments.Oct 27 2017, 2:36 PM
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
531

That's why I suggested to keep things separate and simple. First just decide if the '%' prefix is desired; afterwards, decide whether the register name should be stripped. Keeping the decisions separate makes the flow easier. They will become less entangled in the future too.

I haven't really made up my mind on whether supporting the AIX flavor long term is desirable, I let others shim in on that. But that's a separate follow-up.

alexandreyy updated this revision to Diff 120827.Oct 30 2017, 8:18 AM

Update patch according to suggestions

alexandreyy added a comment.Nov 1 2017, 6:04 AM

Are these changes ok?

alexandreyy added a comment.Nov 3 2017, 8:01 AM

Hi, @joerg
Could you review/approve these changes?

alexandreyy added a comment.Nov 9 2017, 4:32 AM

Hi,
Could someone review/approve this patch, please?
I don't have the permissions to commit it.
Thanks. ;)

echristo requested changes to this revision.Nov 9 2017, 10:50 PM

I really appreciate you doing this work. This has been something I've wanted for some time :)

I've added a few things to this. Should also have a testcase as well.

Thanks!

-eric

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
456

Seems to be no reason to make it a member function?

472

Ditto.

488

Having this not be the direct inverse of the above is weird. Perhaps redo some of that logic?

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
23

"TT" is a standard Triple name.

This revision now requires changes to proceed.Nov 9 2017, 10:50 PM
alexandreyy updated this revision to Diff 122481.Nov 10 2017, 10:56 AM
alexandreyy edited edge metadata.

Updated patch according to review.

alexandreyy added a comment.Nov 10 2017, 10:58 AM
In D39016#921483, @echristo wrote:

I really appreciate you doing this work. This has been something I've wanted for some time :)

I've added a few things to this. Should also have a testcase as well.

Thanks!

-eric

Thanks @echristo.
I modified the patch according to your comments.

alexandreyy updated this revision to Diff 122484.Nov 10 2017, 11:06 AM

Fixed identation.

alexandreyy marked 3 inline comments as done.Nov 10 2017, 11:15 AM
alexandreyy added inline comments.
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
456

Removed from class.

488

Better with that logic.
But it does not change the output printed.
The percent is optional, so it is inserted if the flag FullRegNamesWithPercent is enabled.

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
23

Changed to TT

alexandreyy marked an inline comment as done.Nov 14 2017, 10:49 AM

Hi, guys!
Are these changes Ok to commit?

alexandreyy added a comment.Nov 16 2017, 3:30 AM

ping

alexandreyy added a comment.Nov 16 2017, 9:52 AM

@joerg, @echristo, Could you check if these changes are Ok?
Thanks!

alexandreyy added a comment.Nov 21 2017, 3:57 AM
In D39016#927612, @alexandreyy wrote:

@joerg, @echristo, Could you check if these changes are Ok?
Thanks!

ping

joerg commandeered this revision.Nov 21 2017, 2:10 PM
joerg edited reviewers, added: alexandreyy; removed: joerg.
joerg updated this revision to Diff 123850.Nov 21 2017, 2:13 PM

Split into verbose conditional register names into a separate function. We likely want to remove them going forward as they are a specific feature of the Darwin assembler and not wildly supported.

Create precise predicates for using % register names and stripped register names, decoupling the (incomplete) existing checks.

alexandreyy accepted this revision.Nov 22 2017, 3:30 AM

Thanks, @joerg !
It looks better than before.

alexandreyy added a comment.Nov 29 2017, 7:40 AM

Hi, @echristo @joerg

Could we commit this patch?

Closed by commit rL319381: First step towards more human-friendly PPC assembler output: (authored by joerg). · Explain WhyNov 29 2017, 3:06 PM
This revision was automatically updated to reflect the committed changes.
joerg added a comment.Nov 29 2017, 3:10 PM

So the next steps if you have the time would IMO be:

(1) Convert the Darwinish verbose conditional codes into annotations:

bt 2, foo # condition: eq

or something like that. This removes some platform specific logic and can be applied unconditionally.

(2) Convert the existing test cases and drop the -ppc-reg-with-precent-prefix option. This is sadly mostly busy work unless you can script it.

qiucf mentioned this in D94282: [PowerPC] Support ppc-asm-full-reg-names for AIX.Jan 7 2021, 7:14 PM

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Diff 119850

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h

//===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===// //===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This class prints an PPC MCInst to a .s file. // This class prints an PPC MCInst to a .s file.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_POWERPC_INSTPRINTER_PPCINSTPRINTER_H #ifndef LLVM_LIB_TARGET_POWERPC_INSTPRINTER_PPCINSTPRINTER_H
#define LLVM_LIB_TARGET_POWERPC_INSTPRINTER_PPCINSTPRINTER_H #define LLVM_LIB_TARGET_POWERPC_INSTPRINTER_PPCINSTPRINTER_H
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class PPCInstPrinter : public MCInstPrinter { class PPCInstPrinter : public MCInstPrinter {
bool IsDarwin; Triple TripleInfo;
echristoUnsubmitted
Not Done
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"TT" is a standard Triple name.

echristo: "TT" is a standard Triple name.
alexandreyyUnsubmitted
Not Done
ReplyInline Actions

Changed to TT

alexandreyy: Changed to TT
public: public:
PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI, bool isDarwin) const MCRegisterInfo &MRI, Triple T)
: MCInstPrinter(MAI, MII, MRI), IsDarwin(isDarwin) {} : MCInstPrinter(MAI, MII, MRI), TripleInfo(T) {}
bool isDarwinSyntax() const {
return IsDarwin;
}
void printRegName(raw_ostream &OS, unsigned RegNo) const override; void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override; const MCSubtargetInfo &STI) override;
// Autogenerated by tblgen. // Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O); void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo); static const char *getRegisterName(unsigned RegNo);
bool printAliasInstr(const MCInst *MI, raw_ostream &OS); bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, unsigned PrintMethodIdx,
raw_ostream &OS); raw_ostream &OS);
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printPredicateOperand(const MCInst *MI, unsigned OpNo, void printPredicateOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O, const char *Modifier = nullptr); raw_ostream &O, const char *Modifier = nullptr);
Show All 27 Lines

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

Show All 33 Lines
FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
cl::desc("Use full register names when printing assembly")); cl::desc("Use full register names when printing assembly"));
// Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively. // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
static cl::opt<bool> static cl::opt<bool>
ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false), ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
cl::desc("Prints full register names with vs{31-63} as v{0-31}")); cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
// Strips register prefixes.
static cl::opt<bool>
StripRegisterPrefix("ppc-strip-register-prefix", cl::Hidden, cl::init(false),
cl::desc("Prints register names without prefixes"));
nemanjaiUnsubmitted
Done
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I'm not a fan of this name. We're not "ignoring" the percent sign here, we're just not printing it, right?

nemanjai: I'm not a fan of this name. We're not "ignoring" the percent sign here, we're just not printing…
alexandreyyUnsubmitted
Not Done
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That's right. Fixed variable name to StripRegisterPrefix.

alexandreyy: That's right. Fixed variable name to StripRegisterPrefix.
#define PRINT_ALIAS_INSTR #define PRINT_ALIAS_INSTR
#include "PPCGenAsmWriter.inc" #include "PPCGenAsmWriter.inc"
void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
const char *RegName = getRegisterName(RegNo); const char *RegName = getRegisterName(RegNo);
if (RegName[0] == 'q' /* QPX */) { if (RegName[0] == 'q' /* QPX */) {
// The system toolchain on the BG/Q does not understand QPX register names // The system toolchain on the BG/Q does not understand QPX register names
// in .cfi_* directives, so print the name of the floating-point // in .cfi_* directives, so print the name of the floating-point
▲ Show 20 Lines • Show All 390 Lines • ▼ Show 20 Linesvoid PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
O << refExp.getSymbol().getName(); O << refExp.getSymbol().getName();
O << '('; O << '(';
printOperand(MI, OpNo+1, O); printOperand(MI, OpNo+1, O);
O << ')'; O << ')';
if (refExp.getKind() != MCSymbolRefExpr::VK_None) if (refExp.getKind() != MCSymbolRefExpr::VK_None)
O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind()); O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
} }
/// stripRegisterPrefix - This method strips the character prefix from a /// stripRegisterPrefix - This method strips the character prefix from a
/// register name so that only the number is left. Used by for linux asm. /// register name so that only the number is left.
static const char *stripRegisterPrefix(const char *RegName, unsigned RegNum, static const char *stripRegisterPrefix(const char *RegName, unsigned RegNum,
unsigned RegEncoding) { unsigned RegEncoding) {
echristoUnsubmitted
Done
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Seems to be no reason to make it a member function?

echristo: Seems to be no reason to make it a member function?
alexandreyyUnsubmitted
Not Done
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Removed from class.

alexandreyy: Removed from class.
if (FullRegNames) { if (FullRegNames) {
if (RegNum >= PPC::CR0EQ && RegNum <= PPC::CR7UN) { if (RegNum >= PPC::CR0EQ && RegNum <= PPC::CR7UN) {
const char *CRBits[] = const char *CRBits[] =
{ "lt", "gt", "eq", "un", { "lt", "gt", "eq", "un",
nemanjaiUnsubmitted
Done
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Naming convention: variables start with capitals.

nemanjai: Naming convention: variables start with capitals.
alexandreyyUnsubmitted
Not Done
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Fixed variable names.

alexandreyy: Fixed variable names.
"4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un", "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
"4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un", "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
"4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un", "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
"4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un", "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
"4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un", "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
"4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un", "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
"4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un" "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
}; };
return CRBits[RegEncoding]; return CRBits[RegEncoding];
} }
return RegName; return RegName;
} }
echristoUnsubmitted
Done
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Ditto.

echristo: Ditto.
switch (RegName[0]) { switch (RegName[0]) {
case 'r': case 'r':
case 'f': case 'f':
case 'q': // for QPX case 'q': // for QPX
case 'v': case 'v':
if (RegName[1] == 's') if (RegName[1] == 's')
return RegName + 2; return RegName + 2;
return RegName + 1; return RegName + 1;
case 'c': if (RegName[1] == 'r') return RegName + 2; case 'c': if (RegName[1] == 'r') return RegName + 2;
} }
return RegName; return RegName;
} }
/// insertPercentInRegisterPrefix - Adds a percent symbol in the register
echristoUnsubmitted
Not Done
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Having this not be the direct inverse of the above is weird. Perhaps redo some of that logic?

echristo: Having this not be the direct inverse of the above is weird. Perhaps redo some of that logic?
alexandreyyUnsubmitted
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Better with that logic.
But it does not change the output printed.
The percent is optional, so it is inserted if the flag FullRegNamesWithPercent is enabled.

alexandreyy: Better with that logic. But it does not change the output printed. The percent is optional, so…
/// prefixes.
nemanjaiUnsubmitted
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With this, LLVM will show CR registers as %crN. I am not aware of any other tool that will produce this spelling.

nemanjai: With this, LLVM will show CR registers as `%crN`. I am not aware of any other tool that will…
joergAuthorUnsubmitted
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Should be a static bool showRegistersWithPercentPrefix(RegName(const char *RegName) member of PPCInstPrinter and just return true or false.

joerg: Should be a `static bool showRegistersWithPercentPrefix(RegName(const char *RegName)` member of…
void insertPercentInRegisterPrefix(char *NewRegName, const char *RegName) {
switch (RegName[0]) {
case 'r':
case 'f':
case 'q':
case 'v':
case 'c':
strcpy(NewRegName, "%");
strcat(NewRegName, RegName);
break;
default:
strcpy(NewRegName, RegName);
}
}
void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) { raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo); const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) { if (Op.isReg()) {
unsigned Reg = Op.getReg(); unsigned Reg = Op.getReg();
// There are VSX instructions that use VSX register numbering (vs0 - vs63) // There are VSX instructions that use VSX register numbering (vs0 - vs63)
// as well as those that use VMX register numbering (v0 - v31 which // as well as those that use VMX register numbering (v0 - v31 which
// correspond to vs32 - vs63). If we have an instruction that uses VSX // correspond to vs32 - vs63). If we have an instruction that uses VSX
// numbering, we need to convert the VMX registers to VSX registers. // numbering, we need to convert the VMX registers to VSX registers.
// Namely, we print 32-63 when the instruction operates on one of the // Namely, we print 32-63 when the instruction operates on one of the
// VMX registers. // VMX registers.
// (Please synchronize with PPCAsmPrinter::printOperand) // (Please synchronize with PPCAsmPrinter::printOperand)
if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg) && if ((MII.get(MI->getOpcode()).TSFlags & PPCII::UseVSXReg) &&
!ShowVSRNumsAsVR) { !ShowVSRNumsAsVR) {
if (PPCInstrInfo::isVRRegister(Reg)) if (PPCInstrInfo::isVRRegister(Reg))
Reg = PPC::VSX32 + (Reg - PPC::V0); Reg = PPC::VSX32 + (Reg - PPC::V0);
else if (PPCInstrInfo::isVFRegister(Reg)) else if (PPCInstrInfo::isVFRegister(Reg))
Reg = PPC::VSX32 + (Reg - PPC::VF0); Reg = PPC::VSX32 + (Reg - PPC::VF0);
} }
const char *RegName = getRegisterName(Reg); const char *RegName = getRegisterName(Reg);
// The linux and AIX assembler does not take register prefixes.
if (!isDarwinSyntax()) // Check if we need to change the register prefix.
if (!TripleInfo.isOSDarwin() || StripRegisterPrefix) {
// Linux only accepts register prefixes with percent symbol.
if (TripleInfo.isOSLinux() and !(StripRegisterPrefix or FullRegNames)) {
joergAuthorUnsubmitted
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I said make it a member function because the knowledge that Darwin doesn't get the percent should be part of it, not external...

joerg: I said make it a member function because the knowledge that Darwin doesn't get the percent…
alexandreyyUnsubmitted
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If the OS is Darwin, the register name can't be stripped too.
So, We need to check the OS in the external function printOperand.

Or I can not strip the register prefix in stripRegisterPrefix if the OS is Darwin.

What do you think it is better?

alexandreyy: If the OS is Darwin, the register name can't be stripped too. So, We need to check the OS in…
joergAuthorUnsubmitted
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That's why I suggested to keep things separate and simple. First just decide if the '%' prefix is desired; afterwards, decide whether the register name should be stripped. Keeping the decisions separate makes the flow easier. They will become less entangled in the future too.

I haven't really made up my mind on whether supporting the AIX flavor long term is desirable, I let others shim in on that. But that's a separate follow-up.

joerg: That's why I suggested to keep things separate and simple. First just decide if the '%' prefix…
char *NewRegName = new char[strlen(RegName) + 1];
insertPercentInRegisterPrefix(NewRegName, RegName);
O << NewRegName;
free(NewRegName);
return;
} else {
// AIX assembler does not take register prefixes.
// The assembly syntax without the register prefixes is also accepted by
joergAuthorUnsubmitted
Not Done
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...and here if (showRegistersWithPercentPrefix(RegName) O << "%";. Rest of the RegName logic can remain.

joerg: ...and here `if (showRegistersWithPercentPrefix(RegName) O << "%";`. Rest of the RegName logic…
// Linux and FreeBSD.
RegName = stripRegisterPrefix(RegName, Reg, MRI.getEncodingValue(Reg)); RegName = stripRegisterPrefix(RegName, Reg, MRI.getEncodingValue(Reg));
}
}
O << RegName; O << RegName;
return; return;
} }
if (Op.isImm()) { if (Op.isImm()) {
O << Op.getImm(); O << Op.getImm();
return; return;
} }
assert(Op.isExpr() && "unknown operand kind in printOperand"); assert(Op.isExpr() && "unknown operand kind in printOperand");
Op.getExpr()->print(O, &MAI); Op.getExpr()->print(O, &MAI);
} }

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

Show First 20 Lines • Show All 233 Lines • ▼ Show 20 LinescreateObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
return new PPCTargetMachOStreamer(S); return new PPCTargetMachOStreamer(S);
} }
static MCInstPrinter *createPPCMCInstPrinter(const Triple &T, static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MRI) {
return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin()); return new PPCInstPrinter(MAI, MII, MRI, T);
} }
extern "C" void LLVMInitializePowerPCTargetMC() { extern "C" void LLVMInitializePowerPCTargetMC() {
for (Target *T : for (Target *T :
{&getThePPC32Target(), &getThePPC64Target(), &getThePPC64LETarget()}) { {&getThePPC32Target(), &getThePPC64Target(), &getThePPC64LETarget()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo); RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
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test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-strip-register-prefix | FileCheck %s
@lens = external global i8* ; <i8**> [#uses=1] @lens = external global i8* ; <i8**> [#uses=1]
@vals = external global i32* ; <i32**> [#uses=1] @vals = external global i32* ; <i32**> [#uses=1]
define i32 @test(i32 %i) { define i32 @test(i32 %i) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: addis 4, 2, .LC0@toc@ha ; CHECK-NEXT: addis 4, 2, .LC0@toc@ha
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test/CodeGen/PowerPC/2007-03-24-cntlzd.ll

; RUN: llc -verify-machineinstrs -mcpu=g5 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=g5 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) nounwind { define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) nounwind {
%tmp19 = load i64, i64* %t %tmp19 = load i64, i64* %t
%tmp22 = tail call i64 @llvm.ctlz.i64( i64 %tmp19, i1 true ) ; <i64> [#uses=1] %tmp22 = tail call i64 @llvm.ctlz.i64( i64 %tmp19, i1 true ) ; <i64> [#uses=1]
%tmp23 = trunc i64 %tmp22 to i32 %tmp23 = trunc i64 %tmp22 to i32
%tmp89 = add i32 %tmp23, -64 ; <i32> [#uses=1] %tmp89 = add i32 %tmp23, -64 ; <i32> [#uses=1]
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test/CodeGen/PowerPC/2012-10-12-bitcast.ll

; RUN: llc -verify-machineinstrs -mattr=-vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mattr=-vsx \
; RUN: llc -verify-machineinstrs -mattr=+vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -mattr=+altivec -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mattr=+vsx \
; RUN: -mattr=+altivec -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i32 @test(<16 x i8> %v) nounwind { define i32 @test(<16 x i8> %v) nounwind {
entry: entry:
%0 = bitcast <16 x i8> %v to i128 %0 = bitcast <16 x i8> %v to i128
%1 = lshr i128 %0, 96 %1 = lshr i128 %0, 96
%2 = trunc i128 %1 to i32 %2 = trunc i128 %1 to i32
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test/CodeGen/PowerPC/2012-11-16-mischedcall.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-bgq-linux -enable-misched < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-bgq-linux -enable-misched < %s | FileCheck %s
; ;
; PR14315: misched should not move the physreg copy of %t below the calls. ; PR14315: misched should not move the physreg copy of %t below the calls.
@.str89 = external unnamed_addr constant [6 x i8], align 1 @.str89 = external unnamed_addr constant [6 x i8], align 1
declare void @init() nounwind declare void @init() nounwind
declare void @clock() nounwind declare void @clock() nounwind
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test/CodeGen/PowerPC/2013-05-15-preinc-fold.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i8* @test(i8* %base, i8 %val) { define i8* @test(i8* %base, i8 %val) {
entry: entry:
%arrayidx = getelementptr inbounds i8, i8* %base, i32 -1 %arrayidx = getelementptr inbounds i8, i8* %base, i32 -1
store i8 %val, i8* %arrayidx, align 1 store i8 %val, i8* %arrayidx, align 1
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test/CodeGen/PowerPC/2016-04-28-setjmp.ll

; RUN: llc -filetype=obj <%s | llvm-objdump --disassemble - | FileCheck %s ; RUN: llc -filetype=obj <%s | llvm-objdump --disassemble \
; RUN: -ppc-strip-register-prefix - | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@ptr = common global i8* null, align 8 @ptr = common global i8* null, align 8
; Verify there's no junk between these two instructions from misemitted ; Verify there's no junk between these two instructions from misemitted
; EH_SjLj_Setup. ; EH_SjLj_Setup.
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test/CodeGen/PowerPC/BreakableToken-reduced.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-shrink-wrap=true %s -o - | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -enable-shrink-wrap=true %s -o - | FileCheck %s
; ;
; Test the use of a non-R0 register to save/restore the LR in function ; Test the use of a non-R0 register to save/restore the LR in function
; prologue/epilogue. ; prologue/epilogue.
; This problem can occur as a result of shrink wrapping, where the function ; This problem can occur as a result of shrink wrapping, where the function
; prologue and epilogue are moved from the beginning/ending of the function. If ; prologue and epilogue are moved from the beginning/ending of the function. If
; register R0 is used before the prologue/epilogue blocks, then it cannot be ; register R0 is used before the prologue/epilogue blocks, then it cannot be
; used to save/restore the LR. ; used to save/restore the LR.
; ;
▲ Show 20 Lines • Show All 326 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/a2q-stackalign.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -mcpu=a2q | FileCheck -check-prefix=CHECK-A2Q %s ; RUN: -mtriple=ppc64-- -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-bgq-linux -mcpu=a2 | FileCheck -check-prefix=CHECK-BGQ %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=ppc64-- -mcpu=a2q | FileCheck -check-prefix=CHECK-A2Q %s
; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-bgq-linux -mcpu=a2 | FileCheck \
; RUN: -check-prefix=CHECK-BGQ %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
declare i32 @bar(i8* %a) nounwind; declare i32 @bar(i8* %a) nounwind;
define i32 @foo() nounwind { define i32 @foo() nounwind {
%p = alloca i8, i8 115 %p = alloca i8, i8 115
store i8 0, i8* %p store i8 0, i8* %p
%r = call i32 @bar(i8* %p) %r = call i32 @bar(i8* %p)
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test/CodeGen/PowerPC/aa-tbaa.ll

; RUN: llc -verify-machineinstrs -enable-misched -misched=shuffle -enable-aa-sched-mi -use-tbaa-in-sched-mi=0 -post-RA-scheduler=0 -mcpu=ppc64 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -enable-misched -misched=shuffle -enable-aa-sched-mi \
; RUN: -use-tbaa-in-sched-mi=0 -post-RA-scheduler=0 -mcpu=ppc64 \
; RUN: < %s | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; -misched=shuffle is NDEBUG only! ; -misched=shuffle is NDEBUG only!
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%"class.llvm::MCOperand" = type { i8, %union.anon.110 } %"class.llvm::MCOperand" = type { i8, %union.anon.110 }
Show All 32 Lines

test/CodeGen/PowerPC/aantidep-inline-asm-use.ll

; RUN: llc -O2 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -O2 < %s | FileCheck %s
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-grtev4-linux-gnu" target triple = "powerpc64le-grtev4-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @_ZN10SubProcess19ScrubbedForkAndExecEiPiS0_PNS_7ResultsE() #0 align 2 { define void @_ZN10SubProcess19ScrubbedForkAndExecEiPiS0_PNS_7ResultsE() #0 align 2 {
; CHECK: lis 3, 1234 ; CHECK: lis 3, 1234
; CHECK-NOT: li 3 ; CHECK-NOT: li 3
▲ Show 20 Lines • Show All 296 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/add-fi.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=ppc64 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i32* @test1() { define i32* @test1() {
%X = alloca { i32, i32 } %X = alloca { i32, i32 }
%Y = getelementptr {i32,i32}, {i32,i32}* %X, i32 0, i32 1 %Y = getelementptr {i32,i32}, {i32,i32}* %X, i32 0, i32 1
ret i32* %Y ret i32* %Y
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test/CodeGen/PowerPC/addegluecrash.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -O0 < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) { define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) {
; CHECK-LABEL: bn_mul_comba8: ; CHECK-LABEL: bn_mul_comba8:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: ld 6, 0(4) ; CHECK-NEXT: ld 6, 0(4)
; CHECK-NEXT: ld 7, 0(5) ; CHECK-NEXT: ld 7, 0(5)
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test/CodeGen/PowerPC/addi-licm.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -disable-ppc-preinc-prep < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PIP ; RUN: -mcpu=pwr7 -disable-ppc-preinc-prep < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PIP
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define double @foo() #1 { define double @foo() #1 {
entry: entry:
%x = alloca [2048 x float], align 4 %x = alloca [2048 x float], align 4
%y = alloca [2048 x float], align 4 %y = alloca [2048 x float], align 4
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/addi-offset-fold.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
%struct.S0 = type <{ i32, [5 x i8] }> %struct.S0 = type <{ i32, [5 x i8] }>
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @foo([2 x i64] %a.coerce) local_unnamed_addr #0 { define signext i32 @foo([2 x i64] %a.coerce) local_unnamed_addr #0 {
entry: entry:
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test/CodeGen/PowerPC/addisdtprelha-nonr3.mir

# RUN: llc -relocation-model=pic -start-after=block-placement -o - %s | FileCheck %s # RUN: llc -relocation-model=pic -start-after=block-placement -o - %s -ppc-strip-register-prefix | FileCheck %s
--- | --- |
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@x = internal thread_local unnamed_addr global i1 false @x = internal thread_local unnamed_addr global i1 false
@y = external thread_local global i32, align 4 @y = external thread_local global i32, align 4
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test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll

; RUN: llc -verify-machineinstrs %s -mtriple=powerpc64-unknown-linux-gnu -O2 -o - -optimize-regalloc=false -regalloc=fast | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -O2 -o - \
; RUN: -optimize-regalloc=false -regalloc=fast | FileCheck %s
declare void @func(i8*, i64, i64) declare void @func(i8*, i64, i64)
define void @test(i8* %context, i32** %elementArrayPtr, i32 %value) { define void @test(i8* %context, i32** %elementArrayPtr, i32 %value) {
entry: entry:
%cmp = icmp eq i32 %value, 0 %cmp = icmp eq i32 %value, 0
br i1 %cmp, label %lreturn, label %lnext br i1 %cmp, label %lreturn, label %lnext
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test/CodeGen/PowerPC/alias.ll

; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -code-model=medium| FileCheck --check-prefix=CHECK --check-prefix=MEDIUM %s ; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -code-model=large | FileCheck --check-prefix=CHECK --check-prefix=LARGE %s ; RUN: -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -code-model=medium| FileCheck --check-prefix=CHECK \
; RUN: --check-prefix=MEDIUM %s
; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -code-model=large | FileCheck --check-prefix=CHECK \
; RUN: --check-prefix=LARGE %s
@foo = global i32 42 @foo = global i32 42
@fooa = alias i32, i32* @foo @fooa = alias i32, i32* @foo
@foo2 = global i64 42 @foo2 = global i64 42
@foo2a = alias i64, i64* @foo2 @foo2a = alias i64, i64* @foo2
; CHECK-LABEL: bar: ; CHECK-LABEL: bar:
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test/CodeGen/PowerPC/allocate-r0.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i64 @foo(i64 %a) nounwind { define i64 @foo(i64 %a) nounwind {
entry: entry:
call void asm sideeffect "", "~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12}"() nounwind call void asm sideeffect "", "~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12}"() nounwind
br label %return br label %return
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test/CodeGen/PowerPC/anon_aggr.ll

; RUN: llc -verify-machineinstrs -O0 -mcpu=ppc64 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s ; RUN: -O0 -mcpu=ppc64 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -verify-machineinstrs -O0 -mcpu=970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s ; RUN: -fast-isel=false < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -O0 \
; RUN: -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s \
; RUN: | FileCheck -check-prefix=DARWIN32 %s
; RUN: llc -verify-machineinstrs \
; RUN: -O0 -mcpu=970 -mtriple=powerpc64-apple-darwin8 < %s \
; RUN: | FileCheck -check-prefix=DARWIN64 %s
; Test case for PR 14779: anonymous aggregates are not handled correctly. ; Test case for PR 14779: anonymous aggregates are not handled correctly.
; Darwin bug report PR 15821 is similar. ; Darwin bug report PR 15821 is similar.
; The bug is triggered by passing a byval structure after an anonymous ; The bug is triggered by passing a byval structure after an anonymous
; aggregate. ; aggregate.
%tarray = type { i64, i8* } %tarray = type { i64, i8* }
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test/CodeGen/PowerPC/anyext_srl.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mcpu=pwr8 < %s | FileCheck %s
%class.PB2 = type { [1 x i32], %class.PB1* } %class.PB2 = type { [1 x i32], %class.PB1* }
%class.PB1 = type { [1 x i32], i64, i64, i32 } %class.PB1 = type { [1 x i32], i64, i64, i32 }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define zeroext i1 @foo(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr { define zeroext i1 @foo(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr {
entry: entry:
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test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=ppc64 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @bar() #0 { define void @bar() #0 {
entry: entry:
tail call void @xxx([2 x i64] [i64 4607182418800017408, i64 4611686018427387904]) #0 tail call void @xxx([2 x i64] [i64 4607182418800017408, i64 4611686018427387904]) #0
ret void ret void
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test/CodeGen/PowerPC/asm-Zy.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=a2 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: < %s -mcpu=a2 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
define i32 @zytest(i32 %a) nounwind { define i32 @zytest(i32 %a) nounwind {
entry: entry:
; CHECK: @zytest ; CHECK: @zytest
%r = call i32 asm "lwbrx $0, ${1:y}", "=r,Z"(i32 %a) nounwind, !srcloc !0 %r = call i32 asm "lwbrx $0, ${1:y}", "=r,Z"(i32 %a) nounwind, !srcloc !0
ret i32 %r ret i32 %r
; CHECK: lwbrx 3, 0, ; CHECK: lwbrx 3, 0,
} }
!0 = !{i32 101688} !0 = !{i32 101688}

test/CodeGen/PowerPC/asm-constraints.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=pwr8 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: < %s -mcpu=pwr8 | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
; Check that we accept 'U' and 'X' constraints. ; Check that we accept 'U' and 'X' constraints.
; Generated from following C code: ; Generated from following C code:
; ;
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test/CodeGen/PowerPC/atomic-minmax.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @a32min(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 { define void @a32min(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
entry: entry:
%0 = atomicrmw min i32* %minimum, i32 %val monotonic %0 = atomicrmw min i32* %minimum, i32 %val monotonic
ret void ret void
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test/CodeGen/PowerPC/atomics-constant.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix | FileCheck %s
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@a = constant i64 zeroinitializer @a = constant i64 zeroinitializer
define i64 @foo() { define i64 @foo() {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
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test/CodeGen/PowerPC/atomics-regression.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE ; RUN: llc -ppc-strip-register-prefix -mtriple=powerpc64le-linux-gnu \
; RUN: < %s | FileCheck %s -check-prefix=PPC64LE
define i8 @test0(i8* %ptr) { define i8 @test0(i8* %ptr) {
; PPC64LE-LABEL: test0: ; PPC64LE-LABEL: test0:
; PPC64LE: # BB#0: ; PPC64LE: # BB#0:
; PPC64LE-NEXT: lbz 3, 0(3) ; PPC64LE-NEXT: lbz 3, 0(3)
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%val = load atomic i8, i8* %ptr unordered, align 1 %val = load atomic i8, i8* %ptr unordered, align 1
ret i8 %val ret i8 %val
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test/CodeGen/PowerPC/big-endian-actual-args.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep "addc 4, 4, 6" ; RUN: grep "addc 4, 4, 6"
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep "adde 3, 3, 5" ; RUN: grep "adde 3, 3, 5"
define i64 @foo(i64 %x, i64 %y) { define i64 @foo(i64 %x, i64 %y) {
%z = add i64 %x, %y %z = add i64 %x, %y
ret i64 %z ret i64 %z
} }

test/CodeGen/PowerPC/big-endian-call-result.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: < %s -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep "addic 4, 4, 1" ; RUN: grep "addic 4, 4, 1"
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: < %s -mtriple=powerpc-unknown-linux-gnu | \
; RUN: grep "addze 3, 3" ; RUN: grep "addze 3, 3"
declare i64 @foo() declare i64 @foo()
define i64 @bar() define i64 @bar()
{ {
%t = call i64 @foo() %t = call i64 @foo()
%s = add i64 %t, 1 %s = add i64 %t, 1
ret i64 %s ret i64 %s
} }

test/CodeGen/PowerPC/big-endian-formal-args.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
declare void @bar(i64 %x, i64 %y) declare void @bar(i64 %x, i64 %y)
; CHECK: li 3, 0 ; CHECK: li 3, 0
; CHECK: li 4, 2 ; CHECK: li 4, 2
; CHECK: li 5, 0 ; CHECK: li 5, 0
; CHECK: li 6, 3 ; CHECK: li 6, 3
define void @foo() { define void @foo() {
call void @bar(i64 2, i64 3) call void @bar(i64 2, i64 3)
ret void ret void
} }

test/CodeGen/PowerPC/blockaddress.ll

; RUN: llc -verify-machineinstrs < %s -code-model=small -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=SMALL ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -code-model=medium -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM ; RUN: -code-model=small -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -verify-machineinstrs < %s -code-model=large -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM ; RUN: | FileCheck %s -check-prefix=SMALL
; RUN: llc -verify-machineinstrs < %s -code-model=small -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=SMALL ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -code-model=medium -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM ; RUN: -code-model=medium -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -verify-machineinstrs < %s -code-model=large -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=MEDIUM ; RUN: | FileCheck %s -check-prefix=MEDIUM
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -code-model=large -mtriple=powerpc64-unknown-linux-gnu \
; RUN: | FileCheck %s -check-prefix=MEDIUM
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -code-model=small -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: | FileCheck %s -check-prefix=SMALL
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -code-model=medium -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: | FileCheck %s -check-prefix=MEDIUM
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -code-model=large -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: | FileCheck %s -check-prefix=MEDIUM
define i8* @test() { define i8* @test() {
entry: entry:
br label %here br label %here
here: ; preds = %entry here: ; preds = %entry
; MEDIUM: .Ltmp[[TMP0:[0-9]+]]: ; MEDIUM: .Ltmp[[TMP0:[0-9]+]]:
; MEDIUM: addis [[R0:[0-9]+]], 2, .LC[[LC0:[0-9]+]]@toc@ha ; MEDIUM: addis [[R0:[0-9]+]], 2, .LC[[LC0:[0-9]+]]@toc@ha
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test/CodeGen/PowerPC/bperm.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define zeroext i32 @bs4(i32 zeroext %a) #0 { define zeroext i32 @bs4(i32 zeroext %a) #0 {
entry: entry:
%0 = tail call i32 @llvm.bswap.i32(i32 %a) %0 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %0 ret i32 %0
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test/CodeGen/PowerPC/branch_coalesce.ll

; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s ; RUN: -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s ; RUN: llc -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs \
; RUN: -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefix=CHECK-NOCOALESCE %s
; RUN: llc -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefix=CHECK-NOCOALESCE %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define double @testBranchCoal(double %a, double %b, double %c, i32 %x) { define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
; CHECK-LABEL: @testBranchCoal ; CHECK-LABEL: @testBranchCoal
; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0 ; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]] ; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]]
; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha ; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha
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test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
@vda = common global <2 x double> zeroinitializer, align 16 @vda = common global <2 x double> zeroinitializer, align 16
@vdb = common global <2 x double> zeroinitializer, align 16 @vdb = common global <2 x double> zeroinitializer, align 16
@vdr = common global <2 x double> zeroinitializer, align 16 @vdr = common global <2 x double> zeroinitializer, align 16
@vfa = common global <4 x float> zeroinitializer, align 16 @vfa = common global <4 x float> zeroinitializer, align 16
@vfb = common global <4 x float> zeroinitializer, align 16 @vfb = common global <4 x float> zeroinitializer, align 16
@vfr = common global <4 x float> zeroinitializer, align 16 @vfr = common global <4 x float> zeroinitializer, align 16
@vbllr = common global <2 x i64> zeroinitializer, align 16 @vbllr = common global <2 x i64> zeroinitializer, align 16
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test/CodeGen/PowerPC/builtins-ppc-p8vector.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+power8-vector -mattr=-vsx < %s | FileCheck %s ; RUN: | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-VSX ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \
; RUN: | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+power8-vector \
; RUN: -mattr=-vsx < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-VSX
@vsc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 @vsc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
@vsc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 @vsc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
@vuc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 @vuc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
@vuc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 @vuc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
@res_vll = common global <2 x i64> zeroinitializer, align 16 @res_vll = common global <2 x i64> zeroinitializer, align 16
@res_vull = common global <2 x i64> zeroinitializer, align 16 @res_vull = common global <2 x i64> zeroinitializer, align 16
@res_vsc = common global <16 x i8> zeroinitializer, align 16 @res_vsc = common global <16 x i8> zeroinitializer, align 16
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test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll

; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <4 x i32> @test1(<4 x i32> %a) { define <4 x i32> @test1(<4 x i32> %a) {
entry: entry:
; CHECK-LABEL: test1 ; CHECK-LABEL: test1
; CHECK: xxswapd 34, 34 ; CHECK: xxswapd 34, 34
%vecins6 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1> %vecins6 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
ret <4 x i32> %vecins6 ret <4 x i32> %vecins6
} }
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test/CodeGen/PowerPC/cc.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i64 @test1(i64 %a, i64 %b) { define i64 @test1(i64 %a, i64 %b) {
entry: entry:
%c = icmp eq i64 %a, %b %c = icmp eq i64 %a, %b
br label %foo br label %foo
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test/CodeGen/PowerPC/cmp_elimination.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
; Test cases for compare elimination in PPCMIPeephole pass ; Test cases for compare elimination in PPCMIPeephole pass
define void @func1(i32 signext %a) { define void @func1(i32 signext %a) {
; We should have only one compare instruction ; We should have only one compare instruction
; CHECK-LABEL: @func1 ; CHECK-LABEL: @func1
; CHECK: cmp ; CHECK: cmp
; CHECK-NOT: cmp ; CHECK-NOT: cmp
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test/CodeGen/PowerPC/cmpb-ppc32.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: < %s | FileCheck %s
target datalayout = "E-m:e-p:32:32-i64:64-n32" target datalayout = "E-m:e-p:32:32-i64:64-n32"
target triple = "powerpc-unknown-linux-gnu" target triple = "powerpc-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 { define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 {
entry: entry:
%0 = xor i16 %y, %x %0 = xor i16 %y, %x
%1 = and i16 %0, 255 %1 = and i16 %0, 255
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test/CodeGen/PowerPC/cmpb.ll

; RUN: llc -verify-machineinstrs -mcpu pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 { define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 {
entry: entry:
%0 = xor i16 %y, %x %0 = xor i16 %y, %x
%1 = and i16 %0, 255 %1 = and i16 %0, 255
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test/CodeGen/PowerPC/complex-return.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 -O0 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=ppc64 \
; RUN: -O0 < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define { ppc_fp128, ppc_fp128 } @foo() nounwind { define { ppc_fp128, ppc_fp128 } @foo() nounwind {
entry: entry:
%retval = alloca { ppc_fp128, ppc_fp128 }, align 16 %retval = alloca { ppc_fp128, ppc_fp128 }, align 16
%x = alloca { ppc_fp128, ppc_fp128 }, align 16 %x = alloca { ppc_fp128, ppc_fp128 }, align 16
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test/CodeGen/PowerPC/constants-i64.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=ppc64 < %s \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define i64 @cn1() #0 { define i64 @cn1() #0 {
entry: entry:
ret i64 281474976710655 ret i64 281474976710655
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test/CodeGen/PowerPC/copysignl.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=-vsx < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s -check-prefix=CHECK-VSX ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=-vsx < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-VSX
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define double @foo_d_ll(ppc_fp128 %a, ppc_fp128 %b) #0 { define double @foo_d_ll(ppc_fp128 %a, ppc_fp128 %b) #0 {
entry: entry:
%call = tail call ppc_fp128 @copysignl(ppc_fp128 %a, ppc_fp128 %b) #0 %call = tail call ppc_fp128 @copysignl(ppc_fp128 %a, ppc_fp128 %b) #0
%conv = fptrunc ppc_fp128 %call to double %conv = fptrunc ppc_fp128 %call to double
ret double %conv ret double %conv
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test/CodeGen/PowerPC/crbit-asm.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s ; RUN: -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: -O1 -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr7 -ppc-gen-isel=false < %s \
; RUN: | FileCheck --check-prefix=CHECK-NO-ISEL %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -O1 -mcpu=pwr7 -ppc-gen-isel=false < %s \
; RUN: | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 { define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
entry: entry:
%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0 %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
%1 = and i8 %0, 1 %1 = and i8 %0, 1
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test/CodeGen/PowerPC/crsave.ll

; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32 ; RUN: llc -O0 -ppc-strip-register-prefix -disable-fp-elim \
; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64 ; RUN: -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s \
; RUN: llc -O0 -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s -check-prefix=PPC64-ELFv2 ; RUN: | FileCheck %s -check-prefix=PPC32
; RUN: llc -O0 -ppc-strip-register-prefix -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64
; RUN: llc -O0 -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=PPC64-ELFv2
declare void @foo() declare void @foo()
define i32 @test_cr2() nounwind uwtable { define i32 @test_cr2() nounwind uwtable {
entry: entry:
%ret = alloca i32, align 4 %ret = alloca i32, align 4
%0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
store i32 %0, i32* %ret, align 4 store i32 %0, i32* %ret, align 4
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test/CodeGen/PowerPC/crypto_bifs.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+crypto < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+crypto < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
; FIXME: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; FIXME: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
; FIXME: The original intent was to add a check-next for the blr after every check. ; FIXME: The original intent was to add a check-next for the blr after every check.
; However, this currently fails since we don't eliminate stores of the unused ; However, this currently fails since we don't eliminate stores of the unused
; locals. These stores are sometimes scheduled after the crypto instruction ; locals. These stores are sometimes scheduled after the crypto instruction
; Function Attrs: nounwind ; Function Attrs: nounwind
define <16 x i8> @test_vpmsumb() #0 { define <16 x i8> @test_vpmsumb() #0 {
entry: entry:
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test/CodeGen/PowerPC/ctr-cleanup.ll

; RUN: llc < %s -mcpu=a2 | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix -mcpu=a2 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @main() #0 { define void @main() #0 {
entry: entry:
br i1 undef, label %for.end, label %for.body br i1 undef, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
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test/CodeGen/PowerPC/div-e-32.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define signext i32 @test1() #0 { define signext i32 @test1() #0 {
entry: entry:
%0 = call i32 @llvm.ppc.divwe(i32 32, i32 16) %0 = call i32 @llvm.ppc.divwe(i32 32, i32 16)
ret i32 %0 ret i32 %0
; CHECK: divwe 3, 4, 3 ; CHECK: divwe 3, 4, 3
} }
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test/CodeGen/PowerPC/div-e-all.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define signext i32 @test1() #0 { define signext i32 @test1() #0 {
entry: entry:
%0 = call i32 @llvm.ppc.divwe(i32 32, i32 16) %0 = call i32 @llvm.ppc.divwe(i32 32, i32 16)
ret i32 %0 ret i32 %0
; CHECK: divwe 3, 4, 3 ; CHECK: divwe 3, 4, 3
} }
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test/CodeGen/PowerPC/dyn-alloca-aligned.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.s = type { i32, i32 } %struct.s = type { i32, i32 }
declare void @bar(i32*, i32*) #0 declare void @bar(i32*, i32*) #0
define void @goo(%struct.s* byval nocapture readonly %a, i32 signext %n) #0 { define void @goo(%struct.s* byval nocapture readonly %a, i32 signext %n) #0 {
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test/CodeGen/PowerPC/dyn-alloca-offset.ll

; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
declare i64 @llvm.get.dynamic.area.offset.i64() declare i64 @llvm.get.dynamic.area.offset.i64()
declare i64 @bar(i64) declare i64 @bar(i64)
attributes #0 = { nounwind } attributes #0 = { nounwind }
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test/CodeGen/PowerPC/eh-dwarf-cfa.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
define void @_Z1fv() #0 { define void @_Z1fv() #0 {
entry: entry:
%0 = call i8* @llvm.eh.dwarf.cfa(i32 0) %0 = call i8* @llvm.eh.dwarf.cfa(i32 0)
call void @_Z1gPv(i8* %0) call void @_Z1gPv(i8* %0)
ret void ret void
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test/CodeGen/PowerPC/empty-functions.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin | FileCheck -check-prefix=CHECK-MACHO %s ; RUN: llc -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin -disable-fp-elim | FileCheck -check-prefix=CHECK-MACHO %s ; RUN: -mtriple=powerpc-apple-darwin | FileCheck -check-prefix=CHECK-MACHO %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-linux-gnu | FileCheck -check-prefix=LINUX-NO-FP %s ; RUN: llc -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-linux-gnu -disable-fp-elim | FileCheck -check-prefix=LINUX-FP %s ; RUN: -mtriple=powerpc-apple-darwin -disable-fp-elim | FileCheck -check-prefix=CHECK-MACHO %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc-linux-gnu | FileCheck -check-prefix=LINUX-NO-FP %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc-linux-gnu -disable-fp-elim | FileCheck \
; RUN: -check-prefix=LINUX-FP %s
define void @func() { define void @func() {
entry: entry:
unreachable unreachable
} }
; MachO cannot handle an empty function. ; MachO cannot handle an empty function.
; CHECK-MACHO: _func: ; CHECK-MACHO: _func:
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test/CodeGen/PowerPC/emptystruct.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -O0 -fast-isel=false < %s | FileCheck %s
; This tests correct handling of empty aggregate parameters and return values. ; This tests correct handling of empty aggregate parameters and return values.
; An empty parameter passed by value does not consume a protocol register or ; An empty parameter passed by value does not consume a protocol register or
; a parameter save area doubleword. An empty parameter passed by reference ; a parameter save area doubleword. An empty parameter passed by reference
; is treated as any other pointer parameter. An empty aggregate return value ; is treated as any other pointer parameter. An empty aggregate return value
; is treated as any other aggregate return value, passed via address as a ; is treated as any other aggregate return value, passed via address as a
; hidden parameter in GPR3. In this example, GPR3 contains the return value ; hidden parameter in GPR3. In this example, GPR3 contains the return value
; address, GPR4 contains the address of e2, and e1 and e3 are not passed or ; address, GPR4 contains the address of e2, and e1 and e3 are not passed or
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test/CodeGen/PowerPC/extra-toc-reg-deps.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
%"class.Foam::messageStream.6" = type <{ %"class.Foam::string.5", i32, i32, i32, [4 x i8] }> %"class.Foam::messageStream.6" = type <{ %"class.Foam::string.5", i32, i32, i32, [4 x i8] }>
%"class.Foam::string.5" = type { %"class.std::basic_string.4" } %"class.Foam::string.5" = type { %"class.std::basic_string.4" }
%"class.std::basic_string.4" = type { %"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider.3" } %"class.std::basic_string.4" = type { %"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider.3" }
%"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider.3" = type { i8* } %"struct.std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider.3" = type { i8* }
%"class.Foam::prefixOSstream.27" = type { %"class.Foam::OSstream.26", i8, %"class.Foam::string.5" } %"class.Foam::prefixOSstream.27" = type { %"class.Foam::OSstream.26", i8, %"class.Foam::string.5" }
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test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
%struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] } %struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
%struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] } %struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
@arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4 @arr = common global [2 x [2 x [2 x [2 x [2 x i32]]]]] zeroinitializer, align 4
@A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4 @A = common global [3 x [3 x %struct.A]] zeroinitializer, align 4
@B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4 @B = common global [2 x [2 x [2 x %struct.B]]] zeroinitializer, align 4
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test/CodeGen/PowerPC/fast-isel-call.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
define i32 @t1(i8 signext %a) nounwind { define i32 @t1(i8 signext %a) nounwind {
%1 = sext i8 %a to i32 %1 = sext i8 %a to i32
ret i32 %1 ret i32 %1
} }
define i32 @t2(i8 zeroext %a) nounwind { define i32 @t2(i8 zeroext %a) nounwind {
%1 = zext i8 %a to i32 %1 = zext i8 %a to i32
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test/CodeGen/PowerPC/fast-isel-cmp-imm.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
define void @t1a(float %a) nounwind { define void @t1a(float %a) nounwind {
entry: entry:
; ELF64: t1a ; ELF64: t1a
%cmp = fcmp oeq float %a, 0.000000e+00 %cmp = fcmp oeq float %a, 0.000000e+00
; ELF64: addis ; ELF64: addis
; ELF64: lfs ; ELF64: lfs
; ELF64: fcmpu ; ELF64: fcmpu
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
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test/CodeGen/PowerPC/fast-isel-const.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
define zeroext i1 @testi1(i8 %in) nounwind { define zeroext i1 @testi1(i8 %in) nounwind {
entry: entry:
%c = icmp eq i8 %in, 5 %c = icmp eq i8 %in, 5
br i1 %c, label %true, label %false br i1 %c, label %true, label %false
; ELF64-LABEL: @testi1 ; ELF64-LABEL: @testi1
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test/CodeGen/PowerPC/fast-isel-conversion-p5.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -verify-machineinstrs \
; RUN: -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr5 -ppc-strip-register-prefix \
; RUN: | FileCheck %s --check-prefix=ELF64
; Test sitofp ; Test sitofp
define void @sitofp_double_i32(i32 %a, double %b) nounwind { define void @sitofp_double_i32(i32 %a, double %b) nounwind {
entry: entry:
; ELF64: sitofp_double_i32 ; ELF64: sitofp_double_i32
%b.addr = alloca double, align 8 %b.addr = alloca double, align 8
%conv = sitofp i32 %a to double %conv = sitofp i32 %a to double
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test/CodeGen/PowerPC/fast-isel-conversion.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s ; RUN: llc < %s -O0 -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s ; RUN: -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970 ; RUN: -mcpu=pwr7 -mattr=-vsx | FileCheck %s
; RUN: llc < %s -O0 -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx | FileCheck %s
; RUN: llc < %s -O0 -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx \
; RUN: | FileCheck %s --check-prefix=PPC970
;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt ;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
;; to SelectionDAG in some cases. ;; to SelectionDAG in some cases.
; Test sitofp ; Test sitofp
define void @sitofp_single_i64(i64 %a, float %b) nounwind { define void @sitofp_single_i64(i64 %a, float %b) nounwind {
entry: entry:
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test/CodeGen/PowerPC/fast-isel-ext.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; zext ; zext
define i32 @zext_8_32(i8 %a) nounwind { define i32 @zext_8_32(i8 %a) nounwind {
; ELF64: zext_8_32 ; ELF64: zext_8_32
%r = zext i8 %a to i32 %r = zext i8 %a to i32
; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 ; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
ret i32 %r ret i32 %r
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test/CodeGen/PowerPC/fast-isel-fpconv.ll

; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple powerpc64-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
; The second fctiwz would use an incorrect input register due to wrong handling ; The second fctiwz would use an incorrect input register due to wrong handling
; of COPY_TO_REGCLASS in the FastISel pass. Verify that this is fixed. ; of COPY_TO_REGCLASS in the FastISel pass. Verify that this is fixed.
declare void @func(i32, i32) declare void @func(i32, i32)
define void @test() { define void @test() {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
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test/CodeGen/PowerPC/fast-isel-indirectbr.ll

; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
define void @t1(i8* %x) nounwind { define void @t1(i8* %x) nounwind {
entry: entry:
; ELF64: t1 ; ELF64: t1
br label %L0 br label %L0
L0: L0:
br label %L1 br label %L1
L1: L1:
indirectbr i8* %x, [ label %L0, label %L1 ] indirectbr i8* %x, [ label %L0, label %L1 ]
; ELF64: mtctr 3 ; ELF64: mtctr 3
; ELF64: bctr ; ELF64: bctr
} }

test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll

; RUN: llc < %s -O0 -fast-isel -mattr=+vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64VSX ; RUN: llc < %s -O0 -ppc-strip-register-prefix -fast-isel -mattr=+vsx \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: | FileCheck %s --check-prefix=ELF64VSX
;; The semantics of VSX stores for when R0 is used is different depending on ;; The semantics of VSX stores for when R0 is used is different depending on
;; whether it is used as base or offset. If used as base, the effective ;; whether it is used as base or offset. If used as base, the effective
;; address computation will use zero regardless of the content of R0. If used as ;; address computation will use zero regardless of the content of R0. If used as
;; an offset the content will be used in the effective address. We observed that ;; an offset the content will be used in the effective address. We observed that
;; for some constructors, the initialization values were being stored without ;; for some constructors, the initialization values were being stored without
;; an offset register being specified which was causing R0 to be used as offset ;; an offset register being specified which was causing R0 to be used as offset
;; in regions where it contained the value in the link register. This test ;; in regions where it contained the value in the link register. This test
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test/CodeGen/PowerPC/fast-isel-ret.ll

; FIXME: FastISel currently returns false if it hits code that uses VSX ; FIXME: FastISel currently returns false if it hits code that uses VSX
; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
; When fastisel better supports VSX fix up this test case. ; When fastisel better supports VSX fix up this test case.
; ;
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 ; RUN: llc < %s -O0 -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
define zeroext i1 @rettrue() nounwind { define zeroext i1 @rettrue() nounwind {
entry: entry:
; ELF64-LABEL: rettrue ; ELF64-LABEL: rettrue
; ELF64: li 3, 1 ; ELF64: li 3, 1
; ELF64: blr ; ELF64: blr
ret i1 true ret i1 true
} }
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test/CodeGen/PowerPC/fcpsgn.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: -mattr=-vsx < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define double @foo_dd(double %a, double %b) #0 { define double @foo_dd(double %a, double %b) #0 {
entry: entry:
%call = tail call double @copysign(double %a, double %b) #0 %call = tail call double @copysign(double %a, double %b) #0
ret double %call ret double %call
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test/CodeGen/PowerPC/fdiv-combine.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=ppc64 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Following test case checks: ; Following test case checks:
; a / D; b / D; c / D; ; a / D; b / D; c / D;
; => ; =>
; recip = 1.0 / D; a * recip; b * recip; c * recip; ; recip = 1.0 / D; a * recip; b * recip; c * recip;
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test/CodeGen/PowerPC/float-to-int.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=a2 | FileCheck %s ; RUN: -mcpu=a2 | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=g5 ; RUN: -mcpu=g5
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck -check-prefix=CHECK-P9 %s ; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck -check-prefix=CHECK-P9 %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i64 @foo(float %a) nounwind { define i64 @foo(float %a) nounwind {
%x = fptosi float %a to i64 %x = fptosi float %a to i64
ret i64 %x ret i64 %x
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test/CodeGen/PowerPC/floatPSA.ll

; RUN: llc -verify-machineinstrs -O2 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -O2 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s \
; RUN: | FileCheck %s
; This verifies that single-precision floating point values that can't ; This verifies that single-precision floating point values that can't
; be passed in registers are stored in the rightmost word of the parameter ; be passed in registers are stored in the rightmost word of the parameter
; save area slot. There are 13 architected floating-point registers, so ; save area slot. There are 13 architected floating-point registers, so
; the 14th is passed in storage. The address of the 14th argument is ; the 14th is passed in storage. The address of the 14th argument is
; 48 (fixed size of the linkage area) + 13 * 8 (first 13 args) + 4 ; 48 (fixed size of the linkage area) + 13 * 8 (first 13 args) + 4
; (offset to second word) = 156. ; (offset to second word) = 156.
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test/CodeGen/PowerPC/fma-aggr-FMF.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-linux-gnu | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-linux-gnu | FileCheck %s
define float @can_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) { define float @can_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) {
; CHECK-LABEL: can_fma_with_fewer_uses: ; CHECK-LABEL: can_fma_with_fewer_uses:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: xsmulsp 0, 1, 2 ; CHECK-NEXT: xsmulsp 0, 1, 2
; CHECK-NEXT: fmr 1, 0 ; CHECK-NEXT: fmr 1, 0
; CHECK-NEXT: xsmaddasp 1, 3, 4 ; CHECK-NEXT: xsmaddasp 1, 3, 4
; CHECK-NEXT: xsdivsp 1, 0, 1 ; CHECK-NEXT: xsdivsp 1, 0, 1
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test/CodeGen/PowerPC/fma-mutate.ll

; Test several VSX FMA mutation opportunities. The first one isn't a ; Test several VSX FMA mutation opportunities. The first one isn't a
; reasonable transformation because the killed product register is the ; reasonable transformation because the killed product register is the
; same as the FMA target register. The second one is legal. The third ; same as the FMA target register. The second one is legal. The third
; one doesn't fit the feeding-copy pattern. ; one doesn't fit the feeding-copy pattern.
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math -mattr=+vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math \
; RUN: -mattr=+vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
declare double @llvm.sqrt.f64(double) declare double @llvm.sqrt.f64(double)
define double @foo3(double %a) nounwind { define double @foo3(double %a) nounwind {
%r = call double @llvm.sqrt.f64(double %a) %r = call double @llvm.sqrt.f64(double %a)
ret double %r ret double %r
; CHECK: @foo3 ; CHECK: @foo3
; CHECK: xsnmsubadp [[REG:[0-9]+]], {{[0-9]+}}, [[REG]] ; CHECK: xsnmsubadp [[REG:[0-9]+]], {{[0-9]+}}, [[REG]]
; CHECK: xsmaddmdp ; CHECK: xsmaddmdp
; CHECK: xsmaddadp ; CHECK: xsmaddadp
} }

test/CodeGen/PowerPC/fold-zero.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-CRB %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits \
; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: | FileCheck --check-prefix=CHECK-CRB %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -ppc-gen-isel=false < %s -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr7 | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i32 @test1(i1 %a, i32 %c) nounwind { define i32 @test1(i1 %a, i32 %c) nounwind {
%x = select i1 %a, i32 %c, i32 0 %x = select i1 %a, i32 %c, i32 0
ret i32 %x ret i32 %x
; CHECK-LABEL: @test1 ; CHECK-LABEL: @test1
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test/CodeGen/PowerPC/fp-to-int-ext.ll

; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=a2 < %s \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define double @foo1(i32* %x) #0 { define double @foo1(i32* %x) #0 {
entry: entry:
%0 = load i32, i32* %x, align 4 %0 = load i32, i32* %x, align 4
%conv = sext i32 %0 to i64 %conv = sext i32 %0 to i64
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test/CodeGen/PowerPC/fp-to-int-to-fp.ll

; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s -check-prefix=FPCVT ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s -check-prefix=PPC64 ; RUN: -mcpu=a2 < %s | FileCheck %s -check-prefix=FPCVT
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=ppc64 < %s | FileCheck %s -check-prefix=PPC64
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define float @fool(float %X) #0 { define float @fool(float %X) #0 {
entry: entry:
%conv = fptosi float %X to i64 %conv = fptosi float %X to i64
%conv1 = sitofp i64 %conv to float %conv1 = sitofp i64 %conv to float
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test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8 ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64 ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8 ; RUN: | FileCheck %s -check-prefix=PPC64-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64 ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32 ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s \
; RUN: | FileCheck %s -check-prefix=PPC64
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s \
; RUN: | FileCheck %s -check-prefix=PPC64-P8
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s \
; RUN: | FileCheck %s -check-prefix=PPC64
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s \
; RUN: -check-prefix=PPC32
define i128 @test_abs(ppc_fp128 %x) nounwind { define i128 @test_abs(ppc_fp128 %x) nounwind {
entry: entry:
; PPC64-LABEL: test_abs: ; PPC64-LABEL: test_abs:
; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]] ; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]]
; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]] ; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]]
; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]] ; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]] ; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
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test/CodeGen/PowerPC/fp64-to-int16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -O0 < %s | FileCheck %s
target triple = "powerpc64le--linux-gnu" target triple = "powerpc64le--linux-gnu"
define i1 @Test(double %a) { define i1 @Test(double %a) {
; CHECK-LABEL: Test: ; CHECK-LABEL: Test:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: xscvdpsxws 1, 1 ; CHECK-NEXT: xscvdpsxws 1, 1
; CHECK-NEXT: mfvsrwz 3, 1 ; CHECK-NEXT: mfvsrwz 3, 1
; CHECK-NEXT: xori 3, 3, 65534 ; CHECK-NEXT: xori 3, 3, 65534
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test/CodeGen/PowerPC/frame-size.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
define i64 @foo() nounwind { define i64 @foo() nounwind {
entry: entry:
%x = alloca [32568 x i8] %x = alloca [32568 x i8]
%"alloca point" = bitcast i32 0 to i32 %"alloca point" = bitcast i32 0 to i32
%x1 = bitcast [32568 x i8]* %x to i8* %x1 = bitcast [32568 x i8]* %x to i8*
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test/CodeGen/PowerPC/frameaddr.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mcpu=pwr7 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
declare void @llvm.eh.sjlj.longjmp(i8*) #1 declare void @llvm.eh.sjlj.longjmp(i8*) #1
define i8* @main() #0 { define i8* @main() #0 {
entry: entry:
%0 = call i8* @llvm.frameaddress(i32 0) %0 = call i8* @llvm.frameaddress(i32 0)
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test/CodeGen/PowerPC/fsel.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s ; RUN: | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx \
; RUN: | FileCheck -check-prefix=CHECK-FM %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx \
; RUN: | FileCheck -check-prefix=CHECK-FM-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define double @zerocmp1(double %a, double %y, double %z) #0 { define double @zerocmp1(double %a, double %y, double %z) #0 {
entry: entry:
%cmp = fcmp ult double %a, 0.000000e+00 %cmp = fcmp ult double %a, 0.000000e+00
%z.y = select i1 %cmp, double %z, double %y %z.y = select i1 %cmp, double %z, double %y
ret double %z.y ret double %z.y
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test/CodeGen/PowerPC/func-addr.ll

; RUN: llc -relocation-model=static -verify-machineinstrs -mtriple powerpc64-linux < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: llc -relocation-model=static -verify-machineinstrs -O0 -mtriple powerpc64-linux < %s | FileCheck %s ; RUN: -verify-machineinstrs -mtriple powerpc64-linux < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: -verify-machineinstrs -O0 -mtriple powerpc64-linux < %s | FileCheck %s
define void @foo() { define void @foo() {
ret void ret void
} }
declare i32 @bar(i8*) declare i32 @bar(i8*)
; CHECK-LABEL: {{^}}zed: ; CHECK-LABEL: {{^}}zed:
; CHECK: addis 3, 2, foo@toc@ha ; CHECK: addis 3, 2, foo@toc@ha
; CHECK-NEXT: addi 3, 3, foo@toc@l ; CHECK-NEXT: addi 3, 3, foo@toc@l
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
define void @zed() { define void @zed() {
call i32 @bar(i8* bitcast (void ()* @foo to i8*)) call i32 @bar(i8* bitcast (void ()* @foo to i8*))
ret void ret void
} }

test/CodeGen/PowerPC/gpr-vsr-spill.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr9 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills \
; RUN: < %s | FileCheck %s
define signext i32 @foo(i32 signext %a, i32 signext %b) { define signext i32 @foo(i32 signext %a, i32 signext %b) {
entry: entry:
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29}"(i32 %a, i32 %b)
%mul = mul nsw i32 %0, %a %mul = mul nsw i32 %0, %a
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test/CodeGen/PowerPC/htm.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define zeroext i32 @test1() { define zeroext i32 @test1() {
entry: entry:
%0 = tail call i32 @llvm.ppc.tbegin(i32 0) %0 = tail call i32 @llvm.ppc.tbegin(i32 0)
ret i32 %0 ret i32 %0
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test/CodeGen/PowerPC/i1-ext-fold.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck \
; RUN: --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define signext i32 @foo(i32 signext %a, i32 signext %b) #0 { define signext i32 @foo(i32 signext %a, i32 signext %b) #0 {
entry: entry:
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
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test/CodeGen/PowerPC/i1-to-double.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc32 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=ppc32 \
; RUN: -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
define double @test(i1 %X) { define double @test(i1 %X) {
%Y = uitofp i1 %X to double %Y = uitofp i1 %X to double
ret double %Y ret double %Y
} }
; CHECK-LABEL: @test ; CHECK-LABEL: @test
; CHECK: andi. {{[0-9]+}}, 3, 1 ; CHECK: andi. {{[0-9]+}}, 3, 1
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test/CodeGen/PowerPC/i32-to-float.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx \
; RUN: | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define float @foo(i32 %a) nounwind { define float @foo(i32 %a) nounwind {
entry: entry:
%x = sitofp i32 %a to float %x = sitofp i32 %a to float
ret float %x ret float %x
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test/CodeGen/PowerPC/i64-to-float.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mcpu=a2 | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: | FileCheck -check-prefix=CHECK-VSX %s
; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9 ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -mattr=-direct-move \
; RUN: | FileCheck %s -check-prefix=CHECK-P9
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define float @foo(i64 %a) nounwind { define float @foo(i64 %a) nounwind {
entry: entry:
%x = sitofp i64 %a to float %x = sitofp i64 %a to float
ret float %x ret float %x
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test/CodeGen/PowerPC/i64_fp_round.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -ppc-gen-isel=false < %s | FileCheck %s --check-prefix=CHECK-NO-ISEL ; RUN: -mattr=-fpcvt < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -mattr=-fpcvt -ppc-gen-isel=false < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-NO-ISEL
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define float @test(i64 %x) nounwind readnone { define float @test(i64 %x) nounwind readnone {
entry: entry:
%conv = sitofp i64 %x to float %conv = sitofp i64 %x to float
ret float %conv ret float %conv
} }
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test/CodeGen/PowerPC/ia-neg-const.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 < %s \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define i64 @main() #0 { define i64 @main() #0 {
entry: entry:
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test/CodeGen/PowerPC/ifcvt.ll

; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs \
; RUN: | FileCheck %s
; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs \
; RUN: -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) { define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) {
entry: entry:
%sext82 = shl i32 %d, 16 %sext82 = shl i32 %d, 16
%conv29 = ashr exact i32 %sext82, 16 %conv29 = ashr exact i32 %sext82, 16
%cmp = icmp slt i32 %sext82, 0 %cmp = icmp slt i32 %sext82, 0
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test/CodeGen/PowerPC/inlineasm-i64-reg.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-bgq-linux -mcpu=a2 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: --mtriple=powerpc64-bgq-linux -mcpu=a2 < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
%struct.BG_CoordinateMapping_t = type { [4 x i8] } %struct.BG_CoordinateMapping_t = type { [4 x i8] }
; Function Attrs: alwaysinline inlinehint nounwind ; Function Attrs: alwaysinline inlinehint nounwind
define zeroext i32 @Kernel_RanksToCoords(i64 %mapsize, %struct.BG_CoordinateMapping_t* %map, i64* %numentries) #0 { define zeroext i32 @Kernel_RanksToCoords(i64 %mapsize, %struct.BG_CoordinateMapping_t* %map, i64* %numentries) #0 {
entry: entry:
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test/CodeGen/PowerPC/isel.ll

target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: -mcpu=a2 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
define i64 @test1(i64 %a, i64 %b, i64 %c, i64 %d) { define i64 @test1(i64 %a, i64 %b, i64 %c, i64 %d) {
entry: entry:
%p = icmp uge i64 %a, %b %p = icmp uge i64 %a, %b
%x = select i1 %p, i64 %c, i64 %d %x = select i1 %p, i64 %c, i64 %d
ret i64 %x ret i64 %x
; CHECK-LABEL: @test1 ; CHECK-LABEL: @test1
; CHECK-NO-ISEL-LABEL: @test1 ; CHECK-NO-ISEL-LABEL: @test1
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test/CodeGen/PowerPC/jaggedstructs.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 -O0 -fast-isel=false < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=ppc64 -O0 \
; RUN: -fast-isel=false < %s | FileCheck %s
; This tests receiving and re-passing parameters consisting of structures ; This tests receiving and re-passing parameters consisting of structures
; of size 3, 5, 6, and 7. They are to be found/placed right-adjusted in ; of size 3, 5, 6, and 7. They are to be found/placed right-adjusted in
; the parameter registers. ; the parameter registers.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
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test/CodeGen/PowerPC/lbz-from-ld-shift.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=ppc64 < %s \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
define signext i32 @test(i32* nocapture readonly %P) #0 { define signext i32 @test(i32* nocapture readonly %P) #0 {
entry: entry:
%0 = load i32, i32* %P, align 4 %0 = load i32, i32* %P, align 4
%shr = lshr i32 %0, 24 %shr = lshr i32 %0, 24
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test/CodeGen/PowerPC/ld-st-upd.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-strip-register-prefix < %s \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc-unknown-linux-gnu" target triple = "powerpc-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define i32* @test4(i32* readonly %X, i32* nocapture %dest) #0 { define i32* @test4(i32* readonly %X, i32* nocapture %dest) #0 {
%Y = getelementptr i32, i32* %X, i64 4 %Y = getelementptr i32, i32* %X, i64 4
%A = load i32, i32* %Y, align 4 %A = load i32, i32* %Y, align 4
store i32 %A, i32* %dest, align 4 store i32 %A, i32* %dest, align 4
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test/CodeGen/PowerPC/ldtoc-inv.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-strip-register-prefix < %s \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@phasor = external constant [4096 x i32] @phasor = external constant [4096 x i32]
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @test(i32* nocapture %out, i32 zeroext %step_size) #0 { define void @test(i32* nocapture %out, i32 zeroext %step_size) #0 {
entry: entry:
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test/CodeGen/PowerPC/licm-remat.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-strip-register-prefix < %s | FileCheck %s
; Test case is reduced from the snappy benchmark. ; Test case is reduced from the snappy benchmark.
; Verify MachineLICM will always hoist trivially rematerializable instructions even when register pressure is high. ; Verify MachineLICM will always hoist trivially rematerializable instructions even when register pressure is high.
%"class.snappy::SnappyDecompressor" = type <{ %"class.snappy::Source"*, i8*, i8*, i32, i8, [5 x i8], [6 x i8] }> %"class.snappy::SnappyDecompressor" = type <{ %"class.snappy::Source"*, i8*, i8*, i32, i8, [5 x i8], [6 x i8] }>
%"class.snappy::Source" = type { i32 (...)** } %"class.snappy::Source" = type { i32 (...)** }
%"struct.snappy::iovec" = type { i8*, i64 } %"struct.snappy::iovec" = type { i8*, i64 }
%"class.snappy::SnappyIOVecWriter" = type { %"struct.snappy::iovec"*, i64, i64, i64, i64, i64 } %"class.snappy::SnappyIOVecWriter" = type { %"struct.snappy::iovec"*, i64, i64, i64, i64, i64 }
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test/CodeGen/PowerPC/licm-tocReg.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-strip-register-prefix < %s | FileCheck %s
; The instructions ADDIStocHA/LDtocL are used to calculate the address of ; The instructions ADDIStocHA/LDtocL are used to calculate the address of
; globals. The ones that are in bb.3.if.end could not be hoisted by Machine ; globals. The ones that are in bb.3.if.end could not be hoisted by Machine
; LICM due to BCTRL_LDinto_toc in bb2.if.then. This call causes the compiler ; LICM due to BCTRL_LDinto_toc in bb2.if.then. This call causes the compiler
; to insert a save TOC to stack before the call and load into X2 to restore TOC ; to insert a save TOC to stack before the call and load into X2 to restore TOC
; after. By communicating to Machine LICM that X2 is guaranteed to have the ; after. By communicating to Machine LICM that X2 is guaranteed to have the
; same value before and after BCTRL_LDinto_toc, these instructions can be ; same value before and after BCTRL_LDinto_toc, these instructions can be
; hoisted out of bb.3.if.end to outside of the loop. ; hoisted out of bb.3.if.end to outside of the loop.
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test/CodeGen/PowerPC/load-two-flts.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
define void @_Z4testSt7complexIfE(float %v0, float %v1, i64* %ref.tmp, float* %_M_value.realp.i.i, float* %_M_value.imagp.i.i) { define void @_Z4testSt7complexIfE(float %v0, float %v1, i64* %ref.tmp, float* %_M_value.realp.i.i, float* %_M_value.imagp.i.i) {
entry: entry:
%v2 = load i64, i64* %ref.tmp, align 8 %v2 = load i64, i64* %ref.tmp, align 8
%v3 = lshr i64 %v2, 32 %v3 = lshr i64 %v2, 32
%v4 = trunc i64 %v3 to i32 %v4 = trunc i64 %v3 to i32
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test/CodeGen/PowerPC/load-v4i8-improved.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck \
; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s ; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck \
; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s ; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
define <16 x i8> @test(i32* %s, i32* %t) { define <16 x i8> @test(i32* %s, i32* %t) {
entry: entry:
%0 = bitcast i32* %s to <4 x i8>* %0 = bitcast i32* %s to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 4 %1 = load <4 x i8>, <4 x i8>* %0, align 4
%2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
ret <16 x i8> %2 ret <16 x i8> %2
; CHECK-LABEL: test ; CHECK-LABEL: test
; CHECK: lxsiwax 34, 0, 3 ; CHECK: lxsiwax 34, 0, 3
; CHECK: xxspltw 34, 34, 1 ; CHECK: xxspltw 34, 34, 1
} }

test/CodeGen/PowerPC/longcall.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @bar() local_unnamed_addr #0 { define void @bar() local_unnamed_addr #0 {
entry: entry:
tail call void @foo() #1 tail call void @foo() #1
ret void ret void
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test/CodeGen/PowerPC/loop-prep-all.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-bgq-linux < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BGQ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-bgq-linux < %s \
; RUN: -ppc-strip-register-prefix | FileCheck %s -check-prefix=CHECK \
; RUN: -check-prefix=CHECK-BGQ
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo(double* nocapture %x, double* nocapture readonly %y) #0 { define void @foo(double* nocapture %x, double* nocapture readonly %y) #0 {
entry: entry:
br label %for.body br label %for.body
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test/CodeGen/PowerPC/lsa.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=ppc64 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=ppc64 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define signext i32 @foo() #0 { define signext i32 @foo() #0 {
entry: entry:
%v = alloca [8200 x i32], align 4 %v = alloca [8200 x i32], align 4
%w = alloca [8200 x i32], align 4 %w = alloca [8200 x i32], align 4
%q = alloca [8200 x i32], align 4 %q = alloca [8200 x i32], align 4
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test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll

; RUN: llc -O3 -o - %s | FileCheck %s ; RUN: llc -O3 -o - %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
%class1 = type { %union1 } %class1 = type { %union1 }
%union1 = type { i64, [24 x i8] } %union1 = type { i64, [24 x i8] }
%class2 = type { %class3 } %class2 = type { %class3 }
%class3 = type { %class4 } %class3 = type { %class4 }
%class4 = type { %class5, i64, %union.anon } %class4 = type { %class5, i64, %union.anon }
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test/CodeGen/PowerPC/machine-combiner.ll

; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-PWR ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -O3 \
; RUN: llc -verify-machineinstrs -O3 -mcpu=a2q -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-QPX ; RUN: -mcpu=pwr7 -enable-unsafe-fp-math < %s \
; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-PWR
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -O3 -mcpu=a2q \
; RUN: -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK \
; RUN: -check-prefix=CHECK-QPX
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Verify that the first two adds are independent regardless of how the inputs are ; Verify that the first two adds are independent regardless of how the inputs are
; commuted. The destination registers are used as source registers for the third add. ; commuted. The destination registers are used as source registers for the third add.
define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) {
; CHECK-LABEL: reassociate_adds1: ; CHECK-LABEL: reassociate_adds1:
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test/CodeGen/PowerPC/mcm-1.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s ; RUN: -O0 -code-model=medium <%s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -O0 -code-model=large <%s | FileCheck %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading and storing an external variable. ; for loading and storing an external variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@ei = external global i32 @ei = external global i32
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test/CodeGen/PowerPC/mcm-10.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 -O1 \
; RUN: -code-model=medium <%s | FileCheck %s
; Test peephole optimization for medium code model (32-bit TOC offsets) ; Test peephole optimization for medium code model (32-bit TOC offsets)
; for loading and storing a static variable scoped to a function. ; for loading and storing a static variable scoped to a function.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@test_fn_static.si = internal global i32 0, align 4 @test_fn_static.si = internal global i32 0, align 4
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test/CodeGen/PowerPC/mcm-11.ll

; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium <%s \
; RUN: | FileCheck %s
; Test peephole optimization for medium code model (32-bit TOC offsets) ; Test peephole optimization for medium code model (32-bit TOC offsets)
; for loading and storing a file-scope static variable. ; for loading and storing a file-scope static variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@gi = global i32 5, align 4 @gi = global i32 5, align 4
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test/CodeGen/PowerPC/mcm-12.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -O1 -code-model=medium \
; RUN: -mattr=-vsx < %s | FileCheck %s ; RUN: -mattr=-vsx < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -O1 -code-model=medium \
; RUN: -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O1 -code-model=medium < %s | \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr9 \
; RUN: -O1 -code-model=medium < %s | \
; RUN: FileCheck -check-prefix=CHECK-P9 %s ; RUN: FileCheck -check-prefix=CHECK-P9 %s
; Test peephole optimization for medium code model (32-bit TOC offsets) ; Test peephole optimization for medium code model (32-bit TOC offsets)
; for loading a value from the constant pool (TOC-relative). ; for loading a value from the constant pool (TOC-relative).
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
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test/CodeGen/PowerPC/mcm-13.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s ; RUN: -O0 -code-model=medium <%s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -O0 -code-model=large <%s | FileCheck %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading and storing a weak variable ; for loading and storing a weak variable
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@wi = weak global i32 0, align 4 @wi = weak global i32 0, align 4
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test/CodeGen/PowerPC/mcm-2.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s ; RUN: -mcpu=pwr7 -O0 -code-model=medium <%s \
; RUN: | FileCheck -check-prefix=MEDIUM %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading and storing a static variable scoped to a function. ; for loading and storing a static variable scoped to a function.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@test_fn_static.si = internal global i32 0, align 4 @test_fn_static.si = internal global i32 0, align 4
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test/CodeGen/PowerPC/mcm-3.ll

; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s ; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s ; RUN: -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s \
; RUN: | FileCheck -check-prefix=MEDIUM %s
; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s \
; RUN: | FileCheck -check-prefix=LARGE %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading and storing a file-scope static variable. ; for loading and storing a file-scope static variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@gi = global i32 5, align 4 @gi = global i32 5, align 4
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test/CodeGen/PowerPC/mcm-4.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mcpu=pwr7 -O0 -code-model=medium \
; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s ; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mcpu=pwr7 -O0 -code-model=medium \
; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mcpu=pwr7 -O0 -code-model=large \
; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s ; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mcpu=pwr7 -O0 -code-model=large \
; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=medium \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mcpu=pwr9 -O0 -code-model=medium \
; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-P9 %s ; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-P9 %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=large \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-P9 %s ; RUN: -mcpu=pwr9 -O0 -code-model=large \
; RUN: -fast-isel=false -mattr=+vsx <%s \
; RUN: | FileCheck -check-prefix=LARGE-P9 %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading a value from the constant pool (TOC-relative). ; for loading a value from the constant pool (TOC-relative).
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define double @test_double_const() nounwind { define double @test_double_const() nounwind {
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test/CodeGen/PowerPC/mcm-5.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -code-model=medium <%s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -code-model=large <%s | FileCheck -check-prefix=LARGE %s ; RUN: -code-model=medium <%s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -code-model=large <%s | FileCheck -check-prefix=LARGE %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading the address of a jump table from the TOC. ; for loading the address of a jump table from the TOC.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define signext i32 @test_jump_table(i32 signext %i) nounwind { define signext i32 @test_jump_table(i32 signext %i) nounwind {
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test/CodeGen/PowerPC/mcm-6.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s ; RUN: -O0 -code-model=medium < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -O0 -code-model=large < %s | FileCheck %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading and storing a tentatively defined variable. ; for loading and storing a tentatively defined variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@ti = common global i32 0, align 4 @ti = common global i32 0, align 4
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test/CodeGen/PowerPC/mcm-7.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s ; RUN: -O0 -code-model=medium < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -O0 -code-model=large < %s | FileCheck %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading a function address. ; for loading a function address.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i8* @test_fnaddr() nounwind { define i8* @test_fnaddr() nounwind {
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test/CodeGen/PowerPC/mcm-8.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s ; RUN: -O0 -code-model=medium < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -O0 -code-model=large < %s | FileCheck %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading a variable with available-externally linkage. ; for loading a variable with available-externally linkage.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@x = available_externally constant [13 x i8] c"St9bad_alloc\00" @x = available_externally constant [13 x i8] c"St9bad_alloc\00"
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test/CodeGen/PowerPC/mcm-9.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s ; RUN: -O0 -code-model=medium <%s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -O0 -code-model=large <%s | FileCheck %s
; Test correct code generation for medium and large code model ; Test correct code generation for medium and large code model
; for loading and storing an aliased external variable. ; for loading and storing an aliased external variable.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@a = external global i32 @a = external global i32
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test/CodeGen/PowerPC/mcm-default.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 <%s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -O0 <%s | FileCheck %s
; Test that we generate code for the medium model as the default. ; Test that we generate code for the medium model as the default.
; Use an external variable reference as an example. ; Use an external variable reference as an example.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@ei = external global i32 @ei = external global i32
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test/CodeGen/PowerPC/memcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=CHECK ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: -mtriple=powerpc64le-unknown-gnu-linux < %s \
; RUN: | FileCheck %s -check-prefix=CHECK
define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
; CHECK-LABEL: memcmp8: ; CHECK-LABEL: memcmp8:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: ldbrx 3, 0, 3 ; CHECK-NEXT: ldbrx 3, 0, 3
; CHECK-NEXT: ldbrx 4, 0, 4 ; CHECK-NEXT: ldbrx 4, 0, 4
; CHECK-NEXT: li 5, 0 ; CHECK-NEXT: li 5, 0
; CHECK-NEXT: cmpld 3, 4 ; CHECK-NEXT: cmpld 3, 4
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test/CodeGen/PowerPC/memcpy-vec.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PWR7 ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 < %s \
; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PWR8 ; RUN: | FileCheck %s -check-prefix=PWR7
; RUN: llc -verify-machineinstrs -mcpu=a2q < %s | FileCheck %s -check-prefix=A2Q ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr8 < %s \
; RUN: | FileCheck %s -check-prefix=PWR8
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=a2q < %s \
; RUN: | FileCheck %s -check-prefix=A2Q
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo1(double* nocapture %x, double* nocapture readonly %y) #0 { define void @foo1(double* nocapture %x, double* nocapture readonly %y) #0 {
entry: entry:
%0 = bitcast double* %x to i8* %0 = bitcast double* %x to i8*
%1 = bitcast double* %y to i8* %1 = bitcast double* %y to i8*
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test/CodeGen/PowerPC/memcpy_dereferenceable.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr8 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; This code causes an assertion failure if dereferenceable flag is not properly set in the load generated for memcpy ; This code causes an assertion failure if dereferenceable flag is not properly set in the load generated for memcpy
; CHECK-LABEL: @func ; CHECK-LABEL: @func
; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK-NOT: lxvd2x ; CHECK-NOT: lxvd2x
; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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test/CodeGen/PowerPC/merge_stores_dereferenceable.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; This code causes an assertion failure if dereferenceable flag is not properly set when in merging consecutive stores ; This code causes an assertion failure if dereferenceable flag is not properly set when in merging consecutive stores
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK-NOT: lxvd2x ; CHECK-NOT: lxvd2x
; CHECK: stxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: stxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
define <2 x i64> @func(i64* %pdst) { define <2 x i64> @func(i64* %pdst) {
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test/CodeGen/PowerPC/mftb.ll

; Check handling of the mftb instruction. ; Check handling of the mftb instruction.
; For CPUs 601 and pwr3, the mftb instruction should be emitted. ; For CPUs 601 and pwr3, the mftb instruction should be emitted.
; On all other CPUs (including generic, ppc, ppc64), the mfspr instruction ; On all other CPUs (including generic, ppc, ppc64), the mfspr instruction
; should be used instead. There should no longer be a deprecated warning ; should be used instead. There should no longer be a deprecated warning
; message emittedfor this instruction for any CPU. ; message emittedfor this instruction for any CPU.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 \
; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR ; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s 2>&1 \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s 2>&1 \
; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR ; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s 2>&1 \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s 2>&1 \
; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR ; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s 2>&1 \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc-unknown-linux-gnu < %s 2>&1 \
; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR ; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s 2>&1 \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s 2>&1 \
; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR ; RUN: | FileCheck %s --check-prefix=CHECK-MFSPR
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=601 < %s 2>&1 \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc-unknown-linux-gnu -mcpu=601 < %s 2>&1 \
; RUN: | FileCheck %s --check-prefix=CHECK-MFTB ; RUN: | FileCheck %s --check-prefix=CHECK-MFTB
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr3 < %s 2>&1 \ ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr3 < %s 2>&1 \
; RUN: | FileCheck %s --check-prefix=CHECK-MFTB ; RUN: | FileCheck %s --check-prefix=CHECK-MFTB
; CHECK-MFSPR-NOT: warning: deprecated ; CHECK-MFSPR-NOT: warning: deprecated
; CHECK-MFTB-NOT: warning: deprecated ; CHECK-MFTB-NOT: warning: deprecated
define i32 @get_time() { define i32 @get_time() {
%time = call i32 asm "mftb $0, 268", "=r"() %time = call i32 asm "mftb $0, 268", "=r"()
ret i32 %time ret i32 %time
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test/CodeGen/PowerPC/mulli64.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i64 @foo(i64 %a) #0 { define i64 @foo(i64 %a) #0 {
entry: entry:
%mul = mul nsw i64 %a, 3 %mul = mul nsw i64 %a, 3
ret i64 %mul ret i64 %mul
} }
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
; CHECK: mulli 3, 3, 3 ; CHECK: mulli 3, 3, 3
; CHECK: blr ; CHECK: blr
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

test/CodeGen/PowerPC/multi-return.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -O0 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -O2 < %s | FileCheck %s
; Verify that returning multiple return values in registers works, ; Verify that returning multiple return values in registers works,
; both with fast-isel and regular isel. ; both with fast-isel and regular isel.
define { i32, i32, i32, i32 } @foo() nounwind { define { i32, i32, i32, i32 } @foo() nounwind {
%A1 = insertvalue { i32, i32, i32, i32 } undef, i32 1, 0 %A1 = insertvalue { i32, i32, i32, i32 } undef, i32 1, 0
%A2 = insertvalue { i32, i32, i32, i32 } %A1, i32 2, 1 %A2 = insertvalue { i32, i32, i32, i32 } %A1, i32 2, 1
%A3 = insertvalue { i32, i32, i32, i32 } %A2, i32 3, 2 %A3 = insertvalue { i32, i32, i32, i32 } %A2, i32 3, 2
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test/CodeGen/PowerPC/named-reg-alloc-r1-64.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
define i64 @get_reg() nounwind { define i64 @get_reg() nounwind {
entry: entry:
%reg = call i64 @llvm.read_register.i64(metadata !0) %reg = call i64 @llvm.read_register.i64(metadata !0)
ret i64 %reg ret i64 %reg
; CHECK-LABEL: @get_reg ; CHECK-LABEL: @get_reg
; CHECK: mr 3, 1 ; CHECK: mr 3, 1
; CHECK-DARWIN-LABEL: @get_reg ; CHECK-DARWIN-LABEL: @get_reg
; CHECK-DARWIN: mr r3, r1 ; CHECK-DARWIN: mr r3, r1
} }
declare i64 @llvm.read_register.i64(metadata) nounwind declare i64 @llvm.read_register.i64(metadata) nounwind
!0 = !{!"r1\00"} !0 = !{!"r1\00"}

test/CodeGen/PowerPC/named-reg-alloc-r1.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-apple-darwin \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN ; RUN: 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s ; RUN: -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s \
; RUN: --check-prefix=CHECK-DARWIN
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix < %s \
; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
define i32 @get_reg() nounwind { define i32 @get_reg() nounwind {
entry: entry:
%reg = call i32 @llvm.read_register.i32(metadata !0) %reg = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %reg ret i32 %reg
; CHECK-LABEL: @get_reg ; CHECK-LABEL: @get_reg
; CHECK: mr 3, 1 ; CHECK: mr 3, 1
; CHECK-DARWIN-LABEL: @get_reg ; CHECK-DARWIN-LABEL: @get_reg
; CHECK-DARWIN: mr r3, r1 ; CHECK-DARWIN: mr r3, r1
} }
declare i32 @llvm.read_register.i32(metadata) nounwind declare i32 @llvm.read_register.i32(metadata) nounwind
!0 = !{!"r1\00"} !0 = !{!"r1\00"}

test/CodeGen/PowerPC/named-reg-alloc-r13-64.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
define i64 @get_reg() nounwind { define i64 @get_reg() nounwind {
entry: entry:
%reg = call i64 @llvm.read_register.i64(metadata !0) %reg = call i64 @llvm.read_register.i64(metadata !0)
ret i64 %reg ret i64 %reg
; CHECK-LABEL: @get_reg ; CHECK-LABEL: @get_reg
; CHECK: mr 3, 13 ; CHECK: mr 3, 13
; CHECK-DARWIN-LABEL: @get_reg ; CHECK-DARWIN-LABEL: @get_reg
; CHECK-DARWIN: mr r3, r13 ; CHECK-DARWIN: mr r3, r13
} }
declare i64 @llvm.read_register.i64(metadata) nounwind declare i64 @llvm.read_register.i64(metadata) nounwind
!0 = !{!"r13\00"} !0 = !{!"r13\00"}

test/CodeGen/PowerPC/named-reg-alloc-r13.ll

; RUN: not llc < %s -mtriple=powerpc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN ; RUN: not llc < %s -mtriple=powerpc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s ; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
define i32 @get_reg() nounwind { define i32 @get_reg() nounwind {
entry: entry:
; FIXME: Include an allocatable-specific error message ; FIXME: Include an allocatable-specific error message
; CHECK-DARWIN: Invalid register name global variable ; CHECK-DARWIN: Invalid register name global variable
%reg = call i32 @llvm.read_register.i32(metadata !0) %reg = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %reg ret i32 %reg
; CHECK-LABEL: @get_reg ; CHECK-LABEL: @get_reg
; CHECK: mr 3, 13 ; CHECK: mr 3, 13
} }
declare i32 @llvm.read_register.i32(metadata) nounwind declare i32 @llvm.read_register.i32(metadata) nounwind
!0 = !{!"r13\00"} !0 = !{!"r13\00"}

test/CodeGen/PowerPC/named-reg-alloc-r2.ll

; RUN: not llc < %s -mtriple=powerpc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32 ; RUN: not llc < %s -mtriple=powerpc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32 ; RUN: -ppc-strip-register-prefix 2>&1 | FileCheck %s
; RUN: not llc < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s \
; RUN: --check-prefix=CHECK-NOTPPC32
define i32 @get_reg() nounwind { define i32 @get_reg() nounwind {
entry: entry:
; FIXME: Include an allocatable-specific error message ; FIXME: Include an allocatable-specific error message
; CHECK-NOTPPC32: Invalid register name global variable ; CHECK-NOTPPC32: Invalid register name global variable
%reg = call i32 @llvm.read_register.i32(metadata !0) %reg = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %reg ret i32 %reg
; CHECK-LABEL: @get_reg ; CHECK-LABEL: @get_reg
; CHECK: mr 3, 2 ; CHECK: mr 3, 2
} }
declare i32 @llvm.read_register.i32(metadata) nounwind declare i32 @llvm.read_register.i32(metadata) nounwind
!0 = !{!"r2\00"} !0 = !{!"r2\00"}

test/CodeGen/PowerPC/negate-i1.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
; PR30661 - https://llvm.org/bugs/show_bug.cgi?id=30661 ; PR30661 - https://llvm.org/bugs/show_bug.cgi?id=30661
define i32 @select_i32_neg1_or_0(i1 %a) { define i32 @select_i32_neg1_or_0(i1 %a) {
; CHECK-LABEL: select_i32_neg1_or_0: ; CHECK-LABEL: select_i32_neg1_or_0:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: clrldi 3, 3, 63 ; CHECK-NEXT: clrldi 3, 3, 63
; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: neg 3, 3
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test/CodeGen/PowerPC/negctr.ll

; RUN: llc < %s -mcpu=a2 | FileCheck %s ; RUN: llc < %s -mcpu=a2 -ppc-strip-register-prefix | FileCheck %s
; RUN: llc < %s -mcpu=a2 -disable-lsr | FileCheck -check-prefix=NOLSR %s ; RUN: llc < %s -mcpu=a2 -ppc-strip-register-prefix \
; RUN: -disable-lsr | FileCheck -check-prefix=NOLSR %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @main() #0 { define void @main() #0 {
entry: entry:
br i1 undef, label %for.end, label %for.body br i1 undef, label %for.end, label %for.body
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
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test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll

; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=a2 < %s \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
define double @test1(i64* nocapture readonly %x) #0 { define double @test1(i64* nocapture readonly %x) #0 {
entry: entry:
%0 = load i64, i64* %x, align 8 %0 = load i64, i64* %x, align 8
%conv = sitofp i64 %0 to double %conv = sitofp i64 %0 to double
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test/CodeGen/PowerPC/opt-li-add-to-addi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
define i64 @testOptimizeLiAddToAddi(i64 %a) { define i64 @testOptimizeLiAddToAddi(i64 %a) {
; CHECK-LABEL: testOptimizeLiAddToAddi: ; CHECK-LABEL: testOptimizeLiAddToAddi:
; CHECK: addi 3, 30, 2444 ; CHECK: addi 3, 30, 2444
; CHECK: bl callv ; CHECK: bl callv
; CHECK: addi 3, 30, 234 ; CHECK: addi 3, 30, 234
; CHECK: bl call ; CHECK: bl call
; CHECK: blr ; CHECK: blr
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test/CodeGen/PowerPC/optnone-crbits-i1-ret.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
declare zeroext i1 @ri1() declare zeroext i1 @ri1()
declare void @se1() declare void @se1()
declare void @se2() declare void @se2()
define void @test() #0 { define void @test() #0 {
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test/CodeGen/PowerPC/ori_imm32.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
define i64 @ori_test_a(i64 %a) { define i64 @ori_test_a(i64 %a) {
entry: entry:
; CHECK-LABEL: @ori_test_a ; CHECK-LABEL: @ori_test_a
; CHECK-DAG: ori 3, 3, 65535 ; CHECK-DAG: ori 3, 3, 65535
; CHECK-DAG: oris 3, 3, 65535 ; CHECK-DAG: oris 3, 3, 65535
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%or = or i64 %a, 4294967295 %or = or i64 %a, 4294967295
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test/CodeGen/PowerPC/p8-isel-sched.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo(i32* nocapture %r1, i32* nocapture %r2, i32* nocapture %r3, i32* nocapture %r4, i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) #0 { define void @foo(i32* nocapture %r1, i32* nocapture %r2, i32* nocapture %r3, i32* nocapture %r4, i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) #0 {
entry: entry:
%tobool = icmp ne i32 %a, 0 %tobool = icmp ne i32 %a, 0
%cond = select i1 %tobool, i32 %b, i32 %c %cond = select i1 %tobool, i32 %b, i32 %c
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test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 \
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE ; RUN: -ppc-strip-register-prefix | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -ppc-strip-register-prefix | FileCheck %s -check-prefix=CHECK-LE
; The build[csilf] functions simply test the scalar_to_vector handling with ; The build[csilf] functions simply test the scalar_to_vector handling with
; direct moves. This corresponds to the "insertelement" instruction. Subsequent ; direct moves. This corresponds to the "insertelement" instruction. Subsequent
; to this, there will be a splat corresponding to the shufflevector. ; to this, there will be a splat corresponding to the shufflevector.
@d = common global double 0.000000e+00, align 8 @d = common global double 0.000000e+00, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
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test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define <2 x i32> @test1(<4 x i32> %wide.vec) #0 { define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {
entry: entry:
%strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2> %strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
ret <2 x i32> %strided.vec ret <2 x i32> %strided.vec
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test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll

; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -mcpu=pwr9 -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define zeroext i32 @testCTZ32(i32 signext %a) { define zeroext i32 @testCTZ32(i32 signext %a) {
entry: entry:
%0 = tail call i32 @llvm.cttz.i32(i32 %a, i1 false) %0 = tail call i32 @llvm.cttz.i32(i32 %a, i1 false)
ret i32 %0 ret i32 %0
; CHECK-LABEL: testCTZ32 ; CHECK-LABEL: testCTZ32
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test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll

; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs -ppc-strip-register-prefix < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: -verify-machineinstrs -ppc-strip-register-prefix < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-BE
define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
entry: entry:
; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
; CHECK: xxswapd 0, 35 ; CHECK: xxswapd 0, 35
; CHECK: xxinsertw 34, 0, 12 ; CHECK: xxinsertw 34, 0, 12
; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
; CHECK-BE: xxsldwi 0, 35, 35, 3 ; CHECK-BE: xxsldwi 0, 35, 35, 3
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test/CodeGen/PowerPC/peephole-align.ll

; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s ; RUN: llc -relocation-model=static -ppc-strip-register-prefix \
; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 -O1 -code-model=medium <%s | FileCheck %s ; RUN: -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium <%s \
; RUN: | FileCheck %s
; RUN: llc -relocation-model=static -ppc-strip-register-prefix \
; RUN: -verify-machineinstrs -mcpu=pwr8 -O1 -code-model=medium <%s \
; RUN: | FileCheck %s
; Test peephole optimization for medium code model (32-bit TOC offsets) ; Test peephole optimization for medium code model (32-bit TOC offsets)
; for loading and storing small offsets within aligned values. ; for loading and storing small offsets within aligned values.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.b4 = type<{ i8, i8, i8, i8 }> %struct.b4 = type<{ i8, i8, i8, i8 }>
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test/CodeGen/PowerPC/pip-inner.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo(double* %x, double* nocapture readonly %y) #0 { define void @foo(double* %x, double* nocapture readonly %y) #0 {
entry: entry:
br label %for.cond1.preheader br label %for.cond1.preheader
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test/CodeGen/PowerPC/power9-moves-and-splats.ll

; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mcpu=pwr9 -ppc-strip-register-prefix \
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-BE ; RUN: --check-prefix=CHECK-BE
@Globi = external global i32, align 4 @Globi = external global i32, align 4
@Globf = external global float, align 4 @Globf = external global float, align 4
define <2 x i64> @test1(i64 %a, i64 %b) { define <2 x i64> @test1(i64 %a, i64 %b) {
entry: entry:
; The FIXME below is due to the lowering for BUILD_VECTOR needing a re-vamp ; The FIXME below is due to the lowering for BUILD_VECTOR needing a re-vamp
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test/CodeGen/PowerPC/ppc-redzone-alignment-bug.ll

; Note the formula for negative number alignment calculation should be y = x & ~(n-1) rather than y = (x + (n-1)) & ~(n-1). ; Note the formula for negative number alignment calculation should be y = x & ~(n-1) rather than y = (x + (n-1)) & ~(n-1).
; after patch https://reviews.llvm.org/D34337, we could save 16 bytes in the best case. ; after patch https://reviews.llvm.org/D34337, we could save 16 bytes in the best case.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-BE
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-LE
define signext i32 @bar(i32 signext %ii) { define signext i32 @bar(i32 signext %ii) {
entry: entry:
%0 = tail call i32 asm sideeffect "add $0, $1, $2\0A", "=r,r,r,~{f14},~{r15},~{v20}"(i32 %ii, i32 10) %0 = tail call i32 asm sideeffect "add $0, $1, $2\0A", "=r,r,r,~{f14},~{r15},~{v20}"(i32 %ii, i32 10)
ret i32 %0 ret i32 %0
; Before the fix by patch D34337: ; Before the fix by patch D34337:
; stdu 1, -544(1) ; stdu 1, -544(1)
; std 15, 264(1) ; std 15, 264(1)
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test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE ; RUN: -ppc-strip-register-prefix -mcpu=pwr8 %s -o - \
; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-strip-register-prefix %s -o - -enable-shrink-wrap=false \
; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
; ;
; Note: Lots of tests use inline asm instead of regular calls. ; Note: Lots of tests use inline asm instead of regular calls.
; This allows to have a better control on what the allocation will do. ; This allows to have a better control on what the allocation will do.
; Otherwise, we may have spill right in the entry block, defeating ; Otherwise, we may have spill right in the entry block, defeating
; shrink-wrapping. Moreover, some of the inline asm statement (nop) ; shrink-wrapping. Moreover, some of the inline asm statement (nop)
; are here to ensure that the related paths do not end up as critical ; are here to ensure that the related paths do not end up as critical
; edges. ; edges.
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test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll

; RUN: llc -verify-machineinstrs -O2 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O2 -mtriple=powerpc-unknown-linux-gnu \
; RUN: -ppc-strip-register-prefix < %s | FileCheck %s
@x = global ppc_fp128 0xM405EDA5E353F7CEE0000000000000000, align 16 @x = global ppc_fp128 0xM405EDA5E353F7CEE0000000000000000, align 16
@.str = private unnamed_addr constant [5 x i8] c"%Lf\0A\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"%Lf\0A\00", align 1
define void @foo() #0 { define void @foo() #0 {
entry: entry:
%0 = load ppc_fp128, ppc_fp128* @x, align 16 %0 = load ppc_fp128, ppc_fp128* @x, align 16
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test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll

; RUN: llc -verify-machineinstrs -O2 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O2 -mtriple=powerpc-unknown-linux-gnu \
; RUN: -ppc-strip-register-prefix < %s | FileCheck %s
target datalayout = "E-m:e-p:32:32-i64:64-n32" target datalayout = "E-m:e-p:32:32-i64:64-n32"
target triple = "powerpc-buildroot-linux-gnu" target triple = "powerpc-buildroot-linux-gnu"
@.str = private unnamed_addr constant [5 x i8] c"%Lf\0A\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"%Lf\0A\00", align 1
define i32 @main() #0 { define i32 @main() #0 {
entry: entry:
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test/CodeGen/PowerPC/ppc32-i1-vaarg.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=ppc32 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mcpu=ppc32 -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs < %s -mcpu=ppc32 -mtriple=powerpc-darwin9 | FileCheck %s -check-prefix=CHECK-D ; RUN: | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mcpu=ppc32 -mtriple=powerpc-darwin9 \
; RUN: | FileCheck %s -check-prefix=CHECK-D
target triple = "powerpc-unknown-linux-gnu" target triple = "powerpc-unknown-linux-gnu"
declare void @printf(i8*, ...) declare void @printf(i8*, ...)
define void @main() { define void @main() {
call void (i8*, ...) @printf(i8* undef, i1 false) call void (i8*, ...) @printf(i8* undef, i1 false)
ret void ret void
} }
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test/CodeGen/PowerPC/ppc32-nest.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix < %s | FileCheck %s
target datalayout = "E-m:e-p:32:32-i64:64-n32" target datalayout = "E-m:e-p:32:32-i64:64-n32"
target triple = "powerpc-unknown-linux-gnu" target triple = "powerpc-unknown-linux-gnu"
; Tests that the 'nest' parameter attribute causes the relevant parameter to be ; Tests that the 'nest' parameter attribute causes the relevant parameter to be
; passed in the right register (r11 for PPC). ; passed in the right register (r11 for PPC).
define i8* @nest_receiver(i8* nest %arg) nounwind { define i8* @nest_receiver(i8* nest %arg) nounwind {
; CHECK-LABEL: nest_receiver: ; CHECK-LABEL: nest_receiver:
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test/CodeGen/PowerPC/ppc32-pic-large.ll

; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=LARGE-BSS %s ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -ppc-strip-register-prefix \
; RUN: -relocation-model=pic | FileCheck -check-prefix=LARGE-BSS %s
@bar = common global i32 0, align 4 @bar = common global i32 0, align 4
declare i32 @call_foo(i32, ...) declare i32 @call_foo(i32, ...)
define i32 @foo() { define i32 @foo() {
entry: entry:
%0 = load i32, i32* @bar, align 4 %0 = load i32, i32* @bar, align 4
%call = call i32 (i32, ...) @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64) %call = call i32 (i32, ...) @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64)
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test/CodeGen/PowerPC/ppc32-pic.ll

; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=SMALL-BSS %s ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -ppc-strip-register-prefix \
; RUN: -relocation-model=pic | FileCheck -check-prefix=SMALL-BSS %s
@bar = common global i32 0, align 4 @bar = common global i32 0, align 4
declare i32 @call_foo(i32, ...) declare i32 @call_foo(i32, ...)
define i32 @foo() { define i32 @foo() {
entry: entry:
%0 = load i32, i32* @bar, align 4 %0 = load i32, i32* @bar, align 4
%call = call i32 (i32, ...) @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64) %call = call i32 (i32, ...) @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64)
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test/CodeGen/PowerPC/ppc32-skip-regs.ll

; RUN: llc -O2 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -O2 -mtriple=powerpc-unknown-linux-gnu \
; RUN: -ppc-strip-register-prefix < %s | FileCheck %s
target datalayout = "E-m:e-p:32:32-i64:64-n32" target datalayout = "E-m:e-p:32:32-i64:64-n32"
target triple = "powerpc-buildroot-linux-gnu" target triple = "powerpc-buildroot-linux-gnu"
@x = global ppc_fp128 0xM3FF00000000000000000000000000000, align 16 @x = global ppc_fp128 0xM3FF00000000000000000000000000000, align 16
@.str = private unnamed_addr constant [9 x i8] c"%Lf %Lf\0A\00", align 1 @.str = private unnamed_addr constant [9 x i8] c"%Lf %Lf\0A\00", align 1
define void @foo() #0 { define void @foo() #0 {
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test/CodeGen/PowerPC/ppc32-vacopy.ll

; RUN: llc -verify-machineinstrs -mtriple="powerpc-unknown-linux-gnu" -mcpu=ppc64 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple="powerpc-unknown-linux-gnu" -mcpu=ppc64 < %s | FileCheck %s
; PR15286 ; PR15286
%va_list = type {i8, i8, i16, i8*, i8*} %va_list = type {i8, i8, i16, i8*, i8*}
declare void @llvm.va_copy(i8*, i8*) declare void @llvm.va_copy(i8*, i8*)
define void @test_vacopy() nounwind { define void @test_vacopy() nounwind {
entry: entry:
%0 = alloca %va_list %0 = alloca %va_list
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test/CodeGen/PowerPC/ppc64-P9-mod.ll

; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 \
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs -ppc-strip-register-prefix | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not mod[us][wd] ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 \
; RUN: -verify-machineinstrs -ppc-strip-register-prefix | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -ppc-strip-register-prefix \
; RUN: | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not mod[us][wd]
@mod_resultsw = common local_unnamed_addr global i32 0, align 4 @mod_resultsw = common local_unnamed_addr global i32 0, align 4
@mod_resultud = common local_unnamed_addr global i64 0, align 8 @mod_resultud = common local_unnamed_addr global i64 0, align 8
@div_resultsw = common local_unnamed_addr global i32 0, align 4 @div_resultsw = common local_unnamed_addr global i32 0, align 4
@mod_resultuw = common local_unnamed_addr global i32 0, align 4 @mod_resultuw = common local_unnamed_addr global i32 0, align 4
@div_resultuw = common local_unnamed_addr global i32 0, align 4 @div_resultuw = common local_unnamed_addr global i32 0, align 4
@div_resultsd = common local_unnamed_addr global i64 0, align 8 @div_resultsd = common local_unnamed_addr global i64 0, align 8
@mod_resultsd = common local_unnamed_addr global i64 0, align 8 @mod_resultsd = common local_unnamed_addr global i64 0, align 8
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test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 \
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs -ppc-strip-register-prefix | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not vabsdu ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 \
; RUN: -verify-machineinstrs -ppc-strip-register-prefix | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not vabsdu
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define <4 x i32> @simple_absv_32(<4 x i32> %a) local_unnamed_addr { define <4 x i32> @simple_absv_32(<4 x i32> %a) local_unnamed_addr {
entry: entry:
%sub.i = sub <4 x i32> zeroinitializer, %a %sub.i = sub <4 x i32> zeroinitializer, %a
%0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i) %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i)
ret <4 x i32> %0 ret <4 x i32> %0
; CHECK-LABEL: simple_absv_32 ; CHECK-LABEL: simple_absv_32
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test/CodeGen/PowerPC/ppc64-abi-extend.ll

; Verify that i32 argument/return values are extended to i64 ; Verify that i32 argument/return values are extended to i64
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@si = common global i32 0, align 4 @si = common global i32 0, align 4
@ui = common global i32 0, align 4 @ui = common global i32 0, align 4
declare void @arg_si(i32 signext) declare void @arg_si(i32 signext)
declare void @arg_ui(i32 zeroext) declare void @arg_ui(i32 zeroext)
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test/CodeGen/PowerPC/ppc64-align-long-double.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=-vsx < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=-vsx \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -ppc-strip-register-prefix < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -fast-isel=false -mattr=+vsx \
; RUN: -ppc-strip-register-prefix < %s | FileCheck -check-prefix=CHECK-VSX %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 -fast-isel=false -mattr=+vsx \
; RUN: -ppc-strip-register-prefix < %s | FileCheck -check-prefix=CHECK-P9 %s
; Verify internal alignment of long double in a struct. The double ; Verify internal alignment of long double in a struct. The double
; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
; the long double. Check that these are stored to proper locations ; the long double. Check that these are stored to proper locations
; in the parameter save area and loaded from there for return in FPR1/2. ; in the parameter save area and loaded from there for return in FPR1/2.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
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test/CodeGen/PowerPC/ppc64-altivec-abi.ll

; RUN: llc -verify-machineinstrs < %s -mattr=+altivec | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mattr=+altivec | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Verify that in the 64-bit Linux ABI, vector arguments take up space ; Verify that in the 64-bit Linux ABI, vector arguments take up space
; in the parameter save area. ; in the parameter save area.
define i64 @callee(i64 %a, <4 x i32> %b, i64 %c, <4 x i32> %d, i64 %e) { define i64 @callee(i64 %a, <4 x i32> %b, i64 %c, <4 x i32> %d, i64 %e) {
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test/CodeGen/PowerPC/ppc64-byval-align.ll

; RUN: llc -verify-machineinstrs -O1 < %s -mcpu=pwr7 | FileCheck %s ; RUN: llc -verify-machineinstrs -O1 < %s -ppc-strip-register-prefix \
; RUN: -mcpu=pwr7 | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.test = type { i64, [8 x i8] } %struct.test = type { i64, [8 x i8] }
%struct.pad = type { [8 x i64] } %struct.pad = type { [8 x i64] }
@gt = common global %struct.test zeroinitializer, align 16 @gt = common global %struct.test zeroinitializer, align 16
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test/CodeGen/PowerPC/ppc64-calls.ll

; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mcpu=pwr7 | FileCheck %s ; RUN: llc -relocation-model=static -verify-machineinstrs < %s \
; RUN: llc -relocation-model=static -verify-machineinstrs < %s -code-model=small -mcpu=pwr7 | FileCheck %s -check-prefix=SCM ; RUN: -ppc-strip-register-prefix -mcpu=pwr7 | FileCheck %s
; RUN: llc -relocation-model=static -verify-machineinstrs < %s \
; RUN: -ppc-strip-register-prefix -code-model=small -mcpu=pwr7 \
; RUN: | FileCheck %s -check-prefix=SCM
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @foo() nounwind noinline { define void @foo() nounwind noinline {
ret void ret void
} }
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test/CodeGen/PowerPC/ppc64-cyclecounter.ll

target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
define i64 @test1() nounwind { define i64 @test1() nounwind {
entry: entry:
%r = call i64 @llvm.readcyclecounter() %r = call i64 @llvm.readcyclecounter()
ret i64 %r ret i64 %r
} }
; CHECK: @test1 ; CHECK: @test1
; CHECK: mfspr 3, 268 ; CHECK: mfspr 3, 268
declare i64 @llvm.readcyclecounter() declare i64 @llvm.readcyclecounter()

test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-vsx -fast-isel -fast-isel-abort=1 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -mattr=-vsx -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define fastcc i64 @g1(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { define fastcc i64 @g1(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 {
ret i64 %g1 ret i64 %g1
; CHECK-LABEL: @g1 ; CHECK-LABEL: @g1
; CHECK-NOT: mr 3, ; CHECK-NOT: mr 3,
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test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll

; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s -check-prefix=INVFUNCDESC ; RUN: llc -verify-machineinstrs -mcpu=a2 < %s -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs -mcpu=a2 -mattr=-invariant-function-descriptors < %s | FileCheck %s -check-prefix=NONINVFUNCDESC ; RUN: | FileCheck %s -check-prefix=INVFUNCDESC
; RUN: llc -verify-machineinstrs -mcpu=a2 \
; RUN: -mattr=-invariant-function-descriptors < %s \
; RUN: -ppc-strip-register-prefix | FileCheck %s -check-prefix=NONINVFUNCDESC
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @bar(void (...)* nocapture %x) #0 { define void @bar(void (...)* nocapture %x) #0 {
entry: entry:
%callee.knr.cast = bitcast void (...)* %x to void ()* %callee.knr.cast = bitcast void (...)* %x to void ()*
br label %for.body br label %for.body
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test/CodeGen/PowerPC/ppc64-gep-opt.ll

; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -O3 \
; RUN: llc -verify-machineinstrs -O3 -print-after=codegenprepare -mcpu=ppc64 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s ; RUN: -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -O3 -print-after=codegenprepare -mcpu=pwr7 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -O3 -print-after=codegenprepare -mcpu=ppc64 \
; RUN: < %s >%t 2>&1 && FileCheck \
; RUN: --check-prefix=CHECK-NoAA <%t %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -O3 -print-after=codegenprepare -mcpu=pwr7 \
; RUN: < %s >%t 2>&1 && FileCheck \
; RUN: --check-prefix=CHECK-UseAA <%t %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Following test cases test enabling SeparateConstOffsetFromGEP pass in the PPC ; Following test cases test enabling SeparateConstOffsetFromGEP pass in the PPC
; backend. If useAA() returns true, it will lower a GEP with multiple indices ; backend. If useAA() returns true, it will lower a GEP with multiple indices
; into GEPs with a single index, otherwise it will lower it into a ; into GEPs with a single index, otherwise it will lower it into a
; "ptrtoint+arithmetics+inttoptr" form. ; "ptrtoint+arithmetics+inttoptr" form.
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test/CodeGen/PowerPC/ppc64-i128-abi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \ ; RUN: -mcpu=pwr8 < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s -check-prefix=CHECK-LE \
; RUN: --implicit-check-not xxswapd ; RUN: --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: -mcpu=pwr8 < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s -check-prefix=CHECK-BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX ; RUN: -mcpu=pwr8 -mattr=-vsx < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s -check-prefix=CHECK-NOVSX
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s -check-prefix=CHECK-NOVSX \
; RUN: --implicit-check-not xxswapd ; RUN: --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX ; RUN: -mcpu=pwr8 -mattr=-vsx < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s -check-prefix=CHECK-BE-NOVSX
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s -ppc-strip-register-prefix | \
; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd ; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd ; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ ; RUN: -mcpu=pwr9 -mattr=-vsx < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s -check-prefix=CHECK-NOVSX \
; RUN: --implicit-check-not xxswapd ; RUN: --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \ ; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s \
; RUN: -ppc-strip-register-prefix | \
; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd ; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd
@x = common global <1 x i128> zeroinitializer, align 16 @x = common global <1 x i128> zeroinitializer, align 16
@y = common global <1 x i128> zeroinitializer, align 16 @y = common global <1 x i128> zeroinitializer, align 16
@a = common global i128 zeroinitializer, align 16 @a = common global i128 zeroinitializer, align 16
@b = common global i128 zeroinitializer, align 16 @b = common global i128 zeroinitializer, align 16
; VSX: ; VSX:
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test/CodeGen/PowerPC/ppc64-nest.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Tests that the 'nest' parameter attribute causes the relevant parameter to be ; Tests that the 'nest' parameter attribute causes the relevant parameter to be
; passed in the right register (r11 for PPC). ; passed in the right register (r11 for PPC).
define i8* @nest_receiver(i8* nest %arg) nounwind { define i8* @nest_receiver(i8* nest %arg) nounwind {
; CHECK-LABEL: nest_receiver: ; CHECK-LABEL: nest_receiver:
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test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll

; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 < %s \
; RUN: -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.cd = type { i64, i64, i64 } %struct.cd = type { i64, i64, i64 }
@something = global [33 x i8] c"this is not really code, but...\0A\00", align 1 @something = global [33 x i8] c"this is not really code, but...\0A\00", align 1
@tls_something = thread_local global %struct.cd zeroinitializer, align 8 @tls_something = thread_local global %struct.cd zeroinitializer, align 8
@extern_something = external global %struct.cd @extern_something = external global %struct.cd
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test/CodeGen/PowerPC/ppc64-patchpoint.ll

; RUN: llc < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE ; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: llc -fast-isel -fast-isel-abort=1 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE ; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE ; RUN: llc -fast-isel -fast-isel-abort=1 < %s -ppc-strip-register-prefix \
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -fast-isel -fast-isel-abort=1 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE ; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
; RUN: llc -ppc-strip-register-prefix -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
; RUN: llc -ppc-strip-register-prefix -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -fast-isel -fast-isel-abort=1 < %s | FileCheck %s \
; RUN: -check-prefix=CHECK -check-prefix=CHECK-LE
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Trivial patchpoint codegen ; Trivial patchpoint codegen
; ;
define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: trivial_patchpoint_codegen: ; CHECK-LABEL: trivial_patchpoint_codegen:
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test/CodeGen/PowerPC/ppc64-pre-inc-no-extra-phi.ll

; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 \
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
@perm = common local_unnamed_addr global [100 x i64] zeroinitializer, align 8 @perm = common local_unnamed_addr global [100 x i64] zeroinitializer, align 8
define void @sort_basket() local_unnamed_addr { define void @sort_basket() local_unnamed_addr {
entry: entry:
br label %while.cond br label %while.cond
while.cond: while.cond:
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test/CodeGen/PowerPC/ppc64-r2-alloc.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define signext i32 @foo(i32 signext %a, i32 signext %d) #0 { define signext i32 @foo(i32 signext %a, i32 signext %d) #0 {
entry: entry:
%div = sdiv i32 %a, %d %div = sdiv i32 %a, %d
%div1 = sdiv i32 %div, %d %div1 = sdiv i32 %div, %d
%div2 = sdiv i32 %div1, %d %div2 = sdiv i32 %div1, %d
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test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll

; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY ; RUN: llc -relocation-model=static -verify-machineinstrs \
; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SHRK ; RUN: -ppc-strip-register-prefix < %s \
; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY ; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SHRK ; RUN: -disable-ppc-sco=false --enable-shrink-wrap=false \
; RUN: | FileCheck %s -check-prefix=CHECK-SCO-ONLY
; RUN: llc -relocation-model=static -verify-machineinstrs \
; RUN: -ppc-strip-register-prefix < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -disable-ppc-sco=false --enable-shrink-wrap=true \
; RUN: | FileCheck %s -check-prefix=CHECK-SCO-SHRK
; RUN: llc -relocation-model=static -verify-machineinstrs \
; RUN: -ppc-strip-register-prefix < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -disable-ppc-sco=false --enable-shrink-wrap=false \
; RUN: | FileCheck %s -check-prefix=CHECK-SCO-ONLY
; RUN: llc -relocation-model=static -verify-machineinstrs \
; RUN: -ppc-strip-register-prefix < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -disable-ppc-sco=false --enable-shrink-wrap=true \
; RUN: | FileCheck %s -check-prefix=CHECK-SCO-SHRK
%"class.clang::NamedDecl" = type { i32 } %"class.clang::NamedDecl" = type { i32 }
declare void @__assert_fail(); declare void @__assert_fail();
define i8 @_ZNK5clang9NamedDecl23getLinkageAndVisibilityEv( define i8 @_ZNK5clang9NamedDecl23getLinkageAndVisibilityEv(
%"class.clang::NamedDecl"* %this) { %"class.clang::NamedDecl"* %this) {
entry: entry:
%tobool = icmp eq %"class.clang::NamedDecl"* %this, null %tobool = icmp eq %"class.clang::NamedDecl"* %this, null
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test/CodeGen/PowerPC/ppc64-sibcall.ll

; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-SCO ; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false \
; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO-HASQPX ; RUN: -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO-HASQPX ; RUN: -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s \
; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -code-model=small | FileCheck %s -check-prefix=SCM ; RUN: -check-prefix=CHECK-SCO
; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false \
; RUN: -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 \
; RUN: | FileCheck %s -check-prefix=CHECK-SCO-HASQPX
; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false \
; RUN: -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: | FileCheck %s -check-prefix=CHECK-SCO-HASQPX
; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false \
; RUN: -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -code-model=small | FileCheck %s -check-prefix=SCM
; No combination of "powerpc64le-unknown-linux-gnu" + "CHECK-SCO", because ; No combination of "powerpc64le-unknown-linux-gnu" + "CHECK-SCO", because
; only Power8 (and later) fully support LE. ; only Power8 (and later) fully support LE.
%S_56 = type { [13 x i32], i32 } %S_56 = type { [13 x i32], i32 }
%S_64 = type { [15 x i32], i32 } %S_64 = type { [15 x i32], i32 }
%S_32 = type { [7 x i32], i32 } %S_32 = type { [7 x i32], i32 }
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test/CodeGen/PowerPC/ppc64-smallarg.ll

; Verify that small structures and float arguments are passed in the ; Verify that small structures and float arguments are passed in the
; least significant part of a stack slot doubleword. ; least significant part of a stack slot doubleword.
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.large_arg = type { [8 x i64] } %struct.large_arg = type { [8 x i64] }
%struct.small_arg = type { i16, i8 } %struct.small_arg = type { i16, i8 }
@gl = common global %struct.large_arg zeroinitializer, align 8 @gl = common global %struct.large_arg zeroinitializer, align 8
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test/CodeGen/PowerPC/ppc64-stackmap-nops.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-gnu-linux | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-gnu-linux | FileCheck %s
define void @test_shadow_optimization() { define void @test_shadow_optimization() {
entry: entry:
; Expect 12 bytes worth of nops here rather than 32: With the shadow optimization ; Expect 12 bytes worth of nops here rather than 32: With the shadow optimization
; in place, 20 bytes will be consumed by the frame teardown and return instr. ; in place, 20 bytes will be consumed by the frame teardown and return instr.
; CHECK-LABEL: test_shadow_optimization: ; CHECK-LABEL: test_shadow_optimization:
; CHECK: nop ; CHECK: nop
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test/CodeGen/PowerPC/ppc64-toc.ll

; RUN: llc -verify-machineinstrs -code-model=small < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -code-model=small < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@double_array = global [32 x double] zeroinitializer, align 8 @double_array = global [32 x double] zeroinitializer, align 8
@number64 = global i64 10, align 8 @number64 = global i64 10, align 8
@internal_static_var.x = internal unnamed_addr global i64 0, align 8 @internal_static_var.x = internal unnamed_addr global i64 0, align 8
define i64 @access_int64(i64 %a) nounwind readonly { define i64 @access_int64(i64 %a) nounwind readonly {
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test/CodeGen/PowerPC/ppc64-vaarg-int.ll

target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
define i32 @intvaarg(i32 %a, ...) nounwind { define i32 @intvaarg(i32 %a, ...) nounwind {
entry: entry:
%va = alloca i8*, align 8 %va = alloca i8*, align 8
%va1 = bitcast i8** %va to i8* %va1 = bitcast i8** %va to i8*
call void @llvm.va_start(i8* %va1) call void @llvm.va_start(i8* %va1)
%0 = va_arg i8** %va, i32 %0 = va_arg i8** %va, i32
%sub = sub nsw i32 %a, %0 %sub = sub nsw i32 %a, %0
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test/CodeGen/PowerPC/ppc64-zext.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux" target triple = "powerpc64-unknown-linux"
define i64 @fun(i32 %arg32) nounwind { define i64 @fun(i32 %arg32) nounwind {
entry: entry:
; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 ; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
%o = zext i32 %arg32 to i64 %o = zext i32 %arg32 to i64
ret i64 %o ret i64 %o
} }

test/CodeGen/PowerPC/ppc64le-aggregates.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=pwr8 \ ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix -mcpu=pwr8 \
; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s ; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mattr=+altivec \ ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mattr=+altivec \
; RUN: -mattr=-vsx | FileCheck %s ; RUN: -mattr=-vsx | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr9 \ ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix -mcpu=pwr9 \
; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s ; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s
; Currently VSX support is disabled for this test because we generate lxsdx ; Currently VSX support is disabled for this test because we generate lxsdx
; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we ; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we
; have reg+imm addressing, and is on the list of things to be fixed. ; have reg+imm addressing, and is on the list of things to be fixed.
; The second run step is to ensure that -march=ppc64le is adequate to select ; The second run step is to ensure that -march=ppc64le is adequate to select
; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le. ; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le.
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test/CodeGen/PowerPC/ppc64le-calls.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s
; The second run of the test case is to ensure the behaviour is the same ; The second run of the test case is to ensure the behaviour is the same
; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le. ; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le.
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; Indirect calls requires a full stub creation ; Indirect calls requires a full stub creation
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test/CodeGen/PowerPC/ppc64le-localentry-large.ll

; RUN: llc -verify-machineinstrs -code-model=large < %s | FileCheck %s ; RUN: llc -verify-machineinstrs \
; RUN: -code-model=large < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@number64 = global i64 10, align 8 @number64 = global i64 10, align 8
; CHECK: .abiversion 2 ; CHECK: .abiversion 2
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test/CodeGen/PowerPC/ppc64le-localentry.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -O0 < %s | FileCheck %s ; RUN: -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs -O0 < %s | FileCheck %s ; RUN: -mcpu=pwr8 -O0 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -O0 < %s | FileCheck %s
; The second run of the test case is to ensure the behaviour is the same ; The second run of the test case is to ensure the behaviour is the same
; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le. ; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le.
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@number64 = global i64 10, align 8 @number64 = global i64 10, align 8
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test/CodeGen/PowerPC/ppc64le-smallarg.ll

; Verify that small structures and float arguments are passed in the ; Verify that small structures and float arguments are passed in the
; least significant part of a stack slot doubleword. ; least significant part of a stack slot doubleword.
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
%struct.large_arg = type { [8 x i64] } %struct.large_arg = type { [8 x i64] }
%struct.small_arg = type { i16, i8 } %struct.small_arg = type { i16, i8 }
@gl = common global %struct.large_arg zeroinitializer, align 8 @gl = common global %struct.large_arg zeroinitializer, align 8
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test/CodeGen/PowerPC/ppcf128-endian.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
; RUN: -mattr=-vsx < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 @g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
define void @callee(ppc_fp128 %x) { define void @callee(ppc_fp128 %x) {
entry: entry:
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test/CodeGen/PowerPC/pr13891.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.foo = type { i8, i8 } %struct.foo = type { i8, i8 }
define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline { define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline {
; CHECK-LABEL: _Z5check3foos: ; CHECK-LABEL: _Z5check3foos:
; CHECK: sth 3, {{[0-9]+}}(1) ; CHECK: sth 3, {{[0-9]+}}(1)
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test/CodeGen/PowerPC/pr26690.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s \
; RUN: -ppc-strip-register-prefix | FileCheck %s
%struct.anon = type { %struct.anon.0, %struct.anon.1 } %struct.anon = type { %struct.anon.0, %struct.anon.1 }
%struct.anon.0 = type { i32 } %struct.anon.0 = type { i32 }
%struct.anon.1 = type { i32 } %struct.anon.1 = type { i32 }
@i = common global i32 0, align 4 @i = common global i32 0, align 4
@b = common global i32* null, align 8 @b = common global i32* null, align 8
@c = common global i32 0, align 4 @c = common global i32 0, align 4
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test/CodeGen/PowerPC/pr28130.ll

; RUN: llc -verify-machineinstrs -O0 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O0 < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
%StructA = type { double, double, double, double, double, double, double, double } %StructA = type { double, double, double, double, double, double, double, double }
define void @Test(%StructA* %tmp) unnamed_addr #0 align 2 { define void @Test(%StructA* %tmp) unnamed_addr #0 align 2 {
; CHECK-LABEL: Test: ; CHECK-LABEL: Test:
; CHECK: lxvd2x ; CHECK: lxvd2x
; CHECK-NEXT: xxswapd ; CHECK-NEXT: xxswapd
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test/CodeGen/PowerPC/pr30640.ll

; RUN: llc -O2 -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -O2 -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s \
; RUN: -ppc-strip-register-prefix | FileCheck %s
define i64 @foo() { define i64 @foo() {
entry: entry:
ret i64 -3617008641903833651 ret i64 -3617008641903833651
; CHECK: lis [[REG1:[0-9]+]], -12851 ; CHECK: lis [[REG1:[0-9]+]], -12851
; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 52685 ; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 52685
; CHECK: rldimi 3, 3, 32, 0 ; CHECK: rldimi 3, 3, 32, 0
} }

test/CodeGen/PowerPC/pr32140.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 < %s \
; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: -ppc-strip-register-prefix | FileCheck %s
; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s \
; RUN: -ppc-strip-register-prefix | FileCheck %s
@as = common local_unnamed_addr global i16 0, align 2 @as = common local_unnamed_addr global i16 0, align 2
@bs = common local_unnamed_addr global i16 0, align 2 @bs = common local_unnamed_addr global i16 0, align 2
@ai = common local_unnamed_addr global i32 0, align 4 @ai = common local_unnamed_addr global i32 0, align 4
@bi = common local_unnamed_addr global i32 0, align 4 @bi = common local_unnamed_addr global i32 0, align 4
define void @bswapStorei64Toi32() { define void @bswapStorei64Toi32() {
; CHECK-LABEL: bswapStorei64Toi32: ; CHECK-LABEL: bswapStorei64Toi32:
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test/CodeGen/PowerPC/pr33093.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s \
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: -ppc-strip-register-prefix | FileCheck %s
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s \
; RUN: -ppc-strip-register-prefix | FileCheck %s
define zeroext i32 @ReverseBits(i32 zeroext %n) { define zeroext i32 @ReverseBits(i32 zeroext %n) {
; CHECK-LABEL: ReverseBits: ; CHECK-LABEL: ReverseBits:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 4, -21846
; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: slwi 6, 3, 1 ; CHECK-NEXT: slwi 6, 3, 1
; CHECK-NEXT: srwi 3, 3, 1 ; CHECK-NEXT: srwi 3, 3, 1
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test/CodeGen/PowerPC/preincprep-invoke.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@.str1 = external unnamed_addr constant [1 x i8], align 1 @.str1 = external unnamed_addr constant [1 x i8], align 1
@.str2 = external unnamed_addr constant [39 x i8], align 1 @.str2 = external unnamed_addr constant [39 x i8], align 1
declare void @_ZN13CStdOutStreamlsEPKc() declare void @_ZN13CStdOutStreamlsEPKc()
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test/CodeGen/PowerPC/pwr7-gt-nop.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo(float* nocapture %a, float* nocapture %b, float* nocapture readonly %c, float* nocapture %d) #0 { define void @foo(float* nocapture %a, float* nocapture %b, float* nocapture readonly %c, float* nocapture %d) #0 {
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
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test/CodeGen/PowerPC/pzero-fp-xored.ll

; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx -mcpu=pwr8 < %s | \ ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -ppc-strip-register-prefix \
; RUN: -mattr=+vsx -mcpu=pwr8 < %s | \
; RUN: FileCheck %s --implicit-check-not lxvd2x --implicit-check-not lfs ; RUN: FileCheck %s --implicit-check-not lxvd2x --implicit-check-not lfs
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=-altivec -mcpu=pwr8 -mattr=-vsx < %s | \ ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -ppc-strip-register-prefix \
; RUN: -mattr=-altivec -mcpu=pwr8 -mattr=-vsx < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-NVSXALT --implicit-check-not xxlxor \ ; RUN: FileCheck %s --check-prefix=CHECK-NVSXALT --implicit-check-not xxlxor \
; RUN: --implicit-check-not vxor ; RUN: --implicit-check-not vxor
define signext i32 @t1(float %x) local_unnamed_addr #0 { define signext i32 @t1(float %x) local_unnamed_addr #0 {
entry: entry:
%cmp = fcmp ogt float %x, 0.000000e+00 %cmp = fcmp ogt float %x, 0.000000e+00
%tmp = select i1 %cmp, i32 43, i32 11 %tmp = select i1 %cmp, i32 43, i32 11
ret i32 %tmp ret i32 %tmp
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test/CodeGen/PowerPC/qpx-bv-sint.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix < %s \
; RUN: -mcpu=a2q | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
define void @s452(i32 %inp1) nounwind { define void @s452(i32 %inp1) nounwind {
entry: entry:
br label %for.body4 br label %for.body4
for.body4: ; preds = %for.body4, %entry for.body4: ; preds = %for.body4, %entry
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test/CodeGen/PowerPC/qpx-bv.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix < %s \
; RUN: -mcpu=a2q | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
define <4 x double> @foo(double %f1, double %f2, double %f3, double %f4) { define <4 x double> @foo(double %f1, double %f2, double %f3, double %f4) {
%v1 = insertelement <4 x double> undef, double %f1, i32 0 %v1 = insertelement <4 x double> undef, double %f1, i32 0
%v2 = insertelement <4 x double> %v1, double %f2, i32 1 %v2 = insertelement <4 x double> %v1, double %f2, i32 1
%v3 = insertelement <4 x double> %v2, double %f3, i32 2 %v3 = insertelement <4 x double> %v2, double %f3, i32 2
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test/CodeGen/PowerPC/qpx-func-clobber.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix -mcpu=a2q \
; RUN: | FileCheck %s
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
declare <4 x double> @foo(<4 x double> %p) declare <4 x double> @foo(<4 x double> %p)
define <4 x double> @bar(<4 x double> %p, <4 x double> %q) { define <4 x double> @bar(<4 x double> %p, <4 x double> %q) {
entry: entry:
%v = call <4 x double> @foo(<4 x double> %p) %v = call <4 x double> @foo(<4 x double> %p)
%w = call <4 x double> @foo(<4 x double> %q) %w = call <4 x double> @foo(<4 x double> %q)
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test/CodeGen/PowerPC/qpx-load-splat.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define <4 x double> @foo(double* nocapture readonly %a) #0 { define <4 x double> @foo(double* nocapture readonly %a) #0 {
entry: entry:
%0 = load double, double* %a, align 8 %0 = load double, double* %a, align 8
%vecinit.i = insertelement <4 x double> undef, double %0, i32 0 %vecinit.i = insertelement <4 x double> undef, double %0, i32 0
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test/CodeGen/PowerPC/qpx-load.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix < %s -mcpu=a2q \
; RUN: | FileCheck %s
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
define <4 x double> @foo(<4 x double>* %p) { define <4 x double> @foo(<4 x double>* %p) {
entry: entry:
%v = load <4 x double>, <4 x double>* %p, align 8 %v = load <4 x double>, <4 x double>* %p, align 8
ret <4 x double> %v ret <4 x double> %v
} }
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test/CodeGen/PowerPC/qpx-rounding-ops.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q -enable-unsafe-fp-math | FileCheck -check-prefix=CHECK-FM %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q \
; RUN: -enable-unsafe-fp-math | FileCheck -check-prefix=CHECK-FM %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define <4 x float> @test1(<4 x float> %x) nounwind { define <4 x float> @test1(<4 x float> %x) nounwind {
%call = tail call <4 x float> @llvm.floor.v4f32(<4 x float> %x) nounwind readnone %call = tail call <4 x float> @llvm.floor.v4f32(<4 x float> %x) nounwind readnone
ret <4 x float> %call ret <4 x float> %call
; CHECK: test1: ; CHECK: test1:
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test/CodeGen/PowerPC/qpx-s-load.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mcpu=a2q -ppc-strip-register-prefix \
; RUN: | FileCheck %s
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
define <4 x float> @foo(<4 x float>* %p) { define <4 x float> @foo(<4 x float>* %p) {
entry: entry:
%v = load <4 x float>, <4 x float>* %p, align 4 %v = load <4 x float>, <4 x float>* %p, align 4
ret <4 x float> %v ret <4 x float> %v
} }
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test/CodeGen/PowerPC/qpx-s-sel.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix -mcpu=a2q \
; RUN: | FileCheck %s
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 @R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16
define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x i1> %c) nounwind readnone { define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x i1> %c) nounwind readnone {
entry: entry:
%r = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %r = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %r ret <4 x float> %r
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test/CodeGen/PowerPC/qpx-sel.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=a2q | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix -mcpu=a2q \
; RUN: | FileCheck %s
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 @R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16
define <4 x double> @test1(<4 x double> %a, <4 x double> %b, <4 x i1> %c) nounwind readnone { define <4 x double> @test1(<4 x double> %a, <4 x double> %b, <4 x i1> %c) nounwind readnone {
entry: entry:
%r = select <4 x i1> %c, <4 x double> %a, <4 x double> %b %r = select <4 x i1> %c, <4 x double> %a, <4 x double> %b
ret <4 x double> %r ret <4 x double> %r
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test/CodeGen/PowerPC/qpx-unal-cons-lds.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo(double* noalias nocapture %a, double* noalias nocapture readonly %b) #0 { define void @foo(double* noalias nocapture %a, double* noalias nocapture readonly %b) #0 {
entry: entry:
br label %vector.body br label %vector.body
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test/CodeGen/PowerPC/r31.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 | FileCheck %s
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
define i64 @foo(i64 %a) nounwind { define i64 @foo(i64 %a) nounwind {
entry: entry:
call void asm sideeffect "", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30}"() nounwind call void asm sideeffect "", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30}"() nounwind
br label %return br label %return
; CHECK: @foo ; CHECK: @foo
; CHECK: mr 31, 3 ; CHECK: mr 31, 3
return: ; preds = %entry return: ; preds = %entry
ret i64 %a ret i64 %a
} }

test/CodeGen/PowerPC/reg-names.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s \
; RUN: -ppc-strip-register-prefix | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-FN %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-FN %s
define i64 @test1(i64 %a, i64 %b) { define i64 @test1(i64 %a, i64 %b) {
; CHECK-LABEL: @test1 ; CHECK-LABEL: @test1
; CHECK-FN-LABEL: @test1 ; CHECK-FN-LABEL: @test1
entry: entry:
ret i64 %b ret i64 %b
; CHECK: mr 3, 4 ; CHECK: mr 3, 4
; CHECK-FN: mr r3, r4 ; CHECK-FN: mr r3, r4
; CHECK: blr ; CHECK: blr
; CHECK-FN: blr ; CHECK-FN: blr
} }

test/CodeGen/PowerPC/remat-imm.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
; ModuleID = 'test.c' ; ModuleID = 'test.c'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
target triple = "powerpc-unknown-linux" target triple = "powerpc-unknown-linux"
@.str = private unnamed_addr constant [6 x i8] c"%d,%d\00", align 1 @.str = private unnamed_addr constant [6 x i8] c"%d,%d\00", align 1
define i32 @main() nounwind { define i32 @main() nounwind {
entry: entry:
; CHECK: li 4, 128 ; CHECK: li 4, 128
; CHECK-NOT: mr 4, {{.*}} ; CHECK-NOT: mr 4, {{.*}}
%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i32 128, i32 128) nounwind %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i32 128, i32 128) nounwind
ret i32 0 ret i32 0
} }
declare i32 @printf(i8* nocapture, ...) nounwind declare i32 @printf(i8* nocapture, ...) nounwind

test/CodeGen/PowerPC/remove-redundant-moves.ll

; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s -ppc-strip-register-prefix | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: -verify-machineinstrs < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s --check-prefix=CHECK-BE
define double @test1(<2 x i64> %a) { define double @test1(<2 x i64> %a) {
entry: entry:
; CHECK-LABEL: test1 ; CHECK-LABEL: test1
; CHECK: xxswapd [[SW:[0-9]+]], 34 ; CHECK: xxswapd [[SW:[0-9]+]], 34
; CHECK: xscvsxddp 1, [[SW]] ; CHECK: xscvsxddp 1, [[SW]]
; CHECK-BE-LABEL: test1 ; CHECK-BE-LABEL: test1
; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34 ; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34
; CHECK-BE: xscvsxddp 1, [[CP]] ; CHECK-BE: xscvsxddp 1, [[CP]]
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test/CodeGen/PowerPC/retaddr2.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s -ppc-strip-register-prefix \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define i8* @test1() #0 { define i8* @test1() #0 {
entry: entry:
%0 = tail call i8* @llvm.returnaddress(i32 0) %0 = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %0 ret i8* %0
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test/CodeGen/PowerPC/rlwimi-and.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-crbits < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -mattr=-crbits < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-bgq-linux" target triple = "powerpc64-bgq-linux"
define void @test() align 2 { define void @test() align 2 {
entry: entry:
br i1 undef, label %codeRepl1, label %codeRepl31 br i1 undef, label %codeRepl1, label %codeRepl31
codeRepl1: ; preds = %entry codeRepl1: ; preds = %entry
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test/CodeGen/PowerPC/rlwimi-dyn-and.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 < %s \
; RUN: | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i32 @test1() #0 { define i32 @test1() #0 {
entry: entry:
%conv67.reload = load i32, i32* undef %conv67.reload = load i32, i32* undef
%const = bitcast i32 65535 to i32 %const = bitcast i32 65535 to i32
br label %next br label %next
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test/CodeGen/PowerPC/rlwinm-zero-ext.ll

; RUN: llc -verify-machineinstrs -O2 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -O2 < %s \
; RUN: | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; CHECK-LABEL: test1 ; CHECK-LABEL: test1
define i8 @test1(i32 %a) { define i8 @test1(i32 %a) {
entry: entry:
; CHECK-NOT: rlwinm {{{[0-9]+}}}, {{[0-9]+}}, 0, 24, 27 ; CHECK-NOT: rlwinm {{{[0-9]+}}}, {{[0-9]+}}, 0, 24, 27
; CHECK: rlwinm. [[REG:[0-9]+]], {{[0-9]+}}, 0, 24, 27 ; CHECK: rlwinm. [[REG:[0-9]+]], {{[0-9]+}}, 0, 24, 27
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test/CodeGen/PowerPC/rounding-ops.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: -mattr=-vsx < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s \
; RUN: | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define float @test1(float %x) nounwind { define float @test1(float %x) nounwind {
%call = tail call float @floorf(float %x) nounwind readnone %call = tail call float @floorf(float %x) nounwind readnone
ret float %call ret float %call
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
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test/CodeGen/PowerPC/sdag-ppcf128.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mattr=-crbits < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=-crbits < %s | FileCheck %s
; ;
; PR14751: Unsupported type in SelectionDAG::getConstantFP() ; PR14751: Unsupported type in SelectionDAG::getConstantFP()
define fastcc void @_D3std4math4sqrtFNaNbNfcZc() { define fastcc void @_D3std4math4sqrtFNaNbNfcZc() {
entry: entry:
br i1 undef, label %if, label %else br i1 undef, label %if, label %else
; CHECK: cmplwi 3, 0 ; CHECK: cmplwi 3, 0
if: ; preds = %entry if: ; preds = %entry
store { ppc_fp128, ppc_fp128 } zeroinitializer, { ppc_fp128, ppc_fp128 }* undef store { ppc_fp128, ppc_fp128 } zeroinitializer, { ppc_fp128, ppc_fp128 }* undef
ret void ret void
else: ; preds = %entry else: ; preds = %entry
unreachable unreachable
} }

test/CodeGen/PowerPC/sdiv-pow2.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefix=CHECK-32 %s ; RUN: -mcpu=ppc64 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s \
; RUN: | FileCheck -check-prefix=CHECK-32 %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define signext i32 @foo4(i32 signext %a) #0 { define signext i32 @foo4(i32 signext %a) #0 {
entry: entry:
%div = sdiv i32 %a, 8 %div = sdiv i32 %a, 8
ret i32 %div ret i32 %div
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test/CodeGen/PowerPC/select-i1-vs-i1.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; FIXME: We should check the operands to the cr* logical operation itself, but ; FIXME: We should check the operands to the cr* logical operation itself, but
; unfortunately, FileCheck does not yet understand how to do arithmetic, so we ; unfortunately, FileCheck does not yet understand how to do arithmetic, so we
; can't do so without introducing a register-allocation dependency. ; can't do so without introducing a register-allocation dependency.
define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
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test/CodeGen/PowerPC/setcc-to-sub.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
%class.PB2 = type { [1 x i32], %class.PB1* } %class.PB2 = type { [1 x i32], %class.PB1* }
%class.PB1 = type { [1 x i32], i64, i64, i32 } %class.PB1 = type { [1 x i32], i64, i64, i32 }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
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test/CodeGen/PowerPC/shift-cmp.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
define i1 @and_cmp_variable_power_of_two(i32 %x, i32 %y) { define i1 @and_cmp_variable_power_of_two(i32 %x, i32 %y) {
%shl = shl i32 1, %y %shl = shl i32 1, %y
%and = and i32 %x, %shl %and = and i32 %x, %shl
%cmp = icmp eq i32 %and, %shl %cmp = icmp eq i32 %and, %shl
ret i1 %cmp ret i1 %cmp
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test/CodeGen/PowerPC/shift128.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck --check-prefix=P8 --check-prefix=CHECK %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -mcpu=pwr9 -verify-machineinstrs < %s | FileCheck --check-prefix=P9 --check-prefix=CHECK %s ; RUN: | FileCheck --check-prefix=P8 --check-prefix=CHECK %s
; RUN: llc -ppc-strip-register-prefix -mcpu=pwr9 -verify-machineinstrs < %s \
; RUN: | FileCheck --check-prefix=P9 --check-prefix=CHECK %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; CHECK-LABEL: lshr: ; CHECK-LABEL: lshr:
; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64 ; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64
; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64 ; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64
; CHECK-DAG: srd [[R2:[0-9]+]], 3, 5 ; CHECK-DAG: srd [[R2:[0-9]+]], 3, 5
; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]] ; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]
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test/CodeGen/PowerPC/shift_mask.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix < %s | FileCheck %s
target triple = "powerpc64le-linux-gnu" target triple = "powerpc64le-linux-gnu"
define i8 @test000(i8 %a, i8 %b) { define i8 @test000(i8 %a, i8 %b) {
; CHECK-LABEL: test000: ; CHECK-LABEL: test000:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31
; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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test/CodeGen/PowerPC/sjlj.ll

; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-NOAV %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 \
; RUN: | FileCheck -check-prefix=CHECK-NOAV %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.__jmp_buf_tag = type { [64 x i64], i32, %struct.__sigset_t, [8 x i8] } %struct.__jmp_buf_tag = type { [64 x i64], i32, %struct.__sigset_t, [8 x i8] }
%struct.__sigset_t = type { [16 x i64] } %struct.__sigset_t = type { [16 x i64] }
@env_sigill = internal global [1 x %struct.__jmp_buf_tag] zeroinitializer, align 16 @env_sigill = internal global [1 x %struct.__jmp_buf_tag] zeroinitializer, align 16
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test/CodeGen/PowerPC/sjlj_no0x.ll

; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=a2 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: noinline nounwind ; Function Attrs: noinline nounwind
define void @_Z23BuiltinLongJmpFunc1_bufv() #0 { define void @_Z23BuiltinLongJmpFunc1_bufv() #0 {
entry: entry:
call void @llvm.eh.sjlj.longjmp(i8* bitcast (void ()* @_Z23BuiltinLongJmpFunc1_bufv to i8*)) call void @llvm.eh.sjlj.longjmp(i8* bitcast (void ()* @_Z23BuiltinLongJmpFunc1_bufv to i8*))
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test/CodeGen/PowerPC/splat-bug.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 -O0 -fast-isel=false < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=ppc64 \
; RUN: -O0 -fast-isel=false < %s | FileCheck %s
; Checks for a previous bug where vspltisb/vaddubm were issued in place ; Checks for a previous bug where vspltisb/vaddubm were issued in place
; of vsplitsh/vadduhm. ; of vsplitsh/vadduhm.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@a = external global <16 x i8> @a = external global <16 x i8>
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test/CodeGen/PowerPC/srl-mask.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i64 @foo(i64 %x) #0 { define i64 @foo(i64 %x) #0 {
entry: entry:
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
%a = lshr i64 %x, 35 %a = lshr i64 %x, 35
%b = and i64 %a, 65535 %b = and i64 %a, 65535
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test/CodeGen/PowerPC/stack-protector.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc-apple-darwin8 < %s \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-apple-darwin < %s | FileCheck -check-prefix=DARWIN64 %s ; RUN: | FileCheck -check-prefix=DARWIN32 %s
; RUN: llc -verify-machineinstrs -mtriple=ppc32-unknown-linux < %s | FileCheck -check-prefix=LINUX32 %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-apple-darwin < %s \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux < %s | FileCheck -check-prefix=LINUX64 %s ; RUN: | FileCheck -check-prefix=DARWIN64 %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=ppc32-unknown-linux < %s | FileCheck -check-prefix=LINUX32 %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux < %s \
; RUN: | FileCheck -check-prefix=LINUX64 %s
; DARWIN32: __stack_chk_guard ; DARWIN32: __stack_chk_guard
; DARWIN64: __stack_chk_guard ; DARWIN64: __stack_chk_guard
; LINUX32: lwz {{[0-9]+}}, -28680(2) ; LINUX32: lwz {{[0-9]+}}, -28680(2)
; LINUX64: ld {{[0-9]+}}, -28688(13) ; LINUX64: ld {{[0-9]+}}, -28688(13)
; DARWIN32: __stack_chk_fail ; DARWIN32: __stack_chk_fail
; DARWIN64: __stack_chk_fail ; DARWIN64: __stack_chk_fail
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test/CodeGen/PowerPC/stack-realign.ll

; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-FP %s ; RUN: -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -mtriple=powerpc-unknown-linux-gnu -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-32 %s ; RUN: llc -ppc-strip-register-prefix -mtriple=powerpc64-unknown-linux-gnu \
; RUN: llc -mtriple=powerpc-unknown-linux-gnu -disable-fp-elim -relocation-model=pic < %s | FileCheck -check-prefix=CHECK-32-PIC %s ; RUN: -mcpu=pwr7 -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-FP %s
; RUN: llc -ppc-strip-register-prefix -mtriple=powerpc-unknown-linux-gnu \
; RUN: -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-32 %s
; RUN: llc -ppc-strip-register-prefix -mtriple=powerpc-unknown-linux-gnu \
; RUN: -disable-fp-elim -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefix=CHECK-32-PIC %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.s = type { i32, i32 } %struct.s = type { i32, i32 }
declare void @bar(i32*) declare void @bar(i32*)
@barbaz = external global i32 @barbaz = external global i32
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test/CodeGen/PowerPC/stacksize.ll

; For ELFv2 ABI, we can avoid allocating the parameter area in the stack frame of the caller function ; For ELFv2 ABI, we can avoid allocating the parameter area in the stack frame of the caller function
; if all the arguments can be passed to the callee in registers. ; if all the arguments can be passed to the callee in registers.
; For ELFv1 ABI, we always need to allocate the parameter area. ; For ELFv1 ABI, we always need to allocate the parameter area.
; Tests for ELFv2 ABI ; Tests for ELFv2 ABI
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -target-abi elfv2 < %s | FileCheck %s -check-prefix=PPC64-ELFV2 ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -target-abi elfv2 < %s | FileCheck %s -check-prefix=PPC64-ELFV2 ; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -target-abi elfv2 < %s | FileCheck %s -check-prefix=PPC64-ELFV2
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -target-abi elfv2 < %s | FileCheck %s -check-prefix=PPC64-ELFV2
; Tests for ELFv1 ABI ; Tests for ELFv1 ABI
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -target-abi elfv1 < %s | FileCheck %s -check-prefix=PPC64-ELFV1 ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -target-abi elfv1 < %s | FileCheck %s -check-prefix=PPC64-ELFV1 ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -target-abi elfv1 < %s \
; RUN: | FileCheck %s -check-prefix=PPC64-ELFV1
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -target-abi elfv1 < %s \
; RUN: | FileCheck %s -check-prefix=PPC64-ELFV1
; If the callee has at most eight integer args, parameter area can be ommited for ELFv2 ABI. ; If the callee has at most eight integer args, parameter area can be ommited for ELFv2 ABI.
; PPC64-ELFV2-LABEL: WithoutParamArea1: ; PPC64-ELFV2-LABEL: WithoutParamArea1:
; PPC64-ELFV2-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1) ; PPC64-ELFV2-NOT: stw {{[0-9]+}}, -{{[0-9]+}}(1)
; PPC64-ELFV2: stdu 1, -32(1) ; PPC64-ELFV2: stdu 1, -32(1)
; PPC64-ELFV2: addi 1, 1, 32 ; PPC64-ELFV2: addi 1, 1, 32
; PPC64-ELFV2-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1) ; PPC64-ELFV2-NOT: lwz {{[0-9]+}}, -{{[0-9]+}}(1)
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test/CodeGen/PowerPC/stfiwx-2.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 | FileCheck %s
define void @test(float %F, i8* %P) { define void @test(float %F, i8* %P) {
%I = fptosi float %F to i32 %I = fptosi float %F to i32
%X = trunc i32 %I to i8 %X = trunc i32 %I to i8
store i8 %X, i8* %P store i8 %X, i8* %P
ret void ret void
; CHECK: fctiwz 0, 1 ; CHECK: fctiwz 0, 1
; CHECK: stfiwx 0, 0, 4 ; CHECK: stfiwx 0, 0, 4
; CHECK: lwz 4, 12(1) ; CHECK: lwz 4, 12(1)
; CHECK: stb 4, 0(3) ; CHECK: stb 4, 0(3)
; CHECK: blr ; CHECK: blr
} }

test/CodeGen/PowerPC/structsinmem.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=ppc64 \
; RUN: -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.s1 = type { i8 } %struct.s1 = type { i8 }
%struct.s2 = type { i16 } %struct.s2 = type { i16 }
%struct.s4 = type { i32 } %struct.s4 = type { i32 }
%struct.t1 = type { i8 } %struct.t1 = type { i8 }
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test/CodeGen/PowerPC/structsinregs.ll

; RUN: llc -verify-machineinstrs -mcpu=ppc64 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=ppc64 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.s1 = type { i8 } %struct.s1 = type { i8 }
%struct.s2 = type { i16 } %struct.s2 = type { i16 }
%struct.s4 = type { i32 } %struct.s4 = type { i32 }
%struct.t1 = type { i8 } %struct.t1 = type { i8 }
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test/CodeGen/PowerPC/subreg-postra-2.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @jbd2_journal_commit_transaction(i32 %input1, i32* %input2, i32* %input3, i8** %input4) #0 { define void @jbd2_journal_commit_transaction(i32 %input1, i32* %input2, i32* %input3, i8** %input4) #0 {
entry: entry:
br label %while.body392 br label %while.body392
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test/CodeGen/PowerPC/subreg-postra.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s -ppc-strip-register-prefix\
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s \
; RUN: -ppc-strip-register-prefix | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @jbd2_journal_commit_transaction(i32* %journal, i64 %inp1, i32 %inp2, define void @jbd2_journal_commit_transaction(i32* %journal, i64 %inp1, i32 %inp2,
i32* %inp3, i32** %inp4, i32* %inp3, i32** %inp4,
i32** %inp5, i1 %inp6, i32** %inp5, i1 %inp6,
i1 %inp7, i1 %inp8) #0 { i1 %inp7, i1 %inp8) #0 {
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test/CodeGen/PowerPC/subtract_from_imm.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
; Make sure that the subfic is generated iff possible ; Make sure that the subfic is generated iff possible
define i64 @subtract_from_imm1(i64 %v) nounwind readnone { define i64 @subtract_from_imm1(i64 %v) nounwind readnone {
entry: entry:
; CHECK-LABEL: subtract_from_imm1 ; CHECK-LABEL: subtract_from_imm1
; CHECK: subfic 3, 3, 32767 ; CHECK: subfic 3, 3, 32767
; CHECK: blr ; CHECK: blr
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test/CodeGen/PowerPC/svr4-redzone.ll

; RUN: llc -verify-machineinstrs -mtriple="powerpc-unknown-linux-gnu" < %s | FileCheck %s --check-prefix=PPC32 ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple="powerpc64-unknown-linux-gnu" < %s | FileCheck %s --check-prefix=PPC64 ; RUN: -mtriple="powerpc-unknown-linux-gnu" < %s \
; RUN: | FileCheck %s --check-prefix=PPC32
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple="powerpc64-unknown-linux-gnu" < %s \
; RUN: | FileCheck %s --check-prefix=PPC64
; PR15332 ; PR15332
define i32 @regalloc() nounwind { define i32 @regalloc() nounwind {
entry: entry:
%0 = add i32 1, 2 %0 = add i32 1, 2
ret i32 %0 ret i32 %0
} }
; PPC32-LABEL: regalloc: ; PPC32-LABEL: regalloc:
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test/CodeGen/PowerPC/swaps-le-2.ll

; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -O3 -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s \
; RUN: | FileCheck %s
; Test swap removal when a vector splat must be adjusted to make it legal. ; Test swap removal when a vector splat must be adjusted to make it legal.
; ;
; LH: 2016-11-17 ; LH: 2016-11-17
; Updated align attritue from 16 to 8 to keep swap instructions tests. ; Updated align attritue from 16 to 8 to keep swap instructions tests.
; Changes have been made on little-endian to use lvx and stvx ; Changes have been made on little-endian to use lvx and stvx
; instructions instead of lxvd2x/xxswapd and xxswapd/stxvd2x for ; instructions instead of lxvd2x/xxswapd and xxswapd/stxvd2x for
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test/CodeGen/PowerPC/swaps-le-5.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr8 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
; These tests verify that VSX swap optimization works for various ; These tests verify that VSX swap optimization works for various
; manipulations of <2 x double> vectors. ; manipulations of <2 x double> vectors.
@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16 @x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16 @z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
define void @bar0(double %y) { define void @bar0(double %y) {
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test/CodeGen/PowerPC/swaps-le-6.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr8 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: llc -ppc-strip-register-prefix -mcpu=pwr9 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-P9 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-P9 \
; RUN: --implicit-check-not xxswapd ; RUN: --implicit-check-not xxswapd
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: llc -ppc-strip-register-prefix -mcpu=pwr9 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -O3 \
; RUN: -verify-machineinstrs -mattr=-power9-vector < %s | FileCheck %s ; RUN: -verify-machineinstrs -mattr=-power9-vector < %s | FileCheck %s
; These tests verify that VSX swap optimization works when loading a scalar ; These tests verify that VSX swap optimization works when loading a scalar
; into a vector register. ; into a vector register.
@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16 @x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16 @z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
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test/CodeGen/PowerPC/tail-dup-break-cfg.ll

; RUN: llc -O2 -o - %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -O2 -o - %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-grtev4-linux-gnu" target triple = "powerpc64le-grtev4-linux-gnu"
; Intended layout: ; Intended layout:
; The code for tail-duplication during layout will produce the layout: ; The code for tail-duplication during layout will produce the layout:
; test1 ; test1
; test2 ; test2
; body1 (with copy of test2) ; body1 (with copy of test2)
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test/CodeGen/PowerPC/tail-dup-layout.ll

; RUN: llc -O2 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O2 %s ; RUN: llc -ppc-strip-register-prefix -O2 -o - %s \
; RUN: llc -O3 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O3 %s ; RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O2 %s
; RUN: llc -ppc-strip-register-prefix -O3 -o - %s \
; RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O3 %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-grtev4-linux-gnu" target triple = "powerpc64le-grtev4-linux-gnu"
; Intended layout: ; Intended layout:
; The chain-based outlining produces the layout ; The chain-based outlining produces the layout
; test1 ; test1
; test2 ; test2
; test3 ; test3
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test/CodeGen/PowerPC/testBitReverse.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
declare i32 @llvm.bitreverse.i32(i32) declare i32 @llvm.bitreverse.i32(i32)
define i32 @testBitReverseIntrinsicI32(i32 %arg) { define i32 @testBitReverseIntrinsicI32(i32 %arg) {
; CHECK-LABEL: testBitReverseIntrinsicI32: ; CHECK-LABEL: testBitReverseIntrinsicI32:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 4, -21846
; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: slwi 6, 3, 1 ; CHECK-NEXT: slwi 6, 3, 1
; CHECK-NEXT: srwi 3, 3, 1 ; CHECK-NEXT: srwi 3, 3, 1
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test/CodeGen/PowerPC/thread-pointer.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s --check-prefix=CHECK-32 ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s --check-prefix=CHECK-64 ; RUN: < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s --check-prefix=CHECK-64 ; RUN: | FileCheck %s --check-prefix=CHECK-32
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: < %s -mtriple=powerpc64-unknown-linux-gnu \
; RUN: | FileCheck %s --check-prefix=CHECK-64
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: < %s -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: | FileCheck %s --check-prefix=CHECK-64
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i8* @llvm.thread.pointer() #1 declare i8* @llvm.thread.pointer() #1
define i8* @thread_pointer() { define i8* @thread_pointer() {
; CHECK-32-LABEL: @thread_pointer ; CHECK-32-LABEL: @thread_pointer
; CHECK-32: mr 3, 2 ; CHECK-32: mr 3, 2
; CHECK-32: blr ; CHECK-32: blr
; CHECK-64-LABEL: @thread_pointer ; CHECK-64-LABEL: @thread_pointer
; CHECK-64: mr 3, 13 ; CHECK-64: mr 3, 13
; CHECK-64: blr ; CHECK-64: blr
%1 = tail call i8* @llvm.thread.pointer() %1 = tail call i8* @llvm.thread.pointer()
ret i8* %1 ret i8* %1
} }

test/CodeGen/PowerPC/tls-cse.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -relocation-model=pic < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -relocation-model=pic < %s | grep "__tls_get_addr" | count 1 ; RUN: -O2 -relocation-model=pic < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -O2 -relocation-model=pic < %s | grep "__tls_get_addr" | count 1
; This test was derived from LLVM's own ; This test was derived from LLVM's own
; PrettyStackTraceEntry::~PrettyStackTraceEntry(). It demonstrates an ; PrettyStackTraceEntry::~PrettyStackTraceEntry(). It demonstrates an
; opportunity for CSE of calls to __tls_get_addr(). ; opportunity for CSE of calls to __tls_get_addr().
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
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test/CodeGen/PowerPC/tls-pic.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs\
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s ; RUN: -mcpu=pwr7 -O0 -relocation-model=pic < %s \
; RUN: llc -verify-machineinstrs -mtriple=ppc32-- -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0-32 %s ; RUN: | FileCheck -check-prefix=OPT0 %s
; RUN: llc -verify-machineinstrs -mtriple=ppc32-- -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1-32 %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mcpu=pwr7 -O1 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefix=OPT1 %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=ppc32-- -O0 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefix=OPT0-32 %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=ppc32-- -O1 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefix=OPT1-32 %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Test correct assembly code generation for thread-local storage using ; Test correct assembly code generation for thread-local storage using
; the local dynamic model. ; the local dynamic model.
@a = hidden thread_local global i32 0, align 4 @a = hidden thread_local global i32 0, align 4
define signext i32 @main() nounwind { define signext i32 @main() nounwind {
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test/CodeGen/PowerPC/tls-store2.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O2 -relocation-model=pic < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -O2 -relocation-model=pic < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; Test back-to-back stores of TLS variables to ensure call sequences no ; Test back-to-back stores of TLS variables to ensure call sequences no
; longer overlap. ; longer overlap.
@__once_callable = external thread_local global i8** @__once_callable = external thread_local global i8**
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test/CodeGen/PowerPC/tls.ll

; RUN: llc -relocation-model=static -verify-machineinstrs -O0 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s ; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: llc -relocation-model=static -verify-machineinstrs -O1 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s ; RUN: -verify-machineinstrs -O0 < %s -mcpu=ppc64 \
; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=ppc32-- -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s ; RUN: | FileCheck -check-prefix=OPT0 %s
; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: -verify-machineinstrs -O1 < %s -mcpu=ppc64 \
; RUN: | FileCheck -check-prefix=OPT1 %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -O0 < %s -mtriple=ppc32-- -mcpu=ppc \
; RUN: | FileCheck -check-prefix=OPT0-PPC32 %s
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@a = thread_local global i32 0, align 4 @a = thread_local global i32 0, align 4
;OPT0-LABEL: localexec: ;OPT0-LABEL: localexec:
;OPT1-LABEL: localexec: ;OPT1-LABEL: localexec:
define i32 @localexec() nounwind { define i32 @localexec() nounwind {
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test/CodeGen/PowerPC/tls_get_addr_clobbers.ll

; RUN: llc -verify-machineinstrs -mtriple="powerpc64le-unknown-linux-gnu" -relocation-model=pic < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple="powerpc64le-unknown-linux-gnu" \
; RUN: -relocation-model=pic < %s | FileCheck %s
@a = thread_local global i32* null, align 8 @a = thread_local global i32* null, align 8
define void @test_foo(i32* nocapture %x01, i32* nocapture %x02, i32* nocapture %x03, i32* nocapture %x04, i32* nocapture %x05, i32* nocapture %x06, i32* nocapture %x07, i32* nocapture %x08) #0 { define void @test_foo(i32* nocapture %x01, i32* nocapture %x02, i32* nocapture %x03, i32* nocapture %x04, i32* nocapture %x05, i32* nocapture %x06, i32* nocapture %x07, i32* nocapture %x08) #0 {
entry: entry:
; CHECK-LABEL: test_foo: ; CHECK-LABEL: test_foo:
; CHECK: stdu 1, {{-?[0-9]+}}(1) ; CHECK: stdu 1, {{-?[0-9]+}}(1)
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test/CodeGen/PowerPC/tls_get_addr_stackframe.ll

; RUN: llc -verify-machineinstrs -mtriple="powerpc64le-unknown-linux-gnu" -relocation-model=pic < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple="powerpc64le-unknown-linux-gnu" \
; RUN: -relocation-model=pic < %s | FileCheck %s
; CHECK-LABEL: foo_test: ; CHECK-LABEL: foo_test:
; CHECK: mflr 0 ; CHECK: mflr 0
; CHECK: __tls_get_addr ; CHECK: __tls_get_addr
%struct1.2.41 = type { %struct2.0.39, %struct3.1.40, %struct1.2.41* } %struct1.2.41 = type { %struct2.0.39, %struct3.1.40, %struct1.2.41* }
%struct2.0.39 = type { i64, i32, i32, i32, i32 } %struct2.0.39 = type { i64, i32, i32, i32, i32 }
%struct3.1.40 = type { [160 x i8] } %struct3.1.40 = type { [160 x i8] }
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test/CodeGen/PowerPC/toc-load-sched-bug.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
; This test checks for misordering of a TOC restore instruction relative ; This test checks for misordering of a TOC restore instruction relative
; to subsequent uses of the TOC register. Previously this test broke ; to subsequent uses of the TOC register. Previously this test broke
; because there was no TOC register dependency between the instructions, ; because there was no TOC register dependency between the instructions,
; and the usual stack-adjust instructions that held the TOC restore in ; and the usual stack-adjust instructions that held the TOC restore in
; place were optimized away. ; place were optimized away.
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test/CodeGen/PowerPC/unal-altivec-wint.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 < %s \
; RUN: | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1 declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
define <4 x i32> @test1(<4 x i32>* %h) #0 { define <4 x i32> @test1(<4 x i32>* %h) #0 {
entry: entry:
%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1 %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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test/CodeGen/PowerPC/unal-altivec.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=g5 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s -mcpu=g5 \
; RUN: | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @foo(float* noalias nocapture %a, float* noalias nocapture %b) #0 { define void @foo(float* noalias nocapture %a, float* noalias nocapture %b) #0 {
vector.ph: vector.ph:
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %vector.ph vector.body: ; preds = %vector.body, %vector.ph
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test/CodeGen/PowerPC/unal-vec-ldst.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 { define <16 x i8> @test_l_v16i8(<16 x i8>* %p) #0 {
entry: entry:
%r = load <16 x i8>, <16 x i8>* %p, align 1 %r = load <16 x i8>, <16 x i8>* %p, align 1
ret <16 x i8> %r ret <16 x i8> %r
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test/CodeGen/PowerPC/unal4-std.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=-vsx| FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -mattr=-vsx| FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s -mcpu=pwr7 \
; RUN: -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define void @copy_to_conceal(<8 x i16>* %inp) #0 { define void @copy_to_conceal(<8 x i16>* %inp) #0 {
entry: entry:
store <8 x i16> zeroinitializer, <8 x i16>* %inp, align 2 store <8 x i16> zeroinitializer, <8 x i16>* %inp, align 2
br label %if.end210 br label %if.end210
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test/CodeGen/PowerPC/vaddsplat.ll

; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 <%s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -O0 \
; RUN: -mcpu=pwr7 <%s | FileCheck %s
; Test optimizations of build_vector for 6-bit immediates. ; Test optimizations of build_vector for 6-bit immediates.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%v4i32 = type <4 x i32> %v4i32 = type <4 x i32>
%v8i16 = type <8 x i16> %v8i16 = type <8 x i16>
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test/CodeGen/PowerPC/varargs-struct-float.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix -mcpu=pwr7 \
; RUN: -O0 < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.Sf1 = type { float } %struct.Sf1 = type { float }
define void @foo(float inreg %s.coerce) nounwind { define void @foo(float inreg %s.coerce) nounwind {
entry: entry:
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test/CodeGen/PowerPC/vec-abi-align.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: -mattr=-vsx < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \
; RUN: -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.s2 = type { i64, <4 x float> } %struct.s2 = type { i64, <4 x float> }
@ve = external global <4 x float> @ve = external global <4 x float>
@n = external global i64 @n = external global i64
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test/CodeGen/PowerPC/vec_absd.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr9 \
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr9 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; Check the vabsd* instructions that were added in PowerISA V3.0 ; Check the vabsd* instructions that were added in PowerISA V3.0
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8>, <16 x i8>) declare <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8>, <16 x i8>)
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>)
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test/CodeGen/PowerPC/vec_add_sub_doubleword.ll

; Check VMX 64-bit integer operations ; Check VMX 64-bit integer operations
; ;
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \
; RUN: | FileCheck %s
define <2 x i64> @test_add(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @test_add(<2 x i64> %x, <2 x i64> %y) nounwind {
%result = add <2 x i64> %x, %y %result = add <2 x i64> %x, %y
ret <2 x i64> %result ret <2 x i64> %result
; CHECK: vaddudm 2, 2, 3 ; CHECK: vaddudm 2, 2, 3
} }
define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind { define <2 x i64> @increment_by_one(<2 x i64> %x) nounwind {
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test/CodeGen/PowerPC/vec_add_sub_quadword.ll

; Check VMX 128-bit integer operations ; Check VMX 128-bit integer operations
; ;
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \
; RUN: | FileCheck %s
define <1 x i128> @out_of_bounds_insertelement(<1 x i128> %x, i128 %val) nounwind { define <1 x i128> @out_of_bounds_insertelement(<1 x i128> %x, i128 %val) nounwind {
%tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 1 %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 1
%result = add <1 x i128> %x, %tmpvec %result = add <1 x i128> %x, %tmpvec
ret <1 x i128> %result ret <1 x i128> %result
; CHECK-LABEL: @out_of_bounds_insertelement ; CHECK-LABEL: @out_of_bounds_insertelement
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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test/CodeGen/PowerPC/vec_clz.ll

; Check the vctlz* instructions that were added in P8 ; Check the vctlz* instructions that were added in P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -mattr=-vsx < %s | FileCheck %s
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) nounwind readnone declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) nounwind readnone
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) nounwind readnone declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) nounwind readnone
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>) nounwind readnone declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>) nounwind readnone
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) nounwind readnone declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) nounwind readnone
define <16 x i8> @test_v16i8(<16 x i8> %x) nounwind readnone { define <16 x i8> @test_v16i8(<16 x i8> %x) nounwind readnone {
%vcnt = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x) %vcnt = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x)
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test/CodeGen/PowerPC/vec_cmp.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr6 \
; RUN: -mattr=+altivec < %s | FileCheck %s
; Check vector comparisons using altivec. For non-native types, just basic ; Check vector comparisons using altivec. For non-native types, just basic
; comparison instruction check is done. For altivec supported type (16i8, ; comparison instruction check is done. For altivec supported type (16i8,
; 8i16, 4i32, and 4f32) all the comparisons operators (==, !=, >, >=, <, <=) ; 8i16, 4i32, and 4f32) all the comparisons operators (==, !=, >, >=, <, <=)
; are checked. ; are checked.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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test/CodeGen/PowerPC/vec_cmpd.ll

; Test the doubleword comparison instructions that were added in POWER8 ; Test the doubleword comparison instructions that were added in POWER8
; ;
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -mattr=-vsx < %s | FileCheck %s
define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone { define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
%cmp = icmp eq <2 x i64> %x, %y %cmp = icmp eq <2 x i64> %x, %y
%result = sext <2 x i1> %cmp to <2 x i64> %result = sext <2 x i1> %cmp to <2 x i64>
ret <2 x i64> %result ret <2 x i64> %result
; CHECK-LABEL: v2si64_cmp: ; CHECK-LABEL: v2si64_cmp:
; CHECK: vcmpequd 2, 2, 3 ; CHECK: vcmpequd 2, 2, 3
} }
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test/CodeGen/PowerPC/vec_conv.ll

; RUN: llc -verify-machineinstrs -mattr=+altivec < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mattr=+altivec < %s | FileCheck %s
; Check vector float/int conversion using altivec. ; Check vector float/int conversion using altivec.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
@cte_float = global <4 x float> <float 6.5e+00, float 6.5e+00, float 6.5e+00, float 6.5e+00>, align 16 @cte_float = global <4 x float> <float 6.5e+00, float 6.5e+00, float 6.5e+00, float 6.5e+00>, align 16
@cte_int = global <4 x i32> <i32 6, i32 6, i32 6, i32 6>, align 16 @cte_int = global <4 x i32> <i32 6, i32 6, i32 6, i32 6>, align 16
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test/CodeGen/PowerPC/vec_extload.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec -code-model=small < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr6 \
; RUN: -mattr=+altivec -code-model=small < %s | FileCheck %s
; Check vector extend load expansion with altivec enabled. ; Check vector extend load expansion with altivec enabled.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Altivec does not provides an sext instruction, so it expands ; Altivec does not provides an sext instruction, so it expands
; a set of vector stores (stvx), bytes load/sign expand/store ; a set of vector stores (stvx), bytes load/sign expand/store
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test/CodeGen/PowerPC/vec_extract_p9.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-BE
define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) { define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
; CHECK-LE-LABEL: test1: ; CHECK-LE-LABEL: test1:
; CHECK-LE: # BB#0: # %entry ; CHECK-LE: # BB#0: # %entry
; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: vextubrx 3, 5, 2
; CHECK-LE-NEXT: clrldi 3, 3, 56 ; CHECK-LE-NEXT: clrldi 3, 3, 56
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: test1: ; CHECK-BE-LABEL: test1:
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test/CodeGen/PowerPC/vec_fmuladd.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr6 \
; RUN: -mattr=+altivec < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float> %val, <2 x float>, <2 x float>) declare <2 x float> @llvm.fmuladd.v2f32(<2 x float> %val, <2 x float>, <2 x float>)
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float> %val, <4 x float>, <4 x float>) declare <4 x float> @llvm.fmuladd.v4f32(<4 x float> %val, <4 x float>, <4 x float>)
declare <8 x float> @llvm.fmuladd.v8f32(<8 x float> %val, <8 x float>, <8 x float>) declare <8 x float> @llvm.fmuladd.v8f32(<8 x float> %val, <8 x float>, <8 x float>)
declare <2 x double> @llvm.fmuladd.v2f64(<2 x double> %val, <2 x double>, <2 x double>) declare <2 x double> @llvm.fmuladd.v2f64(<2 x double> %val, <2 x double>, <2 x double>)
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test/CodeGen/PowerPC/vec_int_ext.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-BE
define <4 x i32> @vextsb2wLE(<16 x i8> %a) { define <4 x i32> @vextsb2wLE(<16 x i8> %a) {
; CHECK-LE-LABEL: vextsb2wLE: ; CHECK-LE-LABEL: vextsb2wLE:
; CHECK-LE: # BB#0: # %entry ; CHECK-LE: # BB#0: # %entry
; CHECK-LE-NEXT: vextsb2w 2, 2 ; CHECK-LE-NEXT: vextsb2w 2, 2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: vextsb2wLE: ; CHECK-BE-LABEL: vextsb2wLE:
; CHECK-BE: # BB#0: # %entry ; CHECK-BE: # BB#0: # %entry
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test/CodeGen/PowerPC/vec_mergeow.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LE ; RUN: FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-BE ; RUN: FileCheck %s -check-prefix=CHECK-BE
; Check for a vector merge instruction using two inputs ; Check for a vector merge instruction using two inputs
; The shufflevector specifies the even elements, using big endian element ; The shufflevector specifies the even elements, using big endian element
; ordering. If run on a big endian machine, this should produce the vmrgew ; ordering. If run on a big endian machine, this should produce the vmrgew
; instruction. If run on a little endian machine, this should produce the ; instruction. If run on a little endian machine, this should produce the
; vmrgow instruction. Note also that on little endian the input registers ; vmrgow instruction. Note also that on little endian the input registers
; are swapped also. ; are swapped also.
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test/CodeGen/PowerPC/vec_minmax.ll

; Test the vector min/max doubleword instructions added for P8 ; Test the vector min/max doubleword instructions added for P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \
; RUN: | FileCheck %s
declare <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vmaxud(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vminsd(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vminsd(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vminud(<2 x i64>, <2 x i64>) nounwind readnone
define <2 x i64> @test_vmaxsd(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @test_vmaxsd(<2 x i64> %x, <2 x i64> %y) {
%tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64> %x, <2 x i64> %y) %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmaxsd(<2 x i64> %x, <2 x i64> %y)
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test/CodeGen/PowerPC/vec_mul.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-altivec | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s ; RUN: -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE ; RUN: -mattr=-power8-altivec | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-VSX ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE-VSX ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx \
; RUN: -mcpu=pwr7 | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx \
; RUN: -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx \
; RUN: -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-VSX
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=+vsx \
; RUN: -mcpu=pwr8 -mattr=-power8-altivec | FileCheck %s \
; RUN: -check-prefix=CHECK-LE-VSX
define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) { define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
%tmp = load <4 x i32>, <4 x i32>* %X ; <<4 x i32>> [#uses=1] %tmp = load <4 x i32>, <4 x i32>* %X ; <<4 x i32>> [#uses=1]
%tmp2 = load <4 x i32>, <4 x i32>* %Y ; <<4 x i32>> [#uses=1] %tmp2 = load <4 x i32>, <4 x i32>* %Y ; <<4 x i32>> [#uses=1]
%tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1] %tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1]
ret <4 x i32> %tmp3 ret <4 x i32> %tmp3
} }
; CHECK-LABEL: test_v4i32: ; CHECK-LABEL: test_v4i32:
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test/CodeGen/PowerPC/vec_mul_even_odd.ll

; Check the vector multiply even/odd word instructions that were added in P8 ; Check the vector multiply even/odd word instructions that were added in P8
; ;
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \
; RUN: | FileCheck %s
declare <2 x i64> @llvm.ppc.altivec.vmuleuw(<4 x i32>, <4 x i32>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vmuleuw(<4 x i32>, <4 x i32>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vmulesw(<4 x i32>, <4 x i32>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vmulesw(<4 x i32>, <4 x i32>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vmulouw(<4 x i32>, <4 x i32>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vmulouw(<4 x i32>, <4 x i32>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vmulosw(<4 x i32>, <4 x i32>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vmulosw(<4 x i32>, <4 x i32>) nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmuluwm(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmuluwm(<4 x i32>, <4 x i32>) nounwind readnone
define <2 x i64> @test_vmuleuw(<4 x i32> %x, <4 x i32> %y) nounwind readnone { define <2 x i64> @test_vmuleuw(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
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test/CodeGen/PowerPC/vec_popcnt.ll

; Check the vecpopcnt* instructions that were added in P8 ; Check the vecpopcnt* instructions that were added in P8
; In addition, check the conversions to/from the v2i64 VMX register that was also added in P8. ; In addition, check the conversions to/from the v2i64 VMX register that was also added in P8.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \
; RUN: | FileCheck %s
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
define <16 x i8> @test_v16i8_v2i64(<2 x i64> %x) nounwind readnone { define <16 x i8> @test_v16i8_v2i64(<2 x i64> %x) nounwind readnone {
%tmp = bitcast <2 x i64> %x to <16 x i8>; %tmp = bitcast <2 x i64> %x to <16 x i8>;
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test/CodeGen/PowerPC/vec_revb.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
define <8 x i16> @testXXBRH(<8 x i16> %a) { define <8 x i16> @testXXBRH(<8 x i16> %a) {
; CHECK-LABEL: testXXBRH: ; CHECK-LABEL: testXXBRH:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: xxbrh 34, 34 ; CHECK-NEXT: xxbrh 34, 34
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
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test/CodeGen/PowerPC/vec_rotate_shift.ll

; Test the vector rotate and shift doubleword instructions that were added in P8 ; Test the vector rotate and shift doubleword instructions that were added in P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \
; RUN: | FileCheck %s
declare <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vsld(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vsld(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vsrd(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vsrd(<2 x i64>, <2 x i64>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vsrad(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.ppc.altivec.vsrad(<2 x i64>, <2 x i64>) nounwind readnone
define <2 x i64> @test_vrld(<2 x i64> %x, <2 x i64> %y) nounwind readnone { define <2 x i64> @test_vrld(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
%tmp = tail call <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64> %x, <2 x i64> %y) %tmp = tail call <2 x i64> @llvm.ppc.altivec.vrld(<2 x i64> %x, <2 x i64> %y)
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test/CodeGen/PowerPC/vec_shuffle_le.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx \
; RUN: -mcpu=pwr7 | FileCheck %s
define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) { define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry: entry:
; CHECK: VPKUHUM_xy: ; CHECK: VPKUHUM_xy:
%tmp = load <16 x i8>, <16 x i8>* %A %tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B %tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
; CHECK: lvx [[REG1:[0-9]+]] ; CHECK: lvx [[REG1:[0-9]+]]
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test/CodeGen/PowerPC/vec_sldwi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LE ; RUN: FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-BE ; RUN: FileCheck %s -check-prefix=CHECK-BE
; Possible LE ShuffleVector masks (Case 1): ; Possible LE ShuffleVector masks (Case 1):
; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3) ; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3)
; ShuffleVector((vector int)a, vector(int)b, 7, 0, 1, 2) ; ShuffleVector((vector int)a, vector(int)b, 7, 0, 1, 2)
; ShuffleVector((vector int)a, vector(int)b, 6, 7, 0, 1) ; ShuffleVector((vector int)a, vector(int)b, 6, 7, 0, 1)
; ShuffleVector((vector int)a, vector(int)b, 5, 6, 7, 0) ; ShuffleVector((vector int)a, vector(int)b, 5, 6, 7, 0)
; which targets at: ; which targets at:
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test/CodeGen/PowerPC/vec_sqrt.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec,+fsqrt < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr6 \
; RUN: -mattr=+altivec,+fsqrt < %s | FileCheck %s
; Check for vector sqrt expansion using floating-point types, since altivec ; Check for vector sqrt expansion using floating-point types, since altivec
; does not provide an fsqrt instruction for vector. ; does not provide an fsqrt instruction for vector.
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
declare <2 x float> @llvm.sqrt.v2f32(<2 x float> %val) declare <2 x float> @llvm.sqrt.v2f32(<2 x float> %val)
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test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll

; Check the miscellaneous logical vector operations added in P8 ; Check the miscellaneous logical vector operations added in P8
; ;
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -mattr=-vsx < %s | FileCheck %s
; Test x eqv y ; Test x eqv y
define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
%tmp = xor <4 x i32> %x, %y %tmp = xor <4 x i32> %x, %y
%ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1> %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %ret_val ret <4 x i32> %ret_val
; CHECK: veqv 2, 2, 3 ; CHECK: veqv 2, 2, 3
} }
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test/CodeGen/PowerPC/vec_xxpermdi.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-LE ; RUN: FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-BE ; RUN: FileCheck %s -check-prefix=CHECK-BE
; Possible LE ShuffleVector masks (Case 1): ; Possible LE ShuffleVector masks (Case 1):
; ShuffleVector((vector double)a, (vector double)b, 3, 1) ; ShuffleVector((vector double)a, (vector double)b, 3, 1)
; ShuffleVector((vector double)a, (vector double)b, 2, 1) ; ShuffleVector((vector double)a, (vector double)b, 2, 1)
; ShuffleVector((vector double)a, (vector double)b, 3, 0) ; ShuffleVector((vector double)a, (vector double)b, 3, 0)
; ShuffleVector((vector double)a, (vector double)b, 2, 0) ; ShuffleVector((vector double)a, (vector double)b, 2, 0)
; which targets at: ; which targets at:
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test/CodeGen/PowerPC/vperm-lowering.ll

; RUN: llc -verify-machineinstrs -O0 -fast-isel=false -mcpu=ppc64 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -O0 \
; RUN: -fast-isel=false -mcpu=ppc64 < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
define <16 x i8> @foo() nounwind ssp { define <16 x i8> @foo() nounwind ssp {
%1 = shufflevector <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, <16 x i32> <i32 0, i32 5, i32 10, i32 15, i32 20, i32 25, i32 30, i32 3, i32 8, i32 13, i32 18, i32 23, i32 28, i32 1, i32 6, i32 11> %1 = shufflevector <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, <16 x i32> <i32 0, i32 5, i32 10, i32 15, i32 20, i32 25, i32 30, i32 3, i32 8, i32 13, i32 18, i32 23, i32 28, i32 1, i32 6, i32 11>
ret <16 x i8> %1 ret <16 x i8> %1
} }
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test/CodeGen/PowerPC/vrspill.ll

; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -O0 -ppc-strip-register-prefix \
; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck %s ; RUN: -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx \
; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -O0 -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx \
; RUN: -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -O0 -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx \
; RUN: -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s \
; RUN: | FileCheck -check-prefix=CHECK-VSX %s
; This verifies that we generate correct spill/reload code for vector regs. ; This verifies that we generate correct spill/reload code for vector regs.
define void @addrtaken(i32 %i, <4 x float> %w) nounwind { define void @addrtaken(i32 %i, <4 x float> %w) nounwind {
entry: entry:
%i.addr = alloca i32, align 4 %i.addr = alloca i32, align 4
%w.addr = alloca <4 x float>, align 16 %w.addr = alloca <4 x float>, align 16
store i32 %i, i32* %i.addr, align 4 store i32 %i, i32* %i.addr, align 4
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test/CodeGen/PowerPC/vsx-args.ll

; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | \ ; RUN: -mattr=+vsx | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s -mcpu=pwr7 \
; RUN: -mattr=+vsx -fast-isel -O0 | \
; RUN: FileCheck -check-prefix=CHECK-FISL %s ; RUN: FileCheck -check-prefix=CHECK-FISL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
declare <2 x double> @sv(<2 x double>, <2 x i64>, <4 x float>) #0 declare <2 x double> @sv(<2 x double>, <2 x i64>, <4 x float>) #0
define <2 x double> @main(<4 x float> %a, <2 x double> %b, <2 x i64> %c) #1 { define <2 x double> @main(<4 x float> %a, <2 x double> %b, <2 x i64> %c) #1 {
entry: entry:
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test/CodeGen/PowerPC/vsx-elementary-arith.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
@a = global float 3.000000e+00, align 4 @a = global float 3.000000e+00, align 4
@b = global float 4.000000e+00, align 4 @b = global float 4.000000e+00, align 4
@c = global double 3.000000e+00, align 8 @c = global double 3.000000e+00, align 8
@d = global double 4.000000e+00, align 8 @d = global double 4.000000e+00, align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define float @emit_xsaddsp() { define float @emit_xsaddsp() {
entry: entry:
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test/CodeGen/PowerPC/vsx-p8.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr8 \
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s ; RUN: -mattr=+power8-vector < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr8 \
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s ; RUN: -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr8 \
; RUN: -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr8 \
; RUN: -mattr=+power8-vector -fast-isel -O0 < %s \
; RUN: | FileCheck -check-prefix=CHECK-FISL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Unaligned loads/stores on P8 and later should use VSX where possible. ; Unaligned loads/stores on P8 and later should use VSX where possible.
define <2 x double> @test28u(<2 x double>* %a) { define <2 x double> @test28u(<2 x double>* %a) {
%v = load <2 x double>, <2 x double>* %a, align 8 %v = load <2 x double>, <2 x double>* %a, align 8
ret <2 x double> %v ret <2 x double> %v
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test/CodeGen/PowerPC/vsx-recip-est.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -enable-unsafe-fp-math | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-unsafe-fp-math | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -enable-unsafe-fp-math | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
; RUN: -enable-unsafe-fp-math | FileCheck %s
@a = global float 3.000000e+00, align 4 @a = global float 3.000000e+00, align 4
@b = global float 4.000000e+00, align 4 @b = global float 4.000000e+00, align 4
@c = global double 3.000000e+00, align 8 @c = global double 3.000000e+00, align 8
@d = global double 4.000000e+00, align 8 @d = global double 4.000000e+00, align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define float @emit_xsresp() { define float @emit_xsresp() {
entry: entry:
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test/CodeGen/PowerPC/vsx-spill.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck \ ; RUN: -mattr=+vsx < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -mattr=+vsx < %s | FileCheck \
; RUN: -check-prefix=CHECK-REG %s ; RUN: -check-prefix=CHECK-REG %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -mattr=+vsx -fast-isel -O0 < %s | \
; RUN: FileCheck %s ; RUN: FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -mattr=+vsx -fast-isel -O0 < %s | \
; RUN: FileCheck -check-prefix=CHECK-FISL %s ; RUN: FileCheck -check-prefix=CHECK-FISL %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr9 < %s \
; RUN: | FileCheck \
; RUN: -check-prefix=CHECK-P9-REG %s ; RUN: -check-prefix=CHECK-P9-REG %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 < %s | FileCheck \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr9 \
; RUN: -fast-isel -O0 < %s | FileCheck \
; RUN: -check-prefix=CHECK-P9-FISL %s ; RUN: -check-prefix=CHECK-P9-FISL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define double @foo1(double %a) nounwind { define double @foo1(double %a) nounwind {
entry: entry:
call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
br label %return br label %return
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test/CodeGen/PowerPC/vsx-word-splats.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr7 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-BE ; RUN: --check-prefix=CHECK-BE
define <4 x float> @test0f(<4 x float> %a) { define <4 x float> @test0f(<4 x float> %a) {
entry: entry:
%0 = bitcast <4 x float> %a to <16 x i8> %0 = bitcast <4 x float> %a to <16 x i8>
%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%2 = bitcast <16 x i8> %1 to <4 x float> %2 = bitcast <16 x i8> %1 to <4 x float>
ret <4 x float> %2 ret <4 x float> %2
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test/CodeGen/PowerPC/vsx.ll

; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s ; RUN: -verify-machineinstrs -mcpu=pwr7 \
; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s
; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s ; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s ; RUN: -verify-machineinstrs -mcpu=pwr7 \
; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
; RUN: llc -ppc-strip-register-prefix -relocation-model=static \
; RUN: -verify-machineinstrs -mcpu=pwr8 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s \
; RUN: | FileCheck -check-prefix=CHECK-LE %s
define double @test1(double %a, double %b) { define double @test1(double %a, double %b) {
entry: entry:
%v = fmul double %a, %b %v = fmul double %a, %b
ret double %v ret double %v
; CHECK-LABEL: @test1 ; CHECK-LABEL: @test1
; CHECK: xsmuldp 1, 1, 2 ; CHECK: xsmuldp 1, 1, 2
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test/CodeGen/PowerPC/vsxD-Form-spills.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-PWR9 %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -ppc-strip-register-prefix \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s \
; RUN: | FileCheck -check-prefix=CHECK-PWR9 %s
define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: testSpill: ; CHECK-LABEL: testSpill:
; CHECK: li 11, 80 ; CHECK: li 11, 80
; CHECK: li 12, 96 ; CHECK: li 12, 96
; CHECK: li 3, 48 ; CHECK: li 3, 48
; CHECK: li 10, 64 ; CHECK: li 10, 64
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test/CodeGen/PowerPC/vsx_insert_extract_le.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr8 \
; RUN: -mattr=+vsx \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr9 \
; RUN: -mattr=-power9-vector \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr9 \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-P9 --implicit-check-not xxswapd ; RUN: --check-prefix=CHECK-P9 --implicit-check-not xxswapd
define <2 x double> @testi0(<2 x double>* %p1, double* %p2) { define <2 x double> @testi0(<2 x double>* %p1, double* %p2) {
%v = load <2 x double>, <2 x double>* %p1 %v = load <2 x double>, <2 x double>* %p1
%s = load double, double* %p2 %s = load double, double* %p2
%r = insertelement <2 x double> %v, double %s, i32 0 %r = insertelement <2 x double> %v, double %s, i32 0
ret <2 x double> %r ret <2 x double> %r
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test/CodeGen/PowerPC/vsx_scalar_ld_st.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9 ; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9
@d = common global double 0.000000e+00, align 8 @d = common global double 0.000000e+00, align 8
@f = common global float 0.000000e+00, align 4 @f = common global float 0.000000e+00, align 4
@i = common global i32 0, align 4 @i = common global i32 0, align 4
@ui = common global i32 0, align 4 @ui = common global i32 0, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
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test/CodeGen/PowerPC/vsx_shuffle_le.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr8 \
; RUN: -mattr=+vsx \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr9 \
; RUN: -mattr=-power9-vector \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx \ ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs -mcpu=pwr9 \
; RUN: -mattr=+vsx \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-P9 --implicit-check-not xxswapd ; RUN: --check-prefix=CHECK-P9 --implicit-check-not xxswapd
define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) { define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) {
%v1 = load <2 x double>, <2 x double>* %p1 %v1 = load <2 x double>, <2 x double>* %p1
%v2 = load <2 x double>, <2 x double>* %p2 %v2 = load <2 x double>, <2 x double>* %p2
%v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 0> %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 0>
ret <2 x double> %v3 ret <2 x double> %v3
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test/CodeGen/PowerPC/xray-attribute-instrumentation.ll

; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -filetype=asm -o - \
; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -filetype=asm -o - \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -relocation-model=pic < %s | FileCheck %s ; RUN: -relocation-model=pic < %s | FileCheck %s
define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" { define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK-LABEL: .Ltmp0: ; CHECK-LABEL: .Ltmp0:
; CHECK: b .Ltmp1 ; CHECK: b .Ltmp1
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1) ; CHECK-NEXT: std 0, -8(1)
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
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test/CodeGen/PowerPC/xray-conditional-return.ll

; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -filetype=asm -o - \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
define void @Foo(i32 signext %a, i32 signext %b) #0 { define void @Foo(i32 signext %a, i32 signext %b) #0 {
; CHECK-LABEL: @Foo ; CHECK-LABEL: @Foo
; CHECK: cmpw [[CR:[0-9]+]] ; CHECK: cmpw [[CR:[0-9]+]]
; CHECK-NEXT: ble [[CR]], [[LABEL:\.[a-zA-Z0-9]+]] ; CHECK-NEXT: ble [[CR]], [[LABEL:\.[a-zA-Z0-9]+]]
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: ; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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test/CodeGen/PowerPC/xray-ret-is-terminator.ll

; RUN: llc -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -o - \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
define void @ILLBeBack() #0 { define void @ILLBeBack() #0 {
; CHECK-LABEL @ILLBeBack ; CHECK-LABEL @ILLBeBack
; CHECK: beq {{[0-9]+}}, [[LABEL:\.[a-zA-Z0-9_]+]] ; CHECK: beq {{[0-9]+}}, [[LABEL:\.[a-zA-Z0-9_]+]]
; CHECK: bl __xray_FunctionExit ; CHECK: bl __xray_FunctionExit
; CHECK: [[LABEL]]: ; CHECK: [[LABEL]]:
bb: bb:
br i1 undef, label %bb1, label %bb8 br i1 undef, label %bb1, label %bb8
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test/CodeGen/PowerPC/xray-tail-call-hidden.ll

; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -filetype=asm -o - \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
declare hidden i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" declare hidden i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always"
define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" { define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK-LABEL: .Ltmp0: ; CHECK-LABEL: .Ltmp0:
; CHECK: b .Ltmp1 ; CHECK: b .Ltmp1
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1) ; CHECK-NEXT: std 0, -8(1)
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test/CodeGen/PowerPC/xray-tail-call-sled.ll

; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -filetype=asm -o - \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" { define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK-LABEL: .Ltmp0: ; CHECK-LABEL: .Ltmp0:
; CHECK: b .Ltmp1 ; CHECK: b .Ltmp1
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: std 0, -8(1) ; CHECK-NEXT: std 0, -8(1)
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: bl __xray_FunctionEntry ; CHECK-NEXT: bl __xray_FunctionEntry
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test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll

; Check the miscellaneous logical vector operations added in P8 ; Check the miscellaneous logical vector operations added in P8
; ;
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; Test x eqv y ; Test x eqv y
define <4 x i32> @test_xxleqv(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @test_xxleqv(<4 x i32> %x, <4 x i32> %y) nounwind {
%tmp = xor <4 x i32> %x, %y %tmp = xor <4 x i32> %x, %y
%ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1> %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %ret_val ret <4 x i32> %ret_val
; CHECK: xxleqv 34, 34, 35 ; CHECK: xxleqv 34, 34, 35
} }
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test/CodeGen/PowerPC/zext-bitperm.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s ; RUN: -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s ; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
; RUN: llc -ppc-strip-register-prefix -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
; Test case for PPCTargetLowering::extendSubTreeForBitPermutation. ; Test case for PPCTargetLowering::extendSubTreeForBitPermutation.
; We expect mask and rotate are folded into a rlwinm instruction. ; We expect mask and rotate are folded into a rlwinm instruction.
define zeroext i32 @func(i32* %p, i32 zeroext %i) { define zeroext i32 @func(i32* %p, i32 zeroext %i) {
; CHECK-LABEL: @func ; CHECK-LABEL: @func
; CHECK: addi [[REG1:[0-9]+]], 4, 1 ; CHECK: addi [[REG1:[0-9]+]], 4, 1
; CHECK: rlwinm [[REG2:[0-9]+]], [[REG1]], 2, 22, 29 ; CHECK: rlwinm [[REG2:[0-9]+]], [[REG1]], 2, 22, 29
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test/MC/Disassembler/PowerPC/qpx.txt

# RUN: llvm-mc --disassemble %s -triple powerpc64-bgq-linux -mcpu=a2q | FileCheck %s # RUN: llvm-mc -ppc-strip-register-prefix --disassemble %s \
; RUN: -triple powerpc64-bgq-linux -mcpu=a2q | FileCheck %s
# CHECK: qvfabs 3, 5 # CHECK: qvfabs 3, 5
0x10 0x60 0x2a 0x10 0x10 0x60 0x2a 0x10
# CHECK: qvfadd 3, 4, 5 # CHECK: qvfadd 3, 4, 5
0x10 0x64 0x28 0x2a 0x10 0x64 0x28 0x2a
# CHECK: qvfadds 3, 4, 5 # CHECK: qvfadds 3, 4, 5
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test/MC/Disassembler/PowerPC/vsx.txt

# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s # RUN: llvm-mc -ppc-strip-register-prefix --disassemble %s \
; RUN: -triple powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
# CHECK: lxsdx 7, 5, 31 # CHECK: lxsdx 7, 5, 31
0x7c 0xe5 0xfc 0x98 0x7c 0xe5 0xfc 0x98
# CHECK: lxsiwax 7, 5, 31 # CHECK: lxsiwax 7, 5, 31
0x7c 0xe5 0xf8 0x98 0x7c 0xe5 0xf8 0x98
# CHECK: lxsiwzx 7, 5, 31 # CHECK: lxsiwzx 7, 5, 31
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test/MC/PowerPC/deprecated-p7.s

# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu -mcpu=pwr7 -show-encoding < %s 2>&1 | FileCheck %s # RUN: llvm-mc -ppc-strip-register-prefix -triple powerpc64-unknown-linux-gnu \
# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu -mcpu=pwr7 -show-encoding < %s 2>&1 | FileCheck %s # RUN: -mcpu=pwr7 -show-encoding < %s 2>&1 | FileCheck %s
# RUN: llvm-mc -triple powerpc-unknown-linux-gnu -mcpu=601 -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-OLD %s # RUN: llvm-mc -ppc-strip-register-prefix \
# RUN: -triple powerpc64le-unknown-linux-gnu -mcpu=pwr7 \
# RUN: -show-encoding < %s 2>&1 | FileCheck %s
# RUN: llvm-mc -ppc-strip-register-prefix \
# RUN: -triple powerpc-unknown-linux-gnu -mcpu=601 -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-OLD %s
mftb 3 mftb 3
# CHECK-NOT: warning: deprecated # CHECK-NOT: warning: deprecated
# CHECK: mfspr 3, 268 # CHECK: mfspr 3, 268
# CHECK-OLD-NOT: warning: deprecated # CHECK-OLD-NOT: warning: deprecated
# CHECK-OLD: mftb 3 # CHECK-OLD: mftb 3
# FIXME: Test dst and friends once we can parse them. # FIXME: Test dst and friends once we can parse them.

test/MC/PowerPC/htm.s

# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s # RUN: llvm-mc -ppc-strip-register-prefix -triple powerpc64-unknown-linux-gnu \
# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # RUN: --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
# RUN: llvm-mc -ppc-strip-register-prefix \
# RUN: -triple powerpc64le-unknown-linux-gnu \
# RUN: --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
# CHECK-BE: tbegin. 0 # encoding: [0x7c,0x00,0x05,0x1d] # CHECK-BE: tbegin. 0 # encoding: [0x7c,0x00,0x05,0x1d]
# CHECK-LE: tbegin. 0 # encoding: [0x1d,0x05,0x00,0x7c] # CHECK-LE: tbegin. 0 # encoding: [0x1d,0x05,0x00,0x7c]
tbegin. 0 tbegin. 0
# CHECK-BE: tbegin. 1 # encoding: [0x7c,0x20,0x05,0x1d] # CHECK-BE: tbegin. 1 # encoding: [0x7c,0x20,0x05,0x1d]
# CHECK-LE: tbegin. 1 # encoding: [0x1d,0x05,0x20,0x7c] # CHECK-LE: tbegin. 1 # encoding: [0x1d,0x05,0x20,0x7c]
tbegin. 1 tbegin. 1
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test/MC/PowerPC/qpx.s

# RUN: llvm-mc -triple powerpc64-bgq-linux --show-encoding %s | FileCheck %s # RUN: llvm-mc -ppc-strip-register-prefix -triple powerpc64-bgq-linux \
# RUN: --show-encoding %s | FileCheck %s
# CHECK: qvfabs 3, 5 # encoding: [0x10,0x60,0x2a,0x10] # CHECK: qvfabs 3, 5 # encoding: [0x10,0x60,0x2a,0x10]
qvfabs %q3, %q5 qvfabs %q3, %q5
# CHECK: qvfabs 3, 5 # encoding: [0x10,0x60,0x2a,0x10] # CHECK: qvfabs 3, 5 # encoding: [0x10,0x60,0x2a,0x10]
qvfabs 3, 5 qvfabs 3, 5
# CHECK: qvfadd 3, 4, 5 # encoding: [0x10,0x64,0x28,0x2a] # CHECK: qvfadd 3, 4, 5 # encoding: [0x10,0x64,0x28,0x2a]
qvfadd 3, 4, 5 qvfadd 3, 4, 5
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test/MC/PowerPC/vsx.s

# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s # RUN: llvm-mc -ppc-strip-register-prefix -triple powerpc64-unknown-linux-gnu \
# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # RUN: --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
# RUN: llvm-mc -ppc-strip-register-prefix \
# RUN: -triple powerpc64le-unknown-linux-gnu --show-encoding %s \
# RUN: | FileCheck -check-prefix=CHECK-LE %s
# CHECK-BE: xxswapd 7, 63 # encoding: [0xf0,0xff,0xfa,0x56] # CHECK-BE: xxswapd 7, 63 # encoding: [0xf0,0xff,0xfa,0x56]
# CHECK-LE: xxswapd 7, 63 # encoding: [0x56,0xfa,0xff,0xf0] # CHECK-LE: xxswapd 7, 63 # encoding: [0x56,0xfa,0xff,0xf0]
xxswapd %vs7, %vs63 xxswapd %vs7, %vs63
# CHECK-BE: lxsdx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x99] # CHECK-BE: lxsdx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x99]
# CHECK-LE: lxsdx 39, 5, 31 # encoding: [0x99,0xfc,0xe5,0x7c] # CHECK-LE: lxsdx 39, 5, 31 # encoding: [0x99,0xfc,0xe5,0x7c]
lxsdx 39, 5, 31 lxsdx 39, 5, 31
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