Utilize DQ-Form instructions for spill/restore and fix FrameIndex elimination to only use `lis/addi` if necessary

[lei]

Summary

Currently we produce a bunch of unnecessary code when emitting the prologue/epilogue for spills/restores.
Namely, if the load from stack slot/store to stack slot instruction is an X-Form instruction, we will
always produce an LIS/ORI sequence for the stack offset.

Furthermore, we have not exploited the P9 vector D-Form loads/stores for this purpose.

This patch will address both issues.

Specifying the D-Form load as the instruction to use for stack spills/reloads should be safe because:

1. The stack should be aligned according to the ABI
2. If the stack isn't aligned, PPCRegisterInfo::eliminateFrameIndex() will check for the offset being a multiple of 16 and will convert it to an X-Form instruction if it isn't.

SPEC2017 performance run was done but none of the benchmarks showed any significant improvement.

	       SPEED UP
	       Baseline/new
SPEC_INT	
500.perlbench_r	1.00
502.gcc_r	1.00
505.mcf_r	0.99
523.xalancbmk_r	1.00
525.x264_r	1.01
531.deepsjeng_r	1.00
541.leela_r	1.00
557.xz_r	1.00
	
SPEC_FP	
508.namd_r	1.00
511.povray_r	1.00
519.lbm_r	1.00
538.imagick_r	1.00
544.nab_r	1.00

[echristo]

Code generation looks a lot more reasonable. Can you commit the change to test/CodeGen/PowerPC/sjlj.ll separately?

[lei]

In D38758#894109, @echristo wrote:

Code generation looks a lot more reasonable. Can you commit the change to test/CodeGen/PowerPC/sjlj.ll separately?

NFC patch committed for test/CodeGen/PowerPC/sjlj.ll: rL315482

[lei]

Commit rL315500: [PowerPC] Utilize DQ-Form instructions for spill/restore and fix FrameIndex elimination to only use lis/addi if necessary.

lib/Target/PowerPC/PPCInstrInfo.cpp

unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   case PPC::LD:
   case PPC::LWZ:
   case PPC::LFS:
   case PPC::LFD:
   case PPC::RESTORE_CR:
   case PPC::RESTORE_CRBIT:
   case PPC::LVX:
   case PPC::LXVD2X:
-  case PPC::LXVX:
+  case PPC::LXV:
   case PPC::QVLFDX:
   case PPC::QVLFSXs:
   case PPC::QVLFDXb:
   case PPC::RESTORE_VRSAVE:
   case PPC::SPILLTOVSR_LD:
     // Check for the operands added by addFrameReference (the immediate is the
     // offset which defaults to 0).
     if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
   case PPC::STD:
   case PPC::STW:
   case PPC::STFS:
   case PPC::STFD:
   case PPC::SPILL_CR:
   case PPC::SPILL_CRBIT:
   case PPC::STVX:
   case PPC::STXVD2X:
-  case PPC::STXVX:
+  case PPC::STXV:
   case PPC::QVSTFDX:
   case PPC::QVSTFSXs:
   case PPC::QVSTFDXb:
   case PPC::SPILL_VRSAVE:
   case PPC::SPILLTOVSR_ST:
     // Check for the operands added by addFrameReference (the immediate is the
     // offset which defaults to 0).
     if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
     return true;
   } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
                                        .addReg(SrcReg,
                                                getKillRegState(isKill)),
                                        FrameIdx));
     NonRI = true;
   } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
-    unsigned Op = Subtarget.hasP9Vector() ? PPC::STXVX : PPC::STXVD2X;
+    unsigned Op = Subtarget.hasP9Vector() ? PPC::STXV : PPC::STXVD2X;
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op))
                                        .addReg(SrcReg,
                                                getKillRegState(isKill)),
                                        FrameIdx));
     NonRI = true;
   } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
     unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX;
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
                                                get(PPC::RESTORE_CRBIT), DestReg),
                                        FrameIdx));
     return true;
   } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
                                        FrameIdx));
     NonRI = true;
   } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
-    unsigned Op = Subtarget.hasP9Vector() ? PPC::LXVX : PPC::LXVD2X;
+    unsigned Op = Subtarget.hasP9Vector() ? PPC::LXV : PPC::LXVD2X;
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op), DestReg),
                                        FrameIdx));
     NonRI = true;
   } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
     unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf64 : PPC::LXSDX;
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
                                                DestReg), FrameIdx));
     NonRI = true;

lib/Target/PowerPC/PPCRegisterInfo.cpp

PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   bool is64Bit = TM.isPPC64();
   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
   const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
   unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
            SReg = MF.getRegInfo().createVirtualRegister(RC);
 
   // Insert a set of rA with the full offset value before the ld, st, or add
+  if (isInt<16>(Offset)) 
+    BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
+      .addImm(Offset);
+  else {
     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
       .addImm(Offset >> 16);
     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
       .addReg(SRegHi, RegState::Kill)
       .addImm(Offset);
+  }
 
   // Convert into indexed form of the instruction:
   //
   //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
   //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
   unsigned OperandBase;
 
   if (noImmForm)

test/CodeGen/PowerPC/fast-isel-conversion.ll

 ; FIXME: FastISel currently returns false if it hits code that uses VSX
 ; registers and with -fast-isel-abort=1 turned on the test case will then fail.
 ; When fastisel better supports VSX fix up this test case.
 ;
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s --check-prefix=ELF64LE
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s
 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
 
 ;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
 ;; to SelectionDAG in some cases.
 
 ; Test sitofp
 
 define void @sitofp_single_i64(i64 %a, float %b) nounwind {
 entry:
-; ELF64: sitofp_single_i64
-; ELF64LE: sitofp_single_i64
+; CHECK: sitofp_single_i64
 ; PPC970: sitofp_single_i64
   %b.addr = alloca float, align 4
   %conv = sitofp i64 %a to float
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfids
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfids
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfids
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
 ; PPC970: frsp
   store float %conv, float* %b.addr, align 4
   ret void
 }
 
 define void @sitofp_single_i32(i32 %a, float %b) nounwind {
 entry:
-; ELF64: sitofp_single_i32
-; ELF64LE: sitofp_single_i32
+; CHECK: sitofp_single_i32
 ; PPC970: sitofp_single_i32
   %b.addr = alloca float, align 4
   %conv = sitofp i32 %a to float
-; ELF64: std
-; stack offset used to load the float: 65524 = -16 + 4
-; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524 
-; ELF64: lfiwax
-; ELF64: fcfids
-; ELF64LE: std
-; stack offset used to load the float: 65520 = -16 + 0
-; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
-; ELF64LE: lfiwax
-; ELF64LE: fcfids
+; CHECK: std
+; CHECK-NEXT: li
+; CHECK-NEXT: lfiwax
+; CHECK-NEXT: fcfids
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
 ; PPC970: frsp
   store float %conv, float* %b.addr, align 4
   ret void
 }
 
 define void @sitofp_single_i16(i16 %a, float %b) nounwind {
 entry:
-; ELF64: sitofp_single_i16
-; ELF64LE: sitofp_single_i16
+; CHECK: sitofp_single_i16
 ; PPC970: sitofp_single_i16
   %b.addr = alloca float, align 4
   %conv = sitofp i16 %a to float
-; ELF64: extsh
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfids
-; ELF64LE: extsh
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfids
+; CHECK: extsh
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfids
 ; PPC970: extsh
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
 ; PPC970: frsp
   store float %conv, float* %b.addr, align 4
   ret void
 }
 
 define void @sitofp_single_i8(i8 %a) nounwind {
 entry:
-; ELF64: sitofp_single_i8
-; ELF64LE: sitofp_single_i8
+; CHECK: sitofp_single_i8
 ; PPC970: sitofp_single_i8
   %b.addr = alloca float, align 4
   %conv = sitofp i8 %a to float
-; ELF64: extsb
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfids
-; ELF64LE: extsb
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfids
+; CHECK: extsb
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfids
 ; PPC970: extsb
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
 ; PPC970: frsp
   store float %conv, float* %b.addr, align 4
   ret void
 }
 
 define void @sitofp_double_i32(i32 %a, double %b) nounwind {
 entry:
-; ELF64: sitofp_double_i32
-; ELF64LE: sitofp_double_i32
+; CHECK: sitofp_double_i32
 ; PPC970: sitofp_double_i32
   %b.addr = alloca double, align 8
   %conv = sitofp i32 %a to double
-; ELF64: std
-; stack offset used to load the float: 65524 = -16 + 4
-; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
-; ELF64: lfiwax
-; ELF64: fcfid
-; ELF64LE: std
-; stack offset used to load the float: 65520 = -16 + 0
-; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
-; ELF64LE: lfiwax
-; ELF64LE: fcfid
+; CHECK: std
+; CHECK-NOT: ori
+; CHECK: li
+; CHECK-NOT: ori
+; CHECK: lfiwax
+; CHECK: fcfid
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
   store double %conv, double* %b.addr, align 8
   ret void
 }
 
 define void @sitofp_double_i64(i64 %a, double %b) nounwind {
 entry:
-; ELF64: sitofp_double_i64
-; ELF64LE: sitofp_double_i64
+; CHECK: sitofp_double_i64
 ; PPC970: sitofp_double_i64
   %b.addr = alloca double, align 8
   %conv = sitofp i64 %a to double
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfid
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfid
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfid
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
   store double %conv, double* %b.addr, align 8
   ret void
 }
 
 define void @sitofp_double_i16(i16 %a, double %b) nounwind {
 entry:
-; ELF64: sitofp_double_i16
-; ELF64LE: sitofp_double_i16
+; CHECK: sitofp_double_i16
 ; PPC970: sitofp_double_i16
   %b.addr = alloca double, align 8
   %conv = sitofp i16 %a to double
-; ELF64: extsh
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfid
-; ELF64LE: extsh
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfid
+; CHECK: extsh
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfid
 ; PPC970: extsh
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
   store double %conv, double* %b.addr, align 8
   ret void
 }
 
 define void @sitofp_double_i8(i8 %a, double %b) nounwind {
 entry:
-; ELF64: sitofp_double_i8
-; ELF64LE: sitofp_double_i8
+; CHECK: sitofp_double_i8
 ; PPC970: sitofp_double_i8
   %b.addr = alloca double, align 8
   %conv = sitofp i8 %a to double
-; ELF64: extsb
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfid
-; ELF64LE: extsb
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfid
+; CHECK: extsb
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfid
 ; PPC970: extsb
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
   store double %conv, double* %b.addr, align 8
   ret void
 }
 
 ; Test uitofp
 
 define void @uitofp_single_i64(i64 %a, float %b) nounwind {
 entry:
-; ELF64: uitofp_single_i64
-; ELF64LE: uitofp_single_i64
+; CHECK: uitofp_single_i64
 ; PPC970: uitofp_single_i64
   %b.addr = alloca float, align 4
   %conv = uitofp i64 %a to float
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfidus
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfidus
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfidus
 ; PPC970-NOT: fcfidus
   store float %conv, float* %b.addr, align 4
   ret void
 }
 
 define void @uitofp_single_i32(i32 %a, float %b) nounwind {
 entry:
-; ELF64: uitofp_single_i32
-; ELF64LE: uitofp_single_i32
+; CHECK: uitofp_single_i32
 ; PPC970: uitofp_single_i32
   %b.addr = alloca float, align 4
   %conv = uitofp i32 %a to float
-; ELF64: std
-; stack offset used to load the float: 65524 = -16 + 4
-; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
-; ELF64: lfiwzx
-; ELF64: fcfidus
-; ELF64LE: std
-; stack offset used to load the float: 65520 = -16 + 0
-; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
-; ELF64LE: lfiwzx
-; ELF64LE: fcfidus
+; CHECK: std
+; CHECK-NOT: ori
+; CHECK: li
+; CHECK-NOT: ori
+; CHECK: lfiwzx
+; CHECK: fcfidus
 ; PPC970-NOT: lfiwzx
 ; PPC970-NOT: fcfidus
   store float %conv, float* %b.addr, align 4
   ret void
 }
 
 define void @uitofp_single_i16(i16 %a, float %b) nounwind {
 entry:
-; ELF64: uitofp_single_i16
-; ELF64LE: uitofp_single_i16
+; CHECK: uitofp_single_i16
 ; PPC970: uitofp_single_i16
   %b.addr = alloca float, align 4
   %conv = uitofp i16 %a to float
-; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfidus
-; ELF64LE: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfidus
+; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfidus
 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
 ; PPC970: frsp
   store float %conv, float* %b.addr, align 4
   ret void
 }
 
 define void @uitofp_single_i8(i8 %a) nounwind {
 entry:
-; ELF64: uitofp_single_i8
-; ELF64LE: uitofp_single_i8
+; CHECK: uitofp_single_i8
 ; PPC970: uitofp_single_i8
   %b.addr = alloca float, align 4
   %conv = uitofp i8 %a to float
-; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfidus
-; ELF64LE: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfidus
+; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfidus
 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
 ; PPC970: frsp
   store float %conv, float* %b.addr, align 4
   ret void
 }
 
 define void @uitofp_double_i64(i64 %a, double %b) nounwind {
 entry:
-; ELF64: uitofp_double_i64
-; ELF64LE: uitofp_double_i64
+; CHECK: uitofp_double_i64
 ; PPC970: uitofp_double_i64
   %b.addr = alloca double, align 8
   %conv = uitofp i64 %a to double
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfidu
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfidu
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfidu
 ; PPC970-NOT: fcfidu
   store double %conv, double* %b.addr, align 8
   ret void
 }
 
 define void @uitofp_double_i32(i32 %a, double %b) nounwind {
 entry:
-; ELF64: uitofp_double_i32
-; ELF64LE: uitofp_double_i32
+; CHECK: uitofp_double_i32
 ; PPC970: uitofp_double_i32
   %b.addr = alloca double, align 8
   %conv = uitofp i32 %a to double
-; ELF64: std
-; stack offset used to load the float: 65524 = -16 + 4
-; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
-; ELF64: lfiwzx
-; ELF64: fcfidu
-; ELF64LE: std
-; stack offset used to load the float: 65520 = -16 + 0
-; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
-; ELF64LE: lfiwzx
-; ELF64LE: fcfidu
+; CHECK: std
+; CHECK-NEXT: li
+; CHECK-NEXT: lfiwzx
+; CHECK-NEXT: fcfidu
+; CHECKLE: fcfidu
 ; PPC970-NOT: lfiwzx
 ; PPC970-NOT: fcfidu
   store double %conv, double* %b.addr, align 8
   ret void
 }
 
 define void @uitofp_double_i16(i16 %a, double %b) nounwind {
 entry:
-; ELF64: uitofp_double_i16
-; ELF64LE: uitofp_double_i16
+; CHECK: uitofp_double_i16
 ; PPC970: uitofp_double_i16
   %b.addr = alloca double, align 8
   %conv = uitofp i16 %a to double
-; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfidu
-; ELF64LE: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfidu
+; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfidu
 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
   store double %conv, double* %b.addr, align 8
   ret void
 }
 
 define void @uitofp_double_i8(i8 %a, double %b) nounwind {
 entry:
-; ELF64: uitofp_double_i8
-; ELF64LE: uitofp_double_i8
+; CHECK: uitofp_double_i8
 ; PPC970: uitofp_double_i8
   %b.addr = alloca double, align 8
   %conv = uitofp i8 %a to double
-; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
-; ELF64: std
-; ELF64: lfd
-; ELF64: fcfidu
-; ELF64LE: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
-; ELF64LE: std
-; ELF64LE: lfd
-; ELF64LE: fcfidu
+; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
+; CHECK: std
+; CHECK: lfd
+; CHECK: fcfidu
 ; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
 ; PPC970: std
 ; PPC970: lfd
 ; PPC970: fcfid
   store double %conv, double* %b.addr, align 8
   ret void
 }
 
 ; Test fptosi
 
 define void @fptosi_float_i32(float %a) nounwind {
 entry:
-; ELF64: fptosi_float_i32
-; ELF64LE: fptosi_float_i32
+; CHECK: fptosi_float_i32
 ; PPC970: fptosi_float_i32
   %b.addr = alloca i32, align 4
   %conv = fptosi float %a to i32
-; ELF64: fctiwz
-; ELF64: stfd
-; ELF64: lwa
-; ELF64LE: fctiwz
-; ELF64LE: stfd
-; ELF64LE: lwa
+; CHECK: fctiwz
+; CHECK: stfd
+; CHECK: lwa
 ; PPC970: fctiwz
 ; PPC970: stfd
 ; PPC970: lwa
   store i32 %conv, i32* %b.addr, align 4
   ret void
 }
 
 define void @fptosi_float_i64(float %a) nounwind {
 entry:
-; ELF64: fptosi_float_i64
-; ELF64LE: fptosi_float_i64
+; CHECK: fptosi_float_i64
 ; PPC970: fptosi_float_i64
   %b.addr = alloca i64, align 4
   %conv = fptosi float %a to i64
-; ELF64: fctidz
-; ELF64: stfd
-; ELF64: ld
-; ELF64LE: fctidz
-; ELF64LE: stfd
-; ELF64LE: ld
+; CHECK: fctidz
+; CHECK: stfd
+; CHECK: ld
 ; PPC970: fctidz
 ; PPC970: stfd
 ; PPC970: ld
   store i64 %conv, i64* %b.addr, align 4
   ret void
 }
 
 define void @fptosi_double_i32(double %a) nounwind {
 entry:
-; ELF64: fptosi_double_i32
-; ELF64LE: fptosi_double_i32
+; CHECK: fptosi_double_i32
 ; PPC970: fptosi_double_i32
   %b.addr = alloca i32, align 8
   %conv = fptosi double %a to i32
-; ELF64: fctiwz
-; ELF64: stfd
-; ELF64: lwa
-; ELF64LE: fctiwz
-; ELF64LE: stfd
-; ELF64LE: lwa
+; CHECK: fctiwz
+; CHECK: stfd
+; CHECK: lwa
 ; PPC970: fctiwz
 ; PPC970: stfd
 ; PPC970: lwa
   store i32 %conv, i32* %b.addr, align 8
   ret void
 }
 
 define void @fptosi_double_i64(double %a) nounwind {
 entry:
-; ELF64: fptosi_double_i64
-; ELF64LE: fptosi_double_i64
+; CHECK: fptosi_double_i64
 ; PPC970: fptosi_double_i64
   %b.addr = alloca i64, align 8
   %conv = fptosi double %a to i64
-; ELF64: fctidz
-; ELF64: stfd
-; ELF64: ld
-; ELF64LE: fctidz
-; ELF64LE: stfd
-; ELF64LE: ld
+; CHECK: fctidz
+; CHECK: stfd
+; CHECK: ld
 ; PPC970: fctidz
 ; PPC970: stfd
 ; PPC970: ld
   store i64 %conv, i64* %b.addr, align 8
   ret void
 }
 
 ; Test fptoui
 
 define void @fptoui_float_i32(float %a) nounwind {
 entry:
-; ELF64: fptoui_float_i32
-; ELF64LE: fptoui_float_i32
+; CHECK: fptoui_float_i32
 ; PPC970: fptoui_float_i32
   %b.addr = alloca i32, align 4
   %conv = fptoui float %a to i32
-; ELF64: fctiwuz
-; ELF64: stfd
-; ELF64: lwz
-; ELF64LE: fctiwuz
-; ELF64LE: stfd
-; ELF64LE: lwz
+; CHECK: fctiwuz
+; CHECK: stfd
+; CHECK: lwz
 ; PPC970: fctidz
 ; PPC970: stfd
 ; PPC970: lwz
   store i32 %conv, i32* %b.addr, align 4
   ret void
 }
 
 define void @fptoui_float_i64(float %a) nounwind {
 entry:
-; ELF64: fptoui_float_i64
-; ELF64LE: fptoui_float_i64
+; CHECK: fptoui_float_i64
 ; PPC970: fptoui_float_i64
   %b.addr = alloca i64, align 4
   %conv = fptoui float %a to i64
-; ELF64: fctiduz
-; ELF64: stfd
-; ELF64: ld
-; ELF64LE: fctiduz
-; ELF64LE: stfd
-; ELF64LE: ld
+; CHECK: fctiduz
+; CHECK: stfd
+; CHECK: ld
 ; PPC970-NOT: fctiduz
   store i64 %conv, i64* %b.addr, align 4
   ret void
 }
 
 define void @fptoui_double_i32(double %a) nounwind {
 entry:
-; ELF64: fptoui_double_i32
-; ELF64LE: fptoui_double_i32
+; CHECK: fptoui_double_i32
 ; PPC970: fptoui_double_i32
   %b.addr = alloca i32, align 8
   %conv = fptoui double %a to i32
-; ELF64: fctiwuz
-; ELF64: stfd
-; ELF64: lwz
-; ELF64LE: fctiwuz
-; ELF64LE: stfd
-; ELF64LE: lwz
+; CHECK: fctiwuz
+; CHECK: stfd
+; CHECK: lwz
 ; PPC970: fctidz
 ; PPC970: stfd
 ; PPC970: lwz
   store i32 %conv, i32* %b.addr, align 8
   ret void
 }
 
 define void @fptoui_double_i64(double %a) nounwind {
 entry:
-; ELF64: fptoui_double_i64
-; ELF64LE: fptoui_double_i64
+; CHECK: fptoui_double_i64
 ; PPC970: fptoui_double_i64
   %b.addr = alloca i64, align 8
   %conv = fptoui double %a to i64
-; ELF64: fctiduz
-; ELF64: stfd
-; ELF64: ld
-; ELF64LE: fctiduz
-; ELF64LE: stfd
-; ELF64LE: ld
+; CHECK: fctiduz
+; CHECK: stfd
+; CHECK: ld
 ; PPC970-NOT: fctiduz
   store i64 %conv, i64* %b.addr, align 8
   ret void
 }

test/CodeGen/PowerPC/sjlj.ll

if.end:                                           ; preds = %if.else
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
   %3 = load i32, i32* %retval
   ret i32 %3
 
 ; FIXME: We should be saving VRSAVE on Darwin, but we're not!
 
-; CHECK: @main
+; CHECK-LABEL: main:
 ; CHECK: std
 ; Make sure that we're not saving VRSAVE on non-Darwin:
 ; CHECK-NOT: mfspr
 
 ; CHECK-DAG: stfd
 ; CHECK-DAG: stxvd2x
 
 ; CHECK-DAG: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha

 ; CHECK: .LBB1_3:
 ; CHECK: mflr [[REGL:[0-9]+]]
 ; CHECK: ld [[REG2:[0-9]+]], [[OFF]](31)                   # 8-byte Folded Reload
 ; CHECK: std [[REGL]], 8([[REG2]])
 ; CHECK: li 3, 0
 
 ; CHECK: .LBB1_5:
 
-; CHECK: lfd
-; CHECK: lxvd2x
+; CHECK-DAG: lfd
+; CHECK-DAG: lxvd2x
 ; CHECK: ld
 ; CHECK: blr
 
-; CHECK-NOAV: @main
+; CHECK-NOAV-LABEL: main:
 ; CHECK-NOAV-NOT: stxvd2x
 ; CHECK-NOAV: bcl
 ; CHECK-NOAV: mflr
 ; CHECK-NOAV: bl foo
 ; CHECK-NOAV-NOT: lxvd2x
 ; CHECK-NOAV: blr
 }
 

 if.end:                                           ; preds = %if.else
   store i32 0, i32* %retval
   br label %return
 
 return:                                           ; preds = %if.end, %if.then
   %3 = load i32, i32* %retval
   ret i32 %3
 
-; CHECK: @main2
+; CHECK-LABEL: main2:
 
 ; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha
 ; CHECK-DAG: std 31, env_sigill@toc@l([[REG]])
 ; CHECK-DAG: addi [[REGB:[0-9]+]], [[REG]], env_sigill@toc@l
 ; CHECK-DAG: std [[REGB]], [[OFF:[0-9]+]](31)                  # 8-byte Folded Spill
 ; CHECK-DAG: std 1, 16([[REGB]])
 ; CHECK-DAG: std 2, 24([[REGB]])
 ; CHECK-DAG: std 30, 32([[REGB]])

test/CodeGen/PowerPC/vsx-spill.ll

entry:
   br label %return
 
 ; CHECK-REG: @foo1
 ; CHECK-REG: xxlor [[R1:[0-9]+]], 1, 1
 ; CHECK-REG: xxlor 1, [[R1]], [[R1]]
 ; CHECK-REG: blr
 
 ; CHECK-FISL: @foo1
-; CHECK-FISL: lis 3, -1
-; CHECK-FISL: ori 3, 3, 65384
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
+; CHECK-FISL: li 3, -152
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
 ; CHECK-FISL: stxsdx 1, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-P9-REG: @foo1
 ; CHECK-P9-REG: xxlor [[R1:[0-9]+]], 1, 1
 ; CHECK-P9-REG: xxlor 1, [[R1]], [[R1]]
 ; CHECK-P9-REG: blr
 

test/CodeGen/PowerPC/vsx.ll

 
 ; CHECK-REG-LABEL: @test14
 ; CHECK-REG: xxlnor 34, 34, 35
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test14
 ; CHECK-FISL: xxlor 0, 34, 35
 ; CHECK-FISL: xxlnor 34, 34, 35
-; CHECK-FISL: lis 3, -1
-; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
+; CHECK-FISL: li 3, -16
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
 ; CHECK-FISL: stxvd2x 0, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test14
 ; CHECK-LE: xxlnor 34, 34, 35
 ; CHECK-LE: blr
 }
 
 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
 entry:
   %v = or <8 x i16> %a, %b
   %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
   ret <8 x i16> %w
 
 ; CHECK-REG-LABEL: @test15
 ; CHECK-REG: xxlnor 34, 34, 35
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test15
 ; CHECK-FISL: xxlor 0, 34, 35
 ; CHECK-FISL: xxlor 36, 0, 0
 ; CHECK-FISL: xxlnor 0, 34, 35
 ; CHECK-FISL: xxlor 34, 0, 0
-; CHECK-FISL: lis 3, -1
-; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
+; CHECK-FISL: li 3, -16
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
 ; CHECK-FISL: stxvd2x 36, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test15
 ; CHECK-LE: xxlnor 34, 34, 35
 ; CHECK-LE: blr
 }
 
 define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
 entry:
   %v = or <16 x i8> %a, %b
   %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   ret <16 x i8> %w
 
 ; CHECK-REG-LABEL: @test16
 ; CHECK-REG: xxlnor 34, 34, 35
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test16
 ; CHECK-FISL: xxlor 0, 34, 35
 ; CHECK-FISL: xxlor 36, 0, 0
 ; CHECK-FISL: xxlnor 0, 34, 35
 ; CHECK-FISL: xxlor 34, 0, 0
-; CHECK-FISL: lis 3, -1
-; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
+; CHECK-FISL: li 3, -16
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
 ; CHECK-FISL: stxvd2x 36, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test16
 ; CHECK-LE: xxlnor 34, 34, 35
 ; CHECK-LE: blr
 }
 

 ; CHECK-REG: xxlandc 34, 34, 35
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test18
 ; CHECK-FISL: xxlnor 0, 35, 35
 ; CHECK-FISL: xxlor 36, 0, 0
 ; CHECK-FISL: xxlandc 0, 34, 35
 ; CHECK-FISL: xxlor 34, 0, 0
-; CHECK-FISL: lis 3, -1
-; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
+; CHECK-FISL: li 3, -16
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
 ; CHECK-FISL: stxvd2x 36, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test18
 ; CHECK-LE: xxlandc 34, 34, 35
 ; CHECK-LE: blr
 }
 
 define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
 entry:
   %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %v = and <16 x i8> %a, %w
   ret <16 x i8> %v
 
 ; CHECK-REG-LABEL: @test19
 ; CHECK-REG: xxlandc 34, 34, 35
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test19
 ; CHECK-FISL: xxlnor 0, 35, 35
 ; CHECK-FISL: xxlor 36, 0, 0
 ; CHECK-FISL: xxlandc 0, 34, 35
 ; CHECK-FISL: xxlor 34, 0, 0
-; CHECK-FISL: lis 3, -1
-; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
+; CHECK-FISL: li 3, -16
+; CHECK-FISL-NOT: lis
+; CHECK-FISL-NOT: ori
 ; CHECK-FISL: stxvd2x 36, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test19
 ; CHECK-LE: xxlandc 34, 34, 35
 ; CHECK-LE: blr
 }
 

test/CodeGen/PowerPC/vsxD-Form-spills.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-PWR9 %s
+
+define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) {
+
+; CHECK-LABEL: testSpill:
+; CHECK:    li 11, 80
+; CHECK:    li 12, 96
+; CHECK:    li 3, 48
+; CHECK:    li 10, 64
+; CHECK:    stxvd2x 62, 1, 11 # 16-byte Folded Spill
+; CHECK:    stxvd2x 63, 1, 12 # 16-byte Folded Spill
+; CHECK:    stxvd2x 60, 1, 3 # 16-byte Folded Spill
+; CHECK:    stxvd2x 61, 1, 10 # 16-byte Folded Spill
+; CHECK:    li 9, 96
+; CHECK:    li 10, 80
+; CHECK:    li 11, 64
+; CHECK:    li 12, 48
+; CHECK:    lxvd2x 63, 1, 9 # 16-byte Folded Reload
+; CHECK:    lxvd2x 62, 1, 10 # 16-byte Folded Reload
+; CHECK:    lxvd2x 61, 1, 11 # 16-byte Folded Reload
+; CHECK:    lxvd2x 60, 1, 12 # 16-byte Folded Reload
+; CHECK:    mtlr 0
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR9-LABEL: testSpill:
+; CHECK-PWR9:    stxv 62, 80(1) # 16-byte Folded Spill
+; CHECK-PWR9:    stxv 63, 96(1) # 16-byte Folded Spill
+; CHECK-PWR9:    stxv 60, 48(1) # 16-byte Folded Spill
+; CHECK-PWR9:    stxv 61, 64(1) # 16-byte Folded Spill
+; CHECK-PWR9:    lxv 63, 96(1) # 16-byte Folded Reload
+; CHECK-PWR9:    lxv 62, 80(1) # 16-byte Folded Reload
+; CHECK-PWR9:    lxv 61, 64(1) # 16-byte Folded Reload
+; CHECK-PWR9:    lxv 60, 48(1) # 16-byte Folded Reload
+; CHECK-PWR9:    mtlr 0
+; CHECK-PWR9-NEXT:    blr
+
+entry:
+  %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b)
+  %tobool = icmp eq i32 %0, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  %call = tail call <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b)
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  %call1 = tail call <4 x i32> @test2(<4 x i32> %b, <4 x i32> %a)
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %c.0.in = phi <4 x i32> [ %call, %if.then ], [ %call1, %if.else ]
+  %call3 = tail call <4 x i32> @test1(<4 x i32> %b, <4 x i32> %a)
+  %call5 = tail call <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b)
+  %add4 = add <4 x i32> %a, <i32 0, i32 0, i32 2, i32 2>
+  %add6 = add <4 x i32> %add4, %c.0.in
+  %c.0 = add <4 x i32> %add6, %call3
+  %add7 = add <4 x i32> %c.0, %call5
+  ret <4 x i32> %add7
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)
+declare <4 x i32> @test1(<4 x i32>, <4 x i32>)
+declare <4 x i32> @test2(<4 x i32>, <4 x i32>)