[mips] Introducing option -mabs=[legacy/2008]

[abeserminji]

Summary

In patch D3274 using abs.[ds] instruction is forced, as they should behave in accordance with flags Has2008 and ABS2008. Unfortunately for revisions prior mips32r6 and mips64r6, abs.[ds] is not generating correct result when working with NaNs. To generate a sequence which always produce a correct result but also to allow user more control on how his code is compiled, option -mabs is added where user can choose legacy or 2008. By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6 use abs2008 mode by default.

Part of this patch is taken from patch D3274.

This is LLVM part of patch. Clang part can be found here: https://reviews.llvm.org/D35982

[sdardis]

CodeGen/Mips/fabs.ll

3

abs.[ds] does not generate the correct result when working with NaNs

4

enabled

5

Also, restore the comment that begins with "In 1985 mode," to give better context as to what's being tested.

6–26

This also requires some big endian tests.

Target/Mips/Mips.td

83

Indentation is wrong here, this line should be aligned to the first quotation mark of "abs2008".

Target/Mips/MipsISelLowering.cpp

335

Demorgan's law: change !A && !B to !(A || B), it's somewhat easier to immediately see it is correct.

2428

hasMips64() there should be checking if the ABI is N32 or N64.

Target/Mips/MipsInstrInfo.td

226

Overly long line. You can break it like so:

def UseAbs :          Predicate<"Subtarget->inAbs2008Mode() ||"
                                "TM.Options.NoNaNsFPMath">;

Target/Mips/MipsSubtarget.cpp

106–107

These if statements can be joined together.

108

This line is not clang-formatted.

[abeserminji]

Resolved all the comments.

[sdardis]

You'll also need to guard the microMIPSr3 definitions of fabs with the UseAbs and extend the fabs test case for microMIPS.

lib/Target/Mips/MipsISelLowering.cpp

2426–2427 ↗

(On Diff #111499)

For MIPS cpus that lack ins / ext instructions, DAGCombine performs this transformation: (srl (shl x, c), c) -> (and x, cst2).

So some follow up work would be to provide DAG patterns which transform (and x, cst) back to a (shl (srl x (clz cst)) (clz cst)) sequence.

I do have a stale patch which addresses this.

2433–2436 ↗

(On Diff #111499)

FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64 Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we should be able to drop the usage of mfc1/mtc1 and rewrite the register in place.

lib/Target/Mips/MipsInstrFPU.td

428 ↗

(On Diff #111499)

This requires NotInMicroMips as well.

test/CodeGen/Mips/fabs.ll

25–26 ↗

(On Diff #111499)

I believe this should be -mcpu=mips64r2 (and correct the triple to mips64).

47–48 ↗

(On Diff #111499)

This I believe should be -mcpu=mips64r2 (and correct the triple to mips64).

[abeserminji]

lib/Target/Mips/MipsISelLowering.cpp

2426–2427 ↗

(On Diff #111499)

Is it ok if I add a TODO comment here, so you can submit you patch later?

2433–2436 ↗

(On Diff #111499)

Should I just add this as a comment above the return statement?

[sdardis]

lib/Target/Mips/MipsISelLowering.cpp

2426–2427 ↗

(On Diff #111499)

Yes, that's fine.

2433–2436 ↗

(On Diff #111499)

Just above the 'SDValue LowX'.

[abeserminji]

Comments resolved:

• Added new run checks for microMIPS
• Corrected existing run check lines
• Added NotInMicroMips to the FABS guard in Mips
• Guarded FABS in microMIPS with UseAbs
• Added comments for future work

[abeserminji]

test/CodeGen/Mips/fabs.ll

54 ↗

(On Diff #112538)

I was unable to test microMIPS for some CPUs (mips64, mips32r6, ...) due errors like:

• LLVM ERROR: ran out of registers during register allocation
• LLVM ERROR: Cannot select: t11: f64 = bitcast t14

Do you have any recommendation what to do about it?

[sdardis]

test/CodeGen/Mips/fabs.ll

54 ↗

(On Diff #112538)

Can you run it with -debug and check what registers classes are in use? If you're seeing AFGR64 and FGR64 at the same time, you've hit the bug I suspected.

That bug is where microMIPS AFGR64 using instructions are also available with FGR64 instructions, except that the entire AFGR register set is reserved. The register allocator then errors out because ISel has "incorrectly" selected the AFGR instructions.

[abeserminji]

test/CodeGen/Mips/fabs.ll

54 ↗

(On Diff #112538)

Yes, that's exactly what I get. FGR64 and AFGR64 registers are in use at the same time.

[sdardis]

test/CodeGen/Mips/fabs.ll

54 ↗

(On Diff #112538)

I had hoped to defer that work for a bit. In summary, we need to fix the predicates that guard the micromips instruction set, as currently it's somewhat broken.

The first step towards fixing that issue is to change the overall Predicate = [InMicroMips] for the microMIPS FPU instructions to be AdditionalPredicates = [InMicroMips], then annotate all the floating point instructions there with the correct predicates (ISA, FPU model etc).

The next step is to add predicates for micromips encoding, mips16 encoding, rework the instruction classes not set the encoding predicate, and having a joint encoding + ISA level predicate determining if an instruction is available for a given ISA level and encoding, rather than separating it out into AdditionalPredicates.

Can you take a look at the first step?

Thanks,
Simon

[sdardis]

LGTM as rL315362 should fix the register allocation issue.

lib/Target/Mips/Mips.td

83 ↗

(On Diff #112538)

abs -> abs.fmt mode

lib/Target/Mips/MipsSubtarget.cpp

109 ↗

(On Diff #112538)

Abs -> abs.fmt

lib/Target/Mips/MipsSubtarget.h

81 ↗

(On Diff #112538)

Abs -> abs.fmt

[abeserminji]

Now I get an error for abs.[sd] in this test test/MC/Mips/micromips-fpu-instructions.s, saying that instruction requires a CPU feature not currently enabled. I checked the instruction definitions, and one solution to avoid the error would be to remove NotInMicroMips from AdditionalPredicates at 428 in MipsInstrFPU.td. As abs.fmt instruction in MipsInstrFPU.td has MMRel, my guess would be that NotInMicroMips should not be in AdditionalPredicates. Or is there other way to solve this?

[sdardis]

The root of the problem is that many of the microMIPS FPU instructions are marked as isCodeGenOnly, which means that they aren't in the assembler matching table or disassembler table. This means that although the microMIPS32R6 definitions are used, we can't match them as those definitions have differing feature bits to what the invocation of llvm-mc has in that test. I've got a WIP patch to being addressing this. Hold off on trying to get this patch in for the moment.

[sdardis]

+CCing the llvm-commits.

[abeserminji]

Rebased and updated the patch. Now it seems like the past issues are gone.

[atanasyan]

LGTM

CodeGen/Mips/fabs.ll

-; Check that abs.[ds] is selected and does not depend on -enable-no-nans-fp-math
-; They obey the Has2008 and ABS2008 configuration bits which govern the
-; conformance to IEEE 754 (1985) and IEEE 754 (2008). When these bits are not
-; present, they confirm to 1985.
-; In 1985 mode, abs.[ds] are arithmetic (i.e. they raise invalid operation
-; exceptions when given NaN's). In 2008 mode, they are non-arithmetic (i.e.
-; they are copies and don't raise any exceptions).
-
-; RUN: llc  < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s
-; RUN: llc  < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s
-; RUN: llc  < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s
-
-; RUN: llc  < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 | FileCheck %s
-; RUN: llc  < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 -enable-no-nans-fp-math | FileCheck %s
+; Check that abs.[ds] is only selected for mips32r6 or mips64r6 when no
+; additional options are passed. For revisions prior mips32r6 and mips64r6,
+; abs.[ds] is not generating correct result when working with NaNs, and
+; should be explicitly enabed with -enable-no-nans-fp-math or +abs2008 options.
+
+; RUN: llc  < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s \
+; RUN:   -check-prefix=CHECK-ABSLEGACY
+; RUN: llc  < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 | FileCheck %s \
+; RUN:   -check-prefix=CHECK-ABSLEGACY
+; RUN: llc  < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s \
+; RUN:   -check-prefix=CHECK-ABSLEGACY
+; RUN: llc  < %s -mtriple=mips64el-linux-gnu -mcpu=mips64r2 | FileCheck %s \
+; RUN:    -check-prefix=CHECK-ABSLEGACY
+
+; RUN: llc  < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 \
+; RUN:    -enable-no-nans-fp-math | FileCheck %s -check-prefix=CHECK-ABS2008
+; RUN: llc  < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 \
+; RUN:    -enable-no-nans-fp-math | FileCheck %s -check-prefix=CHECK-ABS2008
+; RUN: llc  < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+abs2008 \
+; RUN:    | FileCheck %s -check-prefix=CHECK-ABS2008
+; RUN: llc  < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+abs2008 \
+; RUN:    | FileCheck %s -check-prefix=CHECK-ABS2008
+; RUN: llc  < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r6 | FileCheck %s \
+; RUN:    -check-prefix=CHECK-ABS2008
+; RUN: llc  < %s -mtriple=mips64el-linux-gnu -mcpu=mips64r6 | FileCheck %s \
+; RUN:    -check-prefix=CHECK-ABS2008
 
 define float @foo0(float %a) nounwind readnone {
 entry:
 
 ; CHECK-LABEL: foo0
-; CHECK: abs.s
+; CHECK-ABS2008: abs.s
+; CHECK-ABSLEGACY: {{(ori|ins)}}
+; CHECK-ABSLEGACY-NOT: abs.s
 
   %call = tail call float @fabsf(float %a) nounwind readnone
   ret float %call
 }
 
 declare float @fabsf(float) nounwind readnone
 
 define double @foo1(double %a) nounwind readnone {
 entry:
 
 ; CHECK-LABEL: foo1:
-; CHECK: abs.d
+; CHECK-ABS2008: abs.d
+; CHECK-ABSLEGACY: {{(ori|ins|dsll)}}
+; CHECK-ABSLEGACY-NOT: abs.d
 
   %call = tail call double @fabs(double %a) nounwind readnone
   ret double %call
 }
 
 declare double @fabs(double) nounwind readnone

CodeGen/Mips/msa/f16-llvm-ir.ll

 ; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips32r5 \
-; RUN:     -mattr=+fp64,+msa -verify-machineinstrs < %s | FileCheck %s \
+; RUN:     -mattr=+fp64,+msa,+abs2008 -verify-machineinstrs < %s | FileCheck %s \
 ; RUN:     --check-prefixes=ALL,MIPS32,MIPSR5,MIPS32-O32,MIPS32R5-O32
 ; RUN: llc -relocation-model=pic -march=mips64el -mcpu=mips64r5 \
-; RUN:     -mattr=+fp64,+msa -verify-machineinstrs -target-abi n32 < %s | FileCheck %s \
+; RUN:     -mattr=+fp64,+msa,+abs2008 -verify-machineinstrs -target-abi n32 < %s | FileCheck %s \
 ; RUN:     --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N32,MIPS64R5-N32
 ; RUN: llc -relocation-model=pic -march=mips64el -mcpu=mips64r5 \
-; RUN:     -mattr=+fp64,+msa -verify-machineinstrs -target-abi n64 < %s | FileCheck %s \
+; RUN:     -mattr=+fp64,+msa,+abs2008 -verify-machineinstrs -target-abi n64 < %s | FileCheck %s \
 ; RUN:     --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N64,MIPS64R5-N64
 
 ; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips32r6 \
 ; RUN:     -mattr=+fp64,+msa -verify-machineinstrs < %s | FileCheck %s \
 ; RUN:     --check-prefixes=ALL,MIPS32,MIPSR6,MIPSR6-O32
 ; RUN: llc -relocation-model=pic -march=mips64el -mcpu=mips64r6 \
 ; RUN:     -mattr=+fp64,+msa -verify-machineinstrs -target-abi n32 < %s | FileCheck %s \
 ; RUN:     --check-prefixes=ALL,MIPS64,MIPSR6,MIPS64-N32,MIPSR6-N32

Target/Mips/Mips.td

 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
                                 "General Purpose Registers are 64-bit wide">;
 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
                                 "Support 64-bit FP registers">;
 def FeatureFPXX        : SubtargetFeature<"fpxx", "IsFPXX", "true",
                                 "Support for FPXX">;
 def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
                                 "IEEE 754-2008 NaN encoding">;
+def FeatureAbs2008     : SubtargetFeature<"abs2008", "Abs2008", "true",
+                                "IEEE 754-2008 abs mode">;
 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
                                 "true", "Only supports single precision float">;
 def FeatureSoftFloat   : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
                                 "Does not support floating point instructions">;
 def FeatureNoOddSPReg  : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
                               "Disable odd numbered single-precision "
                               "registers">;
 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
def FeatureMips32r3    : SubtargetFeature<"mips32r3", "MipsArchVersion",
                                 [FeatureMips32r2]>;
 def FeatureMips32r5    : SubtargetFeature<"mips32r5", "MipsArchVersion",
                                 "Mips32r5", "Mips32r5 ISA Support",
                                 [FeatureMips32r3]>;
 def FeatureMips32r6    : SubtargetFeature<"mips32r6", "MipsArchVersion",
                                 "Mips32r6",
                                 "Mips32r6 ISA Support [experimental]",
                                 [FeatureMips32r5, FeatureFP64Bit,
-                                 FeatureNaN2008]>;
+                                 FeatureNaN2008, FeatureAbs2008]>;
 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
                                 "Mips64", "Mips64 ISA Support",
                                 [FeatureMips5, FeatureMips32]>;
 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
                                 "Mips64r2", "Mips64r2 ISA Support",
                                 [FeatureMips64, FeatureMips32r2]>;
 def FeatureMips64r3    : SubtargetFeature<"mips64r3", "MipsArchVersion",
                                 "Mips64r3", "Mips64r3 ISA Support",
                                 [FeatureMips64r2, FeatureMips32r3]>;
 def FeatureMips64r5    : SubtargetFeature<"mips64r5", "MipsArchVersion",
                                 "Mips64r5", "Mips64r5 ISA Support",
                                 [FeatureMips64r3, FeatureMips32r5]>;
 def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
                                 "Mips64r6",
                                 "Mips64r6 ISA Support [experimental]",
                                 [FeatureMips32r6, FeatureMips64r5,
-                                 FeatureNaN2008]>;
+                                 FeatureNaN2008, FeatureAbs2008]>;
 def FeatureSym32       : SubtargetFeature<"sym32", "HasSym32", "true",
                                           "Symbols are 32 bit on Mips64">;
 
 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
                                       "Mips16 mode">;
 
 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",

Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
   setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
   setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
   setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
   setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
   setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
   setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
   setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
 
+  if (!TM.Options.NoNaNsFPMath && !Subtarget.inAbs2008Mode()) {
+    setOperationAction(ISD::FABS,             MVT::f32,   Custom);
+    setOperationAction(ISD::FABS,             MVT::f64,   Custom);
+  }
+
   if (Subtarget.isGP64bit()) {
     setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
     setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
     setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
     setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
     setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
     setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
     setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
LowerOperation(SDValue Op, SelectionDAG &DAG) const
   case ISD::BlockAddress:       return lowerBlockAddress(Op, DAG);
   case ISD::GlobalTLSAddress:   return lowerGlobalTLSAddress(Op, DAG);
   case ISD::JumpTable:          return lowerJumpTable(Op, DAG);
   case ISD::SELECT:             return lowerSELECT(Op, DAG);
   case ISD::SETCC:              return lowerSETCC(Op, DAG);
   case ISD::VASTART:            return lowerVASTART(Op, DAG);
   case ISD::VAARG:              return lowerVAARG(Op, DAG);
   case ISD::FCOPYSIGN:          return lowerFCOPYSIGN(Op, DAG);
+  case ISD::FABS:               return lowerFABS(Op, DAG);
   case ISD::FRAMEADDR:          return lowerFRAMEADDR(Op, DAG);
   case ISD::RETURNADDR:         return lowerRETURNADDR(Op, DAG);
   case ISD::EH_RETURN:          return lowerEH_RETURN(Op, DAG);
   case ISD::ATOMIC_FENCE:       return lowerATOMIC_FENCE(Op, DAG);
   case ISD::SHL_PARTS:          return lowerShiftLeftParts(Op, DAG);
   case ISD::SRA_PARTS:          return lowerShiftRightParts(Op, DAG, true);
   case ISD::SRL_PARTS:          return lowerShiftRightParts(Op, DAG, false);
   case ISD::LOAD:               return lowerLOAD(Op, DAG);

 SDValue
 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
   if (Subtarget.isGP64bit())
     return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
 
   return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
 }
 
+static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG,
+                           bool HasExtractInsert) {
+  SDLoc DL(Op);
+  SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
+
+  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
+  // to i32.
+  SDValue X = (Op.getValueType() == MVT::f32) ?
+    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
+    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
+                Const1);
+
+  // Clear MSB.
+  if (HasExtractInsert)
+    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
+                      DAG.getRegister(Mips::ZERO, MVT::i32),
+                      DAG.getConstant(31, DL, MVT::i32), Const1, X);
+  else {
+    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
+    Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
+  }
+
+  if (Op.getValueType() == MVT::f32)
+    return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
+
+  SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
+                             Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
+  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
+}
+
+static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG,
+                           bool HasExtractInsert) {
+  SDLoc DL(Op);
+  SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
+
+  // Bitcast to integer node.
+  SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
+
+  // Clear MSB.
+  if (HasExtractInsert)
+    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
+                      DAG.getRegister(Mips::ZERO_64, MVT::i64),
+                      DAG.getConstant(63, DL, MVT::i32), Const1, X);
+  else {
+    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
+    Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
+  }
+
+  return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
+}
+
+SDValue
+MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
+  if (Subtarget.hasMips64() && (Op.getValueType() == MVT::f64))
+    return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert());
+
+  return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert());
+}
+
 SDValue MipsTargetLowering::
 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
   // check the depth
   assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
          "Frame address can only be determined for current frame.");
 
   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
   MFI.setFrameAddressIsTaken(true);

Target/Mips/MipsInstrFPU.td

 let isPseudo = 1, isCodeGenOnly = 1 in {
   def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
   def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
   def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
   def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
   def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
 }
 
+let AdditionalPredicates = [UseAbs] in {
   def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
                ABSS_FM<0x5, 16>;
+  defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
+}
+
 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
              ABSS_FM<0x7, 16>;
-defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
 
 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
               II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
 
 // The odd-numbered registers are only referenced when doing loads,
 // stores, and moves between floating-point and integer registers.

Target/Mips/MipsInstrInfo.td

def NotCnMips    :    Predicate<"!Subtarget->hasCnMips()">,
                       AssemblerPredicate<"!FeatureCnMips">;
 def IsSym32     :     Predicate<"Subtarget->HasSym32()">,
                       AssemblerPredicate<"FeatureSym32">;
 def IsSym64     :     Predicate<"!Subtarget->HasSym32()">,
                       AssemblerPredicate<"!FeatureSym32">;
 def RelocNotPIC :     Predicate<"!TM.isPositionIndependent()">;
 def RelocPIC    :     Predicate<"TM.isPositionIndependent()">;
 def NoNaNsFPMath :    Predicate<"TM.Options.NoNaNsFPMath">;
+def UseAbs :          Predicate<"Subtarget->inAbs2008Mode() || TM.Options.NoNaNsFPMath">;
 def HasStdEnc :       Predicate<"Subtarget->hasStandardEncoding()">,
                       AssemblerPredicate<"!FeatureMips16">;
 def NotDSP :          Predicate<"!Subtarget->hasDSP()">;
 def InMicroMips    :  Predicate<"Subtarget->inMicroMipsMode()">,
                       AssemblerPredicate<"FeatureMicroMips">;
 def NotInMicroMips :  Predicate<"!Subtarget->inMicroMipsMode()">,
                       AssemblerPredicate<"!FeatureMicroMips">;
 def IsLE           :  Predicate<"Subtarget->isLittle()">;

Target/Mips/MipsSubtarget.h

class MipsSubtarget : public MipsGenSubtargetInfo {
 
   /// Are odd single-precision registers permitted?
   /// This corresponds to -modd-spreg and -mno-odd-spreg
   bool UseOddSPReg;
 
   // IsNan2008 - IEEE 754-2008 NaN encoding.
   bool IsNaN2008bit;
 
+  // Abs2008 - Use IEEE 754-2008 Abs instruction.
+  bool Abs2008;
+
   // IsGP64bit - General-purpose registers are 64 bits wide
   bool IsGP64bit;
 
   // IsPTR64bit - Pointers are 64 bit wide
   bool IsPTR64bit;
 
   // HasVFPU - Processor has a vector floating point unit.
   bool HasVFPU;
public:
 
   bool isLittle() const { return IsLittle; }
   bool isABICalls() const { return !NoABICalls; }
   bool isFPXX() const { return IsFPXX; }
   bool isFP64bit() const { return IsFP64bit; }
   bool useOddSPReg() const { return UseOddSPReg; }
   bool noOddSPReg() const { return !UseOddSPReg; }
   bool isNaN2008() const { return IsNaN2008bit; }
+  bool inAbs2008Mode() const { return Abs2008; }
   bool isGP64bit() const { return IsGP64bit; }
   bool isGP32bit() const { return !IsGP64bit; }
   unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
   bool isPTR64bit() const { return IsPTR64bit; }
   bool isPTR32bit() const { return !IsPTR64bit; }
   bool hasSym32() const {
     return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
   }

Target/Mips/MipsSubtarget.cpp

 
 void MipsSubtarget::anchor() { }
 
 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
                              bool little, const MipsTargetMachine &TM)
     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
       IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
-      IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
-      HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
-      HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
-      InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
-      HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
-      Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
-      HasEVA(false), DisableMadd4(false), HasMT(false), TM(TM),
-      TargetTriple(TT), TSInfo(),
+      IsNaN2008bit(false), Abs2008(false), IsGP64bit(false), HasVFPU(false),
+      HasCnMips(false), HasMips3_32(false), HasMips3_32r2(false),
+      HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
+      InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
+      InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false),
+      AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
+      UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
+      HasMT(false), TM(TM), TargetTriple(TT), TSInfo(),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
       FrameLowering(MipsFrameLowering::create(*this)),
       TLInfo(MipsTargetLowering::create(TM, *this)) {
 
   if (MipsArchVersion == MipsDefault)
     MipsArchVersion = Mips32;
 
report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
                        false);
 
   if (!isABI_O32() && !useOddSPReg())
     report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
 
   if (IsFPXX && (isABI_N32() || isABI_N64()))
     report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
 
+  if (inAbs2008Mode()) {
+    if (hasMips32() && !hasMips32r2()) {
+      report_fatal_error("IEEE 754-2008 Abs is not supported for the given architecture.", false);
+    }
+  }
+
   if (hasMips32r6()) {
     StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
 
     assert(isFP64bit());
     assert(isNaN2008());
+    assert(inAbs2008Mode());
     if (hasDSP())
       report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
   }
 
   if (NoABICalls && TM.isPositionIndependent())
     report_fatal_error("position-independent code requires '-mabicalls'");
 
   if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())