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author
Aleksandar Beserminji
committedJan 28, 2019
[mips] Support for +abs2008 attribute
Instruction abs.[ds] is not generating correct result when working with NaNs for revisions prior mips32r6 and mips64r6. To generate a sequence which always produce a correct result, but also to allow user more control on how his code is compiled, attribute +abs2008 is added, so user can choose legacy or 2008. By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6 use abs2008 mode by default. Differential Revision: https://reviews.llvm.org/D35983 llvm-svn: 352370
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‎llvm/lib/Target/Mips/MicroMipsInstrFPU.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,7 @@ multiclass ABSS_MMM<string opstr, InstrItinClass Itin,
123123
defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
124124
defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
125125

126-
let DecoderNamespace = "MicroMips" in {
126+
let DecoderNamespace = "MicroMips", AdditionalPredicates = [UseAbs] in {
127127
def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
128128
ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;
129129
}

‎llvm/lib/Target/Mips/Mips.td

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,8 @@ def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
8282
"Support for FPXX">;
8383
def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
8484
"IEEE 754-2008 NaN encoding">;
85+
def FeatureAbs2008 : SubtargetFeature<"abs2008", "Abs2008", "true",
86+
"Disable IEEE 754-2008 abs.fmt mode">;
8587
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
8688
"true", "Only supports single precision float">;
8789
def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
@@ -141,7 +143,7 @@ def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
141143
"Mips32r6",
142144
"Mips32r6 ISA Support [experimental]",
143145
[FeatureMips32r5, FeatureFP64Bit,
144-
FeatureNaN2008]>;
146+
FeatureNaN2008, FeatureAbs2008]>;
145147
def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
146148
"Mips64", "Mips64 ISA Support",
147149
[FeatureMips5, FeatureMips32]>;
@@ -158,7 +160,7 @@ def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
158160
"Mips64r6",
159161
"Mips64r6 ISA Support [experimental]",
160162
[FeatureMips32r6, FeatureMips64r5,
161-
FeatureNaN2008]>;
163+
FeatureNaN2008, FeatureAbs2008]>;
162164
def FeatureSym32 : SubtargetFeature<"sym32", "HasSym32", "true",
163165
"Symbols are 32 bit on Mips64">;
164166

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -364,6 +364,11 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
364364
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
365365
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
366366

367+
if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) {
368+
setOperationAction(ISD::FABS, MVT::f32, Custom);
369+
setOperationAction(ISD::FABS, MVT::f64, Custom);
370+
}
371+
367372
if (Subtarget.isGP64bit()) {
368373
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
369374
setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
@@ -1218,6 +1223,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
12181223
case ISD::VASTART: return lowerVASTART(Op, DAG);
12191224
case ISD::VAARG: return lowerVAARG(Op, DAG);
12201225
case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1226+
case ISD::FABS: return lowerFABS(Op, DAG);
12211227
case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
12221228
case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
12231229
case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
@@ -2295,6 +2301,71 @@ MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
22952301
return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
22962302
}
22972303

2304+
static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG,
2305+
bool HasExtractInsert) {
2306+
SDLoc DL(Op);
2307+
SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2308+
2309+
// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2310+
// to i32.
2311+
SDValue X = (Op.getValueType() == MVT::f32)
2312+
? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0))
2313+
: DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2314+
Op.getOperand(0), Const1);
2315+
2316+
// Clear MSB.
2317+
if (HasExtractInsert)
2318+
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2319+
DAG.getRegister(Mips::ZERO, MVT::i32),
2320+
DAG.getConstant(31, DL, MVT::i32), Const1, X);
2321+
else {
2322+
// TODO: Provide DAG patterns which transform (and x, cst)
2323+
// back to a (shl (srl x (clz cst)) (clz cst)) sequence.
2324+
SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2325+
Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2326+
}
2327+
2328+
if (Op.getValueType() == MVT::f32)
2329+
return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2330+
2331+
// FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64
2332+
// Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we
2333+
// should be able to drop the usage of mfc1/mtc1 and rewrite the register in
2334+
// place.
2335+
SDValue LowX =
2336+
DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2337+
DAG.getConstant(0, DL, MVT::i32));
2338+
return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2339+
}
2340+
2341+
static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG,
2342+
bool HasExtractInsert) {
2343+
SDLoc DL(Op);
2344+
SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2345+
2346+
// Bitcast to integer node.
2347+
SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2348+
2349+
// Clear MSB.
2350+
if (HasExtractInsert)
2351+
Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2352+
DAG.getRegister(Mips::ZERO_64, MVT::i64),
2353+
DAG.getConstant(63, DL, MVT::i32), Const1, X);
2354+
else {
2355+
SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2356+
Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2357+
}
2358+
2359+
return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2360+
}
2361+
2362+
SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2363+
if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64))
2364+
return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert());
2365+
2366+
return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert());
2367+
}
2368+
22982369
SDValue MipsTargetLowering::
22992370
lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
23002371
// check the depth

‎llvm/lib/Target/Mips/MipsInstrFPU.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -486,7 +486,7 @@ let isPseudo = 1, isCodeGenOnly = 1 in {
486486
def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
487487
}
488488

489-
let AdditionalPredicates = [NotInMicroMips] in {
489+
let AdditionalPredicates = [NotInMicroMips, UseAbs] in {
490490
def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
491491
ABSS_FM<0x5, 16>, ISA_MIPS1;
492492
defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1;

‎llvm/lib/Target/Mips/MipsInstrInfo.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -220,6 +220,8 @@ def IsNotN64 : Predicate<"!Subtarget->isABI_N64()">;
220220
def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">;
221221
def RelocPIC : Predicate<"TM.isPositionIndependent()">;
222222
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
223+
def UseAbs : Predicate<"Subtarget->inAbs2008Mode() ||"
224+
"TM.Options.NoNaNsFPMath">;
223225
def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
224226
AssemblerPredicate<"!FeatureMips16">;
225227
def NotDSP : Predicate<"!Subtarget->hasDSP()">;

‎llvm/lib/Target/Mips/MipsSubtarget.cpp

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
7272
unsigned StackAlignOverride)
7373
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
7474
IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
75-
NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
75+
NoABICalls(false), Abs2008(false), IsFP64bit(false), UseOddSPReg(true),
7676
IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
7777
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
7878
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
@@ -128,11 +128,18 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
128128
report_fatal_error(
129129
"indirect jumps with hazard barriers requires MIPS32R2 or later");
130130
}
131+
if (inAbs2008Mode() && hasMips32() && !hasMips32r2()) {
132+
report_fatal_error("IEEE 754-2008 abs.fmt is not supported for the given "
133+
"architecture.",
134+
false);
135+
}
136+
131137
if (hasMips32r6()) {
132138
StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
133139

134140
assert(isFP64bit());
135141
assert(isNaN2008());
142+
assert(inAbs2008Mode());
136143
if (hasDSP())
137144
report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
138145
}

‎llvm/lib/Target/Mips/MipsSubtarget.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
8686
// NoABICalls - Disable SVR4-style position-independent code.
8787
bool NoABICalls;
8888

89+
// Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
90+
bool Abs2008;
91+
8992
// IsFP64bit - The target processor has 64-bit floating point registers.
9093
bool IsFP64bit;
9194

@@ -272,6 +275,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
272275
bool useOddSPReg() const { return UseOddSPReg; }
273276
bool noOddSPReg() const { return !UseOddSPReg; }
274277
bool isNaN2008() const { return IsNaN2008bit; }
278+
bool inAbs2008Mode() const { return Abs2008; }
275279
bool isGP64bit() const { return IsGP64bit; }
276280
bool isGP32bit() const { return !IsGP64bit; }
277281
unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }

‎llvm/test/CodeGen/Mips/fabs.ll

Lines changed: 74 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,84 @@
1-
; Check that abs.[ds] is selected and does not depend on -enable-no-nans-fp-math
2-
; They obey the Has2008 and ABS2008 configuration bits which govern the
3-
; conformance to IEEE 754 (1985) and IEEE 754 (2008). When these bits are not
4-
; present, they confirm to 1985.
1+
; Check that abs.[ds] is only selected for mips32r6 or mips64r6 when no
2+
; additional options are passed. For revisions prior mips32r6 and mips64r6,
3+
; abs.[ds] does not generate the correct result when working with NaNs, and
4+
; should be explicitly enabled with -enable-no-nans-fp-math or +abs2008 options.
5+
56
; In 1985 mode, abs.[ds] are arithmetic (i.e. they raise invalid operation
67
; exceptions when given NaN's). In 2008 mode, they are non-arithmetic (i.e.
78
; they are copies and don't raise any exceptions).
89

9-
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s
10-
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s
11-
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s
10+
; Testing default values
11+
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s \
12+
; RUN: -check-prefix=CHECK-ABSLEGACY
13+
; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 | FileCheck %s \
14+
; RUN: -check-prefix=CHECK-ABSLEGACY
15+
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s \
16+
; RUN: -check-prefix=CHECK-ABSLEGACY
17+
; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64r2 | FileCheck %s \
18+
; RUN: -check-prefix=CHECK-ABSLEGACY
19+
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r6 | FileCheck %s \
20+
; RUN: -check-prefix=CHECK-ABS2008
21+
; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64r6 | FileCheck %s \
22+
; RUN: -check-prefix=CHECK-ABS2008
23+
; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 | FileCheck %s \
24+
; RUN: -check-prefix=CHECK-ABSLEGACY
25+
; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 | FileCheck %s \
26+
; RUN: -check-prefix=CHECK-ABSLEGACY
27+
; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 | FileCheck %s \
28+
; RUN: -check-prefix=CHECK-ABSLEGACY
29+
; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 | FileCheck %s \
30+
; RUN: -check-prefix=CHECK-ABSLEGACY
31+
; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 | FileCheck %s \
32+
; RUN: -check-prefix=CHECK-ABS2008
33+
; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 | FileCheck %s \
34+
; RUN: -check-prefix=CHECK-ABS2008
35+
; Testing non-default values
36+
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+abs2008 \
37+
; RUN: | FileCheck %s -check-prefix=CHECK-ABS2008
38+
; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64r2 -mattr=+abs2008 \
39+
; RUN: | FileCheck %s -check-prefix=CHECK-ABS2008
40+
; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+abs2008 \
41+
; RUN: | FileCheck %s -check-prefix=CHECK-ABS2008
42+
; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -mattr=+abs2008 \
43+
; RUN: | FileCheck %s -check-prefix=CHECK-ABS2008
44+
; Testing -enable-no-nans-fp-math
45+
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 \
46+
; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=CHECK-ABS2008
47+
; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 \
48+
; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=CHECK-ABS2008
49+
; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 \
50+
; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=CHECK-ABS2008
51+
; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 \
52+
; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=CHECK-ABS2008
1253

13-
; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 | FileCheck %s
14-
; RUN: llc < %s -mtriple=mips64el-linux-gnu -mcpu=mips64 -enable-no-nans-fp-math | FileCheck %s
54+
; microMIPS
55+
; Testing default values
56+
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -mattr=+micromips \
57+
; RUN: | FileCheck %s -check-prefix=CHECK-ABSLEGACY
58+
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+micromips \
59+
; RUN: | FileCheck %s -check-prefix=CHECK-ABSLEGACY
60+
; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -mattr=+micromips \
61+
; RUN: | FileCheck %s -check-prefix=CHECK-ABSLEGACY
62+
; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips \
63+
; RUN: | FileCheck %s -check-prefix=CHECK-ABSLEGACY
64+
; Testing non-default values
65+
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 \
66+
; RUN: -mattr=+abs2008,+micromips | FileCheck %s -check-prefix=CHECK-ABS2008
67+
; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 \
68+
; RUN: -mattr=+abs2008,+micromips | FileCheck %s -check-prefix=CHECK-ABS2008
69+
; Testing -enable-no-nans-fp-math
70+
; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 -mattr=+micromips \
71+
; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=CHECK-ABS2008
72+
; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -mattr=+micromips \
73+
; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=CHECK-ABS2008
1574

1675
define float @foo0(float %a) nounwind readnone {
1776
entry:
1877

1978
; CHECK-LABEL: foo0
20-
; CHECK: abs.s
79+
; CHECK-ABS2008: abs.s
80+
; CHECK-ABSLEGACY: {{(ori|ins)}}
81+
; CHECK-ABSLEGACY-NOT: abs.s
2182

2283
%call = tail call float @fabsf(float %a) nounwind readnone
2384
ret float %call
@@ -29,7 +90,9 @@ define double @foo1(double %a) nounwind readnone {
2990
entry:
3091

3192
; CHECK-LABEL: foo1:
32-
; CHECK: abs.d
93+
; CHECK-ABS2008: abs.d
94+
; CHECK-ABSLEGACY: {{(ori|ins|dsll)}}
95+
; CHECK-ABSLEGACY-NOT: abs.d
3396

3497
%call = tail call double @fabs(double %a) nounwind readnone
3598
ret double %call

‎llvm/test/CodeGen/Mips/llvm-ir/abs.ll

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,12 @@
1-
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
2-
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
3-
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
4-
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
5-
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
1+
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
2+
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
3+
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
4+
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
5+
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
66

77
define float @abs_s(float %a) {
8-
; MIPS32: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S
8+
; MIPS32: {{(ori|ins)}}
9+
; MIPS32-NOT: abs.s
910
; MIPS32FP64: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S
1011
; MM: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM
1112
; MMFP64: abs.s {{.*}} # <MCInst #{{[0-9]+}} FABS_S_MM
@@ -15,7 +16,8 @@ define float @abs_s(float %a) {
1516
}
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define double @abs_d(double %a) {
18-
; MIPS32: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D32
19+
; MIPS32: {{(ori|ins|dsll)}}
20+
; MIPS32-NOT: abs.d
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; MIPS32FP64: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64
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; MM: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D32_MM
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; MMFP64: abs.d {{.*}} # <MCInst #{{[0-9]+}} FABS_D64_MM

‎llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -relocation-model=pic -mtriple=mipsel-- -mcpu=mips32r5 \
2+
; RUN: llc -relocation-model=pic -mtriple=mipsel-- -mcpu=mips32r5 -mattr=+abs2008 \
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; RUN: -mattr=+fp64,+msa -verify-machineinstrs -mips-jalr-reloc=false < %s | FileCheck %s \
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; RUN: --check-prefixes=ALL,MIPS32,MIPSR5,MIPS32-O32,MIPS32R5-O32
5-
; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r5 \
5+
; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r5 -mattr=+abs2008 \
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; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n32 -mips-jalr-reloc=false < %s | FileCheck %s \
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; RUN: --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N32,MIPS64R5-N32
8-
; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r5 \
8+
; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r5 -mattr=+abs2008 \
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; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n64 -mips-jalr-reloc=false < %s | FileCheck %s \
1010
; RUN: --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N64,MIPS64R5-N64
1111

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