[ARM] Emit error when ARM exec mode is not available.

[fhahn]

Summary

A similar error message has been removed from the ARMTargetMachineBase
constructor in r306939. With this patch, we generate an error message
for the example below, compiled with -mcpu=cortex-m0, which does not
have ARM execution mode.

__attribute__((target("arm"))) int foo(int a, int b)
{
    return a + b % a;
}

__attribute__((target("thumb"))) int bar(int a, int b)
{
    return a + b % a;
}

By adding this error message to ARMBaseTargetMachine::getSubtargetImpl,
we can deal with functions that set -thumb-mode in target-features.
At the moment it seems like Clang does not have access to target-feature
specific information, so adding the error message to the frontend will
be harder.

[efriedma]

Even if clang eventually starts generating its own error message, we should still generate an error in the backend: we shouldn't crash on invalid bitcode files.

test/CodeGen/ARM/no-arm-mode.ll

5

Do you need "not" here? I thought we only check the return code for the last program in the pipe.

[fhahn]

Updated title

test/CodeGen/ARM/no-arm-mode.ll

5

It seems like the return code of the first program is also checked. WIthout not, the test fails when run through lit.

[efriedma]

LGTM

test/CodeGen/ARM/no-arm-mode.ll

5

Hmm, okay, that's fine then.

[fhahn]

Updated to use LLVMContext::emitError instead of fatal error. Before committing D35569 needs to land, otherwise the second invocation of in the test will not produce errors.

[echristo]

LGTM.

lib/Target/ARM/ARMSubtarget.cpp

: ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
       // At this point initializeSubtargetDependencies has been called so
       // we can query directly.
       InstrInfo(isThumb1Only()
                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
                     : !isThumb()
                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
       TLInfo(TM, *this) {
-  assert((isThumb() || hasARMOps()) &&
-         "Target must either be thumb or support ARM operations!");
 
 #ifndef LLVM_BUILD_GLOBAL_ISEL
   GISelAccessor *GISel = new GISelAccessor();
 #else
   ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor();
   GISel->CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
   GISel->Legalizer.reset(new ARMLegalizerInfo(*this));
 

lib/Target/ARM/ARMTargetMachine.cpp

ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
 
   auto &I = SubtargetMap[CPU + FS];
   if (!I) {
     // This needs to be done before we create a new subtarget since any
     // creation will depend on the TM and the code generation flags on the
     // function that reside in TargetOptions.
     resetTargetOptions(F);
     I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
+
+    if (!I->isThumb() && !I->hasARMOps())
+      F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
+          "instructions, but the target does not support ARM mode execution.");
   }
+
   return I.get();
 }
 
 TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
   return TargetIRAnalysis([this](const Function &F) {
     return TargetTransformInfo(ARMTTIImpl(this, F));
   });
 }

test/CodeGen/ARM/no-arm-mode.ll

+; RUN: not llc -mtriple=armv7-windows-itanium -mcpu=cortex-a9 -o /dev/null %s 2>&1 \
+; RUN:   | FileCheck %s -check-prefixes=CHECK-OPTIONS,CHECK-FEATURE
+
+; RUN: not llc -mtriple=thumb-unknown-linux -mcpu=cortex-m0 -o /dev/null %s 2>&1 \
+; RUN:   | FileCheck %s -check-prefix=CHECK-FEATURE
+
+define void @foo() {
+entry:
+  ret void
+}
+
+; CHECK-OPTIONS: Function 'foo' uses ARM instructions, but the target does not support ARM mode execution.
+
+define void @no_thumb_mode_feature() #0 {
+entry:
+  ret void
+}
+
+; CHECK-FEATURE: Function 'no_thumb_mode_feature' uses ARM instructions, but the target does not support ARM mode execution.
+
+attributes #0 = { "target-features"="-thumb-mode" }