[COFF, ARM64, CodeView] Add support to emit CodeView debug info for ARM64 COFF

[ruiu]

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

307–308

Please fix style.

[mgrang]

I have a related question: Does it make sense to make -gcodeview the default for Windows COFF targets (both arm/arm64)? ie: clang would internally add -gcodeview if -g is passed.

[mgrang]

Addressed comment.

[rnk]

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

307–308

The old way of doing this supported emitting both dwarf and CV, which we briefly considered to be interesting. There isn't any real use case for it, but I think I'd prefer it if these things were independent. We shouldn't have a dwarf version flag if the frontend wants us to emit codeview.

[mgrang]

>> The old way of doing this supported emitting both dwarf and CV, which we briefly considered to be interesting. There isn't any real use case for it, but I think I'd prefer it if these things were independent. We shouldn't have a dwarf version flag if the frontend wants us to emit codeview.

@rnk So you mean adding an "else if" here is fine or should I revert this to the old way?

[majnemer]

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

308

Hrm, why isn't this just if (MMI->getModule()->getDwarfVersion()) ?

[mgrang]

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

308

In order to emit CodeView info for COFF, we need to pass -g -gcodeview. I wanted to make this an else-if since otherwise it will always emit Dwarf info as well (due to the presence of -g).

[rnk]

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

308

I don't think that'll happen, I don't see any "Dwarf Version" metadata when I run clang -S -emit-llvm -g -gcodeview t.c -o -.

[mgrang]

Reverted the change in AsmPrinter.cpp.

[rnk]

lgtm

include/llvm/DebugInfo/CodeView/CodeView.h

enum class CPUType : uint16_t {
   ARM4 = 0x61,
   ARM4T = 0x62,
   ARM5 = 0x63,
   ARM5T = 0x64,
   ARM6 = 0x65,
   ARM_XMAC = 0x66,
   ARM_WMMX = 0x67,
   ARM7 = 0x68,
+  ARM64 = 0x69,
   Omni = 0x70,
   Ia64 = 0x80,
   Ia64_2 = 0x81,
   CEE = 0x90,
   AM33 = 0xa0,
   M32R = 0xb0,
   TriCore = 0xc0,
   X64 = 0xd0,

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

bool AsmPrinter::doInitialization(Module &M) {
   if (MAI->doesSupportDebugInformation()) {
     bool EmitCodeView = MMI->getModule()->getCodeViewFlag();
     if (EmitCodeView && (TM.getTargetTriple().isKnownWindowsMSVCEnvironment() ||
                          TM.getTargetTriple().isWindowsItaniumEnvironment())) {
       Handlers.push_back(HandlerInfo(new CodeViewDebug(this),
                                      DbgTimerName, DbgTimerDescription,
                                      CodeViewLineTablesGroupName,
                                      CodeViewLineTablesGroupDescription));
     }
-    if (!EmitCodeView || MMI->getModule()->getDwarfVersion()) {
+    else if (!EmitCodeView || MMI->getModule()->getDwarfVersion()) {
       DD = new DwarfDebug(this, &M);
       DD->beginModule();
       Handlers.push_back(HandlerInfo(DD, DbgTimerName, DbgTimerDescription,
                                      DWARFGroupName, DWARFGroupDescription));
     }
   }
 
   switch (MAI->getExceptionHandlingType()) {

lib/CodeGen/AsmPrinter/CodeViewDebug.cpp

 static CPUType mapArchToCVCPUType(Triple::ArchType Type) {
   switch (Type) {
     case Triple::ArchType::x86:
       return CPUType::Pentium3;
     case Triple::ArchType::x86_64:
       return CPUType::X64;
     case Triple::ArchType::thumb:
       return CPUType::Thumb;
+    case Triple::ArchType::aarch64:
+      return CPUType::ARM64;
     default:
       report_fatal_error("target architecture doesn't map to a CodeView "
                          "CPUType");
   }
 }
 
 } // end anonymous namespace
 

lib/Target/AArch64/AArch64RegisterInfo.cpp

 #include "llvm/Target/TargetOptions.h"
 
 using namespace llvm;
 
 #define GET_REGINFO_TARGET_DESC
 #include "AArch64GenRegisterInfo.inc"
 
 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
-    : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
+    : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {
+  AArch64_MC::initLLVMToCVRegMapping(this);
+}
 
 const MCPhysReg *
 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   assert(MF && "Invalid MachineFunction pointer.");
   if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
     // GHC set of callee saved regs is empty as all those regs are
     // used for passing STG regs around
     return CSR_AArch64_NoRegs_SaveList;

lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp

AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) {
 
   HasIdentDirective = true;
 }
 
 AArch64MCAsmInfoCOFF::AArch64MCAsmInfoCOFF() {
   CommentString = ";";
   PrivateGlobalPrefix = ".L";
   PrivateLabelPrefix = ".L";
+  SupportsDebugInformation = true;
+  ExceptionsType = ExceptionHandling::WinEH;
 }

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
                                                  formatted_raw_ostream &OS,
                                                  MCInstPrinter *InstPrint,
                                                  bool isVerboseAsm);
 
 MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
                                                     const MCSubtargetInfo &STI);
 
+namespace AArch64_MC {
+void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
+}
+
 } // End llvm namespace
 
 // Defines symbolic names for AArch64 registers.  This defines a mapping from
 // register name to register number.
 //
 #define GET_REGINFO_ENUM
 #include "AArch64GenRegisterInfo.inc"
 

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

 static MCSubtargetInfo *
 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
   if (CPU.empty())
     CPU = "generic";
 
   return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
 }
 
+void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
+  for (unsigned Reg = AArch64::NoRegister + 1;
+       Reg < AArch64::NUM_TARGET_REGS; ++Reg) {
+    unsigned CV = MRI->getEncodingValue(Reg);
+    MRI->mapLLVMRegToCVReg(Reg, CV);
+  }
+}
+
 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitAArch64MCRegisterInfo(X, AArch64::LR);
+  AArch64_MC::initLLVMToCVRegMapping(X);
   return X;
 }
 
 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
                                          const Triple &TheTriple) {
   MCAsmInfo *MAI;
   if (TheTriple.isOSBinFormatMachO())
     MAI = new AArch64MCAsmInfoDarwin();

test/MC/AArch64/coff-debug.ll

+; RUN: llc -mtriple=aarch64-windows -filetype=obj -o - %s | \
+; RUN: llvm-readobj -codeview - | FileCheck %s
+
+; ModuleID = 'a.c'
+source_filename = "a.c"
+target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--windows-msvc18.0.0"
+
+; Function Attrs: noinline nounwind optnone
+define i32 @main() #0 !dbg !7 {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval, align 4
+  ret i32 1, !dbg !11
+}
+
+attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5}
+!llvm.ident = !{!6}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+!1 = !DIFile(filename: "a.c", directory: "/", checksumkind: CSK_MD5, checksum: "")
+!2 = !{}
+!3 = !{i32 2, !"CodeView", i32 1}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"wchar_size", i32 2}
+!6 = !{!"clang"}
+!7 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, isOptimized: false, unit: !0, variables: !2)
+!8 = !DISubroutineType(types: !9)
+!9 = !{!10}
+!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!11 = !DILocation(line: 2, column: 3, scope: !7)
+
+; CHECK: Format: COFF-ARM64
+; CHECK: Arch: aarch64
+; CHECK: AddressSize: 64bit
+; CHECK: CodeViewTypes [
+; CHECK:   Section: .debug$T (5)
+; CHECK:   Magic: 0x4
+; CHECK:   ArgList (0x1000) {
+; CHECK:     TypeLeafKind: LF_ARGLIST (0x1201)
+; CHECK:     NumArgs: 0
+; CHECK:     Arguments [
+; CHECK:     ]
+; CHECK:   }
+; CHECK:   Procedure (0x1001) {
+; CHECK:     TypeLeafKind: LF_PROCEDURE (0x1008)
+; CHECK:     ReturnType: int (0x74)
+; CHECK:     CallingConvention: NearC (0x0)
+; CHECK:     FunctionOptions [ (0x0)
+; CHECK:     ]
+; CHECK:     NumParameters: 0
+; CHECK:     ArgListType: () (0x1000)
+; CHECK:   }
+; CHECK:   FuncId (0x1002) {
+; CHECK:     TypeLeafKind: LF_FUNC_ID (0x1601)
+; CHECK:     ParentScope: 0x0
+; CHECK:     FunctionType: int () (0x1001)
+; CHECK:     Name: main
+; CHECK:   }
+; CHECK: ]
+; CHECK: CodeViewDebugInfo [
+; CHECK:   Section: .debug$S (4)
+; CHECK:   Magic: 0x4
+; CHECK:   Subsection [
+; CHECK:     SubSectionType: Symbols (0xF1)
+; CHECK:     Compile3Sym {
+; CHECK:       Kind: S_COMPILE3 (0x113C)
+; CHECK:       Language: C (0x0)
+; CHECK:       Flags [ (0x0)
+; CHECK:       ]
+; CHECK:     }
+; CHECK:   ]
+; CHECK:   Subsection [
+; CHECK:     SubSectionType: Symbols (0xF1)
+; CHECK:     GlobalProcIdSym {
+; CHECK:       Kind: S_GPROC32_ID (0x1147)
+; CHECK:       PtrParent: 0x0
+; CHECK:       PtrEnd: 0x0
+; CHECK:       PtrNext: 0x0
+; CHECK:       CodeSize: 0x14
+; CHECK:       DbgStart: 0x0
+; CHECK:       DbgEnd: 0x0
+; CHECK:       FunctionType: main (0x1002)
+; CHECK:       CodeOffset: main+0x0
+; CHECK:       Segment: 0x0
+; CHECK:       Flags [ (0x0)
+; CHECK:       ]
+; CHECK:       DisplayName: main
+; CHECK:       LinkageName: main
+; CHECK:     }
+; CHECK:     ProcEnd {
+; CHECK:       Kind: S_PROC_ID_END (0x114F)
+; CHECK:     }
+; CHECK:   ]
+; CHECK:   Subsection [
+; CHECK:     SubSectionType: Lines (0xF2)
+; CHECK:     LinkageName: main
+; CHECK:   ]
+; CHECK:   Subsection [
+; CHECK:     SubSectionType: FileChecksums (0xF4)
+; CHECK:     FileChecksum {
+; CHECK:       ChecksumSize: 0x0
+; CHECK:       ChecksumKind: None (0x0)
+; CHECK:       ChecksumBytes: ()
+; CHECK:     }
+; CHECK:   ]
+; CHECK:   Subsection [
+; CHECK:     SubSectionType: StringTable (0xF3)
+; CHECK:   ]
+; CHECK:   FunctionLineTable [
+; CHECK:     LinkageName: main
+; CHECK:     Flags: 0x1
+; CHECK:     CodeSize: 0x14
+; CHECK:     FilenameSegment [
+; CHECK:       +0x0 [
+; CHECK:         LineNumberStart: 1
+; CHECK:         LineNumberEndDelta: 0
+; CHECK:         IsStatement: No
+; CHECK:         ColStart: 0
+; CHECK:         ColEnd: 0
+; CHECK:       ]
+; CHECK:       +0x8 [
+; CHECK:         LineNumberStart: 2
+; CHECK:         LineNumberEndDelta: 0
+; CHECK:         IsStatement: No
+; CHECK:         ColStart: 3
+; CHECK:         ColEnd: 0
+; CHECK:       ]
+; CHECK:     ]
+; CHECK:   ]
+; CHECK: ]

tools/llvm-pdbutil/MinimalSymbolDumper.cpp

switch (Cpu) {
     RETURN_CASE(CPUType, ARM4, "arm 4");
     RETURN_CASE(CPUType, ARM4T, "arm 4t");
     RETURN_CASE(CPUType, ARM5, "arm 5");
     RETURN_CASE(CPUType, ARM5T, "arm 5t");
     RETURN_CASE(CPUType, ARM6, "arm 6");
     RETURN_CASE(CPUType, ARM_XMAC, "arm xmac");
     RETURN_CASE(CPUType, ARM_WMMX, "arm wmmx");
     RETURN_CASE(CPUType, ARM7, "arm 7");
+    RETURN_CASE(CPUType, ARM64, "arm64");
     RETURN_CASE(CPUType, Omni, "omni");
     RETURN_CASE(CPUType, Ia64, "intel itanium ia64");
     RETURN_CASE(CPUType, Ia64_2, "intel itanium ia64 2");
     RETURN_CASE(CPUType, CEE, "cee");
     RETURN_CASE(CPUType, AM33, "am33");
     RETURN_CASE(CPUType, M32R, "m32r");
     RETURN_CASE(CPUType, TriCore, "tri-core");
     RETURN_CASE(CPUType, X64, "intel x86-x64");