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[AArch64] Use 16 bytes as preferred function alignment on Cortex-A57.
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Authored by fhahn on Jul 3 2017, 8:54 AM.

Details

Summary

This change gives a 0.89% speed on execution time, a 0.94% improvement
in benchmark scores and a 0.62% increase in binary size on a Cortex-A57.
These numbers are the geomean results on a wide range of benchmarks from
the test-suite, SPEC2000, SPEC2006 and a range of proprietary suites.

The software optimization guide for the Cortex-A57 recommends 16 byte
branch alignment.

Diff Detail

Event Timeline

fhahn created this revision.Jul 3 2017, 8:54 AM
mcrosier resigned from this revision.Jul 6 2017, 10:17 AM

From a coding standpoint this all LGTM. However, I'm going to defer to a A57 code owner for final approval.

kristof.beyls accepted this revision.Jul 7 2017, 12:29 AM

LGTM from a Cortex-A57 point-of-view: this patch is generating code in line with the optimization guide recommendations and the benchmark numbers quoted look good.

This revision is now accepted and ready to land.Jul 7 2017, 12:29 AM
fhahn updated this revision to Diff 105614.Jul 7 2017, 3:37 AM

rebased

fhahn closed this revision.Jul 7 2017, 3:43 AM