[LLD][ELF] Introduce range extension thunks for ARM

[peter.smith]

Summary

This change adds initial support for range extension thunks. All thunks must be created within the first pass so some corner cases are not supported. A follow up patch will add support for multiple passes.

With this change the existing tests arm-branch-error.s and arm-thumb-branch-error.s now no longer fail with an out of range branch. These have been renamed and tests added for the range extension thunk.

This is patch 8/11 of range thunks. It is dependent on all previous patches D34690, D34689, D34688 and their transitive dependencies

[peter.smith]

Rebased, no other differences.

[ruiu]

ELF/Relocations.cpp

1020

Does this mean that this would use the upper bound if a referrer's address is greater than a thunk? Is it guaranteed that a thunk for this symbol is created within a range this way?

[peter.smith]

ELF/Relocations.cpp

1020

If I'm reading the expression correctly; if the address of the referrer is greater than the ThunkSection we can insert a Thunk into the ThunkSection if we are in range of its lower bound. If the address of the referrer is lower than that of the ThunkSection we need to be in range of its upper bound.

Given that we process referrers and ThunkSections in ascending order of address this should mean that on that pass we are in range.

referrer low (want to check that we are in range of upper bound of ThunkSection)
...
ThunkSection Base (TSBase lower bound)
    Thunks
ThunkSection Limit (TSLimit upper bound)
...
referrer high (want to check that we are in range of lower bound of ThunkSection)

[peter.smith]

Rebased diff on top of changes to D34689.

I'm planning to see how many test cases that I can take from D31665 and D31666 and will add them here as soon as I can.

[peter.smith]

Updated to add tests from D31665 and D31666.

[peter.smith]

Rebase to account for r308056 and r308057, no other changes.

[peter.smith]

Rebased to account for r309311 Merge OutputSectionCommand and OutputSection. No other changes.

[peter.smith]

Rebased to account for changes in D34689

[smeenai]

ELF/Arch/ARM.cpp

215–219

You should use LLVM_FALLTHROUGH.

226–230

Same here.

ELF/Relocations.cpp

1038

The changes in this function are just an NFC variable rename, and don't seem super related to this patch. You could upload them separately (or even just commit them directly).

1040

This assumes that IS->OutSecOff is in range of Src, correct?

If I understand correctly, you can insert a ThunkSection at the start or the end of an InputSection, but not in the middle. Over here, should we instead check if the start and the end of IS are in range of Src, use whichever one is in range, and raise an error if neither of them is?

1152–1153

Nits: The comma should be a semicolon, and there should be a period at the end.

1153–1154

Did clang-format do this? The combined line is under 80 chars, so I'm not sure why it would be split.

ELF/Thunks.cpp

253

Are the changes in this function related to this diff?

ELF/Writer.cpp

1283

This comment should be updated.

[peter.smith]

I've updated the diff with the review changes and a couple of new tests.

ELF/Relocations.cpp

1038

I've extracted these into D37627

1040

Agreed, I've made the change and I've added a couple of test cases for it.

1153–1154

I think I had run clang-format on the previous and next patch but not this one. I've now run it on this one.

ELF/Thunks.cpp

253

Yes they are. Thunks were previously only supported for branch (B, B.w) instructions as these cannot be transformed into a BLX for interworking. The change here permits BL and BLX instructions to have Thunks.

ELF/Writer.cpp

1283

I've removed it.

[peter.smith]

Rebase to account for changes In D34689 and D37627, no other changes.

[peter.smith]

Rebased on top of refactoring change D37743. No other changes.

[pcc]

ELF/Arch/ARM.cpp

215–219

This line needs a semicolon.

226–230

Same.

[peter.smith]

Thank you for pointing out the missing semicolons. I have updated the diff and rebased in light of recent refactoring changes.

[peter.smith]

Rebased in light of RelType refactoring, no other changes.

[ruiu]

LGTM

ELF/Relocations.h

136

Can you use RelType instead of uint32_t?

ELF/Arch/ARM.cpp

public:
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   void addPltSymbols(InputSectionBase *IS, uint64_t Off) const override;
   void addPltHeaderSymbols(InputSectionBase *ISD) const override;
   bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
-                  const SymbolBody &S) const override;
+                  uint64_t BranchAddr, const SymbolBody &S) const override;
   bool inBranchRange(uint32_t RelocType, uint64_t Src,
                      uint64_t Dst) const override;
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
 };
 } // namespace
 
 ARM::ARM() {
   CopyRel = R_ARM_COPY;

 
 void ARM::addPltSymbols(InputSectionBase *ISD, uint64_t Off) const {
   auto *IS = cast<InputSection>(ISD);
   addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS);
   addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS);
 }
 
 bool ARM::needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
-                     const SymbolBody &S) const {
+                     uint64_t BranchAddr, const SymbolBody &S) const {
   // If S is an undefined weak symbol in an executable we don't need a Thunk.
   // In a DSO calls to undefined symbols, including weak ones get PLT entries
   // which may need a thunk.
   if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak() &&
       !Config->Shared)
     return false;
   // A state change from ARM to Thumb and vice versa must go through an
   // interworking thunk if the relocation type is not R_ARM_CALL or
   // R_ARM_THM_CALL.
   switch (RelocType) {
   case R_ARM_PC24:
   case R_ARM_PLT32:
   case R_ARM_JUMP24:
     // Source is ARM, all PLT entries are ARM so no interworking required.
     // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
     if (Expr == R_PC && ((S.getVA() & 1) == 1))
       return true;
-    break;
+    // Fall through
+  case R_ARM_CALL: {
+    uint64_t Dst = (Expr == R_PLT_PC) ? S.getPltVA() : S.getVA();
+    return !inBranchRange(RelocType, BranchAddr, Dst);
+  }
   case R_ARM_THM_JUMP19:
   case R_ARM_THM_JUMP24:
     // Source is Thumb, all PLT entries are ARM so interworking is required.
     // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
     if (Expr == R_PLT_PC || ((S.getVA() & 1) == 0))
       return true;
-    break;
+    // Fall through
+  case R_ARM_THM_CALL: {
+    uint64_t Dst = (Expr == R_PLT_PC) ? S.getPltVA() : S.getVA();
+    return !inBranchRange(RelocType, BranchAddr, Dst);
+  }
   }
   return false;
 }
 
 bool ARM::inBranchRange(uint32_t RelocType, uint64_t Src, uint64_t Dst) const {
   uint64_t Range;
   uint64_t InstrSize;
   switch (RelocType) {

ELF/Arch/Mips.cpp

public:
   int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
   bool isPicRel(uint32_t Type) const override;
   uint32_t getDynRel(uint32_t Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
-                  const SymbolBody &S) const override;
+                  uint64_t BranchAddr, const SymbolBody &S) const override;
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   bool usesOnlyLowPageBits(uint32_t Type) const override;
 };
 } // namespace
 
 template <class ELFT> MIPS<ELFT>::MIPS() {
   GotPltHeaderEntriesNum = 2;
   DefaultMaxPageSize = 65536;
void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
   write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
   writeMipsHi16<E>(Buf, GotPltEntryAddr);
   writeMipsLo16<E>(Buf + 4, GotPltEntryAddr);
   writeMipsLo16<E>(Buf + 12, GotPltEntryAddr);
 }
 
 template <class ELFT>
 bool MIPS<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, const InputFile *File,
-                            const SymbolBody &S) const {
+                            uint64_t BranchAddr, const SymbolBody &S) const {
   // Any MIPS PIC code function is invoked with its address in register $t9.
   // So if we have a branch instruction from non-PIC code to the PIC one
   // we cannot make the jump directly and need to create a small stubs
   // to save the target function address.
   // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
   if (Type != R_MIPS_26)
     return false;
   auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);

ELF/Relocations.h

public:
 
   // The number of completed passes of createThunks this permits us
   // to do one time initialization on Pass 0 and put a limit on the
   // number of times it can be called to prevent infinite loops.
   uint32_t Pass = 0;
 
 private:
   void mergeThunks();
-  ThunkSection *getISRThunkSec(OutputSection *OS,
-                               std::vector<InputSection *> *ISR);
+  ThunkSection *getISRThunkSec(OutputSection *OS, InputSection *IS,
+                               std::vector<InputSection *> *ISR, uint32_t Type,
+                               uint64_t Src);
   ThunkSection *getISThunkSec(InputSection *IS, OutputSection *OS);
   void
   createInitialThunkSections(ArrayRef<OutputSectionCommand *> OutputSections);
   void forEachExecInputSection(
       ArrayRef<OutputSectionCommand *> OutputSections,
       std::function<void(OutputSection *, std::vector<InputSection *> *,
                          InputSection *)>
           Fn);
-  std::pair<Thunk *, bool> getThunk(SymbolBody &Body, uint32_t Type);
+  std::pair<Thunk *, bool> getThunk(SymbolBody &Body, uint32_t Type,
+                                    uint64_t Src);
   ThunkSection *addThunkSection(OutputSection *OS,
                                 std::vector<InputSection *> *, uint64_t Off);
   // Record all the available Thunks for a Symbol
   llvm::DenseMap<SymbolBody *, std::vector<Thunk *>> ThunkedSymbols;
 
   // Find a Thunk from the Thunks symbol definition, we can use this to find
   // the Thunk from a relocation to the Thunks symbol definition.
   llvm::DenseMap<SymbolBody *, Thunk *> Thunks;

ELF/Relocations.cpp

auto MergeCmp = [](const InputSection *A, const InputSection *B) {
       return false;
     };
     std::merge(ISR->begin(), ISR->end(), Thunks.begin(), Thunks.end(),
                std::back_inserter(Tmp), MergeCmp);
     *ISR = std::move(Tmp);
   }
 }
 
-ThunkSection *ThunkCreator::getISRThunkSec(OutputSection *OS,
-                                           std::vector<InputSection *> *ISR) {
-  // FIXME: When range extension thunks are supported we will need to check
-  // that the ThunkSection is in range of the caller
-  for (ThunkSection *TS : ThunkSections[ISR])
+ThunkSection *ThunkCreator::getISRThunkSec(OutputSection *OS, InputSection *IS,
+                                           std::vector<InputSection *> *ISR,
+                                           uint32_t Type, uint64_t Src) {
+  // Use the simple heuristic of inserting the Thunk in the first ThunkSection
+  // in range of the caller.
+  for (ThunkSection *TS : ThunkSections[ISR]) {
+    uint64_t TSBase = OS->Addr + TS->OutSecOff;
+    uint64_t TSLimit = TSBase + TS->getSize();
+    if (Target->inBranchRange(Type, Src, (Src > TSLimit) ? TSBase : TSLimit))
       return TS;
+  }
 
-  // FIXME: When range extension thunks are supported we must handle the case
-  // where no pre-created ThunkSections are in range by creating a new one in
-  // range for now it is unreachable
-  llvm_unreachable("Must have created at least one ThunkSection per ISR");
+  // No suitable ThunkSection exists. This can happen when there is a branch
+  // with lower range than the ThunkSection spacing or when there are too
+  // many Thunks. Create a new ThunkSection.
+  return addThunkSection(OS, ISR, IS->OutSecOff);
 }
 
 ThunkSection *ThunkCreator::getISThunkSec(InputSection *IS, OutputSection *OS) {
   ThunkSection *TS = ThunkedSections.lookup(IS);
   if (TS)
     return TS;
   auto *TOS = IS->getParent();
 
   // Find InputSectionRange within TOS that IS is in
   OutputSectionCommand *C = Script->getCmd(TOS);
   std::vector<InputSection *> *Range = nullptr;
   for (BaseCommand *BC : C->Commands)
-    if (auto *ISD = dyn_cast<InputSectionDescription> (BC)) {
+    if (auto *ISD = dyn_cast<InputSectionDescription>(BC)) {
       InputSection *first = ISD->Sections.front();
       InputSection *last = ISD->Sections.back();
       if (IS->OutSecOff >= first->OutSecOff &&
           IS->OutSecOff <= last->OutSecOff) {
         Range = &ISD->Sections;
         break;
       }
     }
ThunkSection *ThunkCreator::addThunkSection(OutputSection *OS,
                                             std::vector<InputSection *> *ISR,
                                             uint64_t Off) {
   auto *TS = make<ThunkSection>(OS, Off);
   ThunkSections[ISR].push_back(TS);
   return TS;
 }
 
 std::pair<Thunk *, bool> ThunkCreator::getThunk(SymbolBody &Body,
-                                                uint32_t Type) {
+                                                uint32_t Type,
+                                                uint64_t Src) {
   auto Res = ThunkedSymbols.insert({&Body, std::vector<Thunk *>()});
   if (!Res.second) {
     // Check existing Thunks for Body to see if they can be reused
     for (Thunk *ET : Res.first->second)
-      if (ET->compatibleWith(Type))
+      if (ET->compatibleWith(Type) &&
+          Target->inBranchRange(Type, Src, ET->ThunkSym->getVA()))
         return {ET, false};
   }
   // No existing compatible Thunk in range, create a new one
   Thunk *T = addThunk(Type, Body);
   Res.first->second.push_back(T);
   return {T, true};
 }
 

 // Process all relocations from the InputSections that have been assigned
 // to OutputSections and redirect through Thunks if needed.
 //
 // createThunks must be called after scanRelocs has created the Relocations for
 // each InputSection. It must be called before the static symbol table is
 // finalized. If any Thunks are added to an OutputSection the output section
 // offsets of the InputSections will change.
 //
-// FIXME: All Thunks are assumed to be in range of the relocation. Range
-// extension Thunks are not yet supported.
+// FIXME: Initial support for RangeThunks, only one pass supported
 bool ThunkCreator::createThunks(
     ArrayRef<OutputSectionCommand *> OutputSections) {
   if (Pass > 0)
     ThunkSections.clear();
   else if (Target->ThunkSectionSpacing)
     createInitialThunkSections(OutputSections);
 
   // Create all the Thunks and insert them into synthetic ThunkSections. The
   // ThunkSections are later inserted back into the OutputSection.
 
   // We separate the creation of ThunkSections from the insertion of the
   // ThunkSections back into the OutputSection as ThunkSections are not always
   // inserted into the same OutputSection as the caller.
   forEachExecInputSection(
       OutputSections, [&](OutputSection *OS,  std::vector<InputSection*> *ISR,
                           InputSection *IS) {
         for (Relocation &Rel : IS->Relocations) {
           SymbolBody &Body = *Rel.Sym;
+          uint64_t Src = OS->Addr + IS->OutSecOff + Rel.Offset;
           if (Thunks.find(&Body) != Thunks.end() ||
-              !Target->needsThunk(Rel.Expr, Rel.Type, IS->File, Body))
+              !Target->needsThunk(Rel.Expr, Rel.Type, IS->File, Src, Body))
             continue;
           Thunk *T;
           bool IsNew;
-          std::tie(T, IsNew) = getThunk(Body, Rel.Type);
+          std::tie(T, IsNew) = getThunk(Body, Rel.Type, Src);
           if (IsNew) {
             // Find or create a ThunkSection for the new Thunk
             ThunkSection *TS;
             if (auto *TIS = T->getTargetInputSection())
               TS = getISThunkSec(TIS, OS);
             else
-              TS = getISRThunkSec(OS, ISR);
+              TS = getISRThunkSec(OS, IS, ISR, Rel.Type, Src);
             TS->addThunk(T);
             Thunks[T->ThunkSym] = T;
           }
           // Redirect relocation to Thunk, we never go via the PLT to a Thunk
           Rel.Sym = T->ThunkSym;
           Rel.Expr = fromPlt(Rel.Expr);
         }
       });

ELF/Target.h

public:
   // only uses the low 12 bits in a system with 4k pages. If this is true, the
   // bits will always have the same value at runtime and we don't have to emit
   // a dynamic relocation.
   virtual bool usesOnlyLowPageBits(uint32_t Type) const;
 
   // Decide whether a Thunk is needed for the relocation from File
   // targeting S.
   virtual bool needsThunk(RelExpr Expr, uint32_t RelocType,
-                          const InputFile *File, const SymbolBody &S) const;
+                          const InputFile *File, uint64_t BranchAddr,
+                          const SymbolBody &S) const;
   // Return true if we can reach Dst from Src with Relocation RelocType
   virtual bool inBranchRange(uint32_t RelocType, uint64_t Src,
                              uint64_t Dst) const;
   virtual RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
                              const uint8_t *Loc) const = 0;
   virtual void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const = 0;
   virtual ~TargetInfo();
 

ELF/Target.cpp

 
 int64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
   return 0;
 }
 
 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; }
 
 bool TargetInfo::needsThunk(RelExpr Expr, uint32_t RelocType,
-                            const InputFile *File, const SymbolBody &S) const {
+                            const InputFile *File, uint64_t BranchAddr,
+                            const SymbolBody &S) const {
   return false;
 }
 
 bool TargetInfo::inBranchRange(uint32_t RelocType, uint64_t Src,
                                uint64_t Dst) const {
   return true;
 }
 

ELF/Thunks.cpp

 static Thunk *addThunkArm(uint32_t Reloc, SymbolBody &S) {
   // ARM relocations need ARM to Thumb interworking Thunks.
   // Thumb relocations need Thumb to ARM relocations.
   // Use position independent Thunks if we require position independent code.
   switch (Reloc) {
   case R_ARM_PC24:
   case R_ARM_PLT32:
   case R_ARM_JUMP24:
+  case R_ARM_CALL:
     if (Config->Pic)
       return make<ARMV7PILongThunk>(S);
     return make<ARMV7ABSLongThunk>(S);
   case R_ARM_THM_JUMP19:
   case R_ARM_THM_JUMP24:
+  case R_ARM_THM_CALL:
     if (Config->Pic)
       return make<ThumbV7PILongThunk>(S);
     return make<ThumbV7ABSLongThunk>(S);
   }
   fatal("unrecognized relocation type");
 }
 
 static Thunk *addThunkMips(SymbolBody &S) {

ELF/Writer.cpp

applySynthetic({InX::DynSymTab,    InX::Bss,           InX::BssRelRo,
                   InX::Plt,          InX::Iplt,          In<ELFT>::EhFrameHdr,
                   In<ELFT>::VerSym,  In<ELFT>::VerNeed,  InX::Dynamic},
                  [](SyntheticSection *SS) { SS->finalizeContents(); });
 
   // Some architectures use small displacements for jump instructions.
   // It is linker's responsibility to create thunks containing long
   // jump instructions if jump targets are too far. Create thunks.
   if (Target->NeedsThunks) {
     // FIXME: only ARM Interworking and Mips LA25 Thunks are implemented,
     // these
     // do not require address information. To support range extension Thunks
     // we need to assign addresses so that we can tell if jump instructions
     // are out of range. This will need to turn into a loop that converges
     // when no more Thunks are added
     ThunkCreator TC;
     Script->assignAddresses();
     if (TC.createThunks(OutputSectionCommands)) {
       applySynthetic({InX::MipsGot},
                      [](SyntheticSection *SS) { SS->updateAllocSize(); });
+      Script->assignAddresses();
       if (TC.createThunks(OutputSectionCommands))
         fatal("All non-range thunks should be created in first call");
     }
   }
 
   // Fill other section headers. The dynamic table is finalized
   // at the end because some tags like RELSZ depend on result
   // of finalizing other sections.

test/ELF/arm-branch-error.s

-// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
-// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/far-arm-abs.s -o %tfar
-// RUN: not ld.lld  %t %tfar -o %t2 2>&1 | FileCheck %s
-// REQUIRES: arm
- .syntax unified
- .section .text, "ax",%progbits
- .globl _start
- .balign 0x10000
- .type _start,%function
-_start:
- // address of too_far symbols are just out of range of ARM branch with
- // 26-bit immediate field and an addend of -8
- bl  too_far1
- b   too_far2
- beq too_far3
-
-// CHECK: R_ARM_CALL out of range
-// CHECK-NEXT: R_ARM_JUMP24 out of range
-// CHECK-NEXT: R_ARM_JUMP24 out of range

test/ELF/arm-branch-rangethunk.s

+// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
+// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/far-arm-abs.s -o %tfar
+// RUN: ld.lld  %t %tfar -o %t2 2>&1
+// RUN: llvm-objdump -d -triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
+// REQUIRES: arm
+ .syntax unified
+ .section .text, "ax",%progbits
+ .globl _start
+ .balign 0x10000
+ .type _start,%function
+_start:
+ // address of too_far symbols are just out of range of ARM branch with
+ // 26-bit immediate field and an addend of -8
+ bl  too_far1
+ b   too_far2
+ beq too_far3
+
+// CHECK: Disassembly of section .text:
+// CHECK-NEXT: _start:
+// CHECK-NEXT:    20000:       01 00 00 eb     bl      #4 <__ARMv7ABSLongThunk_too_far1>
+// CHECK-NEXT:    20004:       03 00 00 ea     b       #12 <__ARMv7ABSLongThunk_too_far2>
+// CHECK-NEXT:    20008:       05 00 00 0a     beq     #20 <__ARMv7ABSLongThunk_too_far3>
+// CHECK: __ARMv7ABSLongThunk_too_far1:
+// CHECK-NEXT:    2000c:       08 c0 00 e3     movw    r12, #8
+// CHECK-NEXT:    20010:       02 c2 40 e3     movt    r12, #514
+// CHECK-NEXT:    20014:       1c ff 2f e1     bx      r12
+// CHECK: __ARMv7ABSLongThunk_too_far2:
+// CHECK-NEXT:    20018:       0c c0 00 e3     movw    r12, #12
+// CHECK-NEXT:    2001c:       02 c2 40 e3     movt    r12, #514
+// CHECK-NEXT:    20020:       1c ff 2f e1     bx      r12
+// CHECK: __ARMv7ABSLongThunk_too_far3:
+// CHECK-NEXT:    20024:       10 c0 00 e3     movw    r12, #16
+// CHECK-NEXT:    20028:       02 c2 40 e3     movt    r12, #514
+// CHECK-NEXT:    2002c:       1c ff 2f e1     bx      r12

test/ELF/arm-thumb-branch-error.s

-// RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
-// RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %S/Inputs/far-arm-thumb-abs.s -o %tfar
-// RUN: not ld.lld  %t %tfar -o %t2 2>&1 | FileCheck %s
-// REQUIRES: arm
- .syntax unified
- .section .text, "ax",%progbits
- .globl _start
- .balign 0x10000
- .type _start,%function
-_start:
- // address of too_far symbols are just out of range of ARM branch with
- // 26-bit immediate field and an addend of -8
- bl  too_far1
- b   too_far2
- beq.w too_far3
-
-// CHECK: R_ARM_THM_CALL out of range
-// CHECK-NEXT: R_ARM_THM_JUMP24 out of range
-// CHECK-NEXT: R_ARM_THM_JUMP19 out of range

test/ELF/arm-thumb-branch-rangethunk.s

+// RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
+// RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %S/Inputs/far-arm-thumb-abs.s -o %tfar
+// RUN: ld.lld  %t %tfar -o %t2 2>&1
+// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2
+// REQUIRES: arm
+ .syntax unified
+ .thumb
+ .section .text, "ax",%progbits
+ .globl _start
+ .balign 0x10000
+ .type _start,%function
+_start:
+ // address of too_far symbols are just out of range of ARM branch with
+ // 26-bit immediate field and an addend of -8
+ bl  too_far1
+ b   too_far2
+ beq.w too_far3
+
+// CHECK: Disassembly of section .text:
+// CHECK-NEXT: _start:
+// CHECK-NEXT:    20000:       00 f0 04 f8     bl      #8
+// CHECK-NEXT:    20004:       00 f0 07 b8     b.w     #14 <__Thumbv7ABSLongThunk_too_far2>
+// CHECK-NEXT:    20008:       00 f0 0a 80     beq.w   #20 <__Thumbv7ABSLongThunk_too_far3>
+// CHECK: __Thumbv7ABSLongThunk_too_far1:
+// CHECK-NEXT:    2000c:       40 f2 05 0c     movw    r12, #5
+// CHECK-NEXT:    20010:       c0 f2 02 1c     movt    r12, #258
+// CHECK-NEXT:    20014:       60 47   bx      r12
+// CHECK: __Thumbv7ABSLongThunk_too_far2:
+// CHECK-NEXT:    20016:       40 f2 09 0c     movw    r12, #9
+// CHECK-NEXT:    2001a:       c0 f2 02 1c     movt    r12, #258
+// CHECK-NEXT:    2001e:       60 47   bx      r12
+// CHECK: __Thumbv7ABSLongThunk_too_far3:
+// CHECK-NEXT:    20020:       40 f2 0d 0c     movw    r12, #13
+// CHECK-NEXT:    20024:       c0 f2 12 0c     movt    r12, #18
+// CHECK-NEXT:    20028:       60 47   bx      r12
+// CHECK-NEXT:    2002a:       00 00   movs    r0, r0