[ARM] - Add the option to directly access TLS pointer

[spetrovic]

Summary

This patch enables choice for accessing thread local storage pointer (like '-mtp' in gcc).
The values are:
'-mtp=soft': generate call to __aeabi_read_tp() - before this patch this was the only way to access the pointer, and it remains default.
'-mtp=cp15': read the pointer directly from coprocessor cp15, with 'mrc' instruction.

[t.p.northover]

I think this fits in better as a subtarget feature controlled by "-mattr". The implementation could then be almost all in TableGen, just using different patterns for ARMthread_pointer (giving greater symmetry with the existing path). It would also make it much neater to pipe through to clang.

test/CodeGen/ARM/readtp.ll

22

Isn't the actual register a pretty critical ABI issue?

[spetrovic]

Comments addressed. I'm also preparing new patch for clang.

[t.p.northover]

Thanks Strahinja, this looks good to me.

[nickdesaulniers]

Follow up: https://reviews.llvm.org/D112600

lib/Target/ARM/ARMISelLowering.h

 #include "llvm/Target/TargetLowering.h"
 #include <utility>
 
 namespace llvm {
 
 class ARMSubtarget;
 class InstrItineraryData;
 
+enum ReadTPMode {
+      Soft,
+      Cp15
+};
+
   namespace ARMISD {
 
     // ARM Specific DAG Nodes
     enum NodeType : unsigned {
       // Start the numbering where the builtin ops and target ops leave off.
       FIRST_NUMBER = ISD::BUILTIN_OP_END,
 
       Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,

lib/Target/ARM/ARMISelLowering.cpp

 static cl::opt<unsigned> ConstpoolPromotionMaxSize(
     "arm-promote-constant-max-size", cl::Hidden,
     cl::desc("Maximum size of constant to promote into a constant pool"),
     cl::init(64));
 static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
     "arm-promote-constant-max-total", cl::Hidden,
     cl::desc("Maximum size of ALL constants to promote into a constant pool"),
     cl::init(128));
+static cl::opt<ReadTPMode> ReadThreadPointer(
+    "mtp", cl::Hidden, cl::init(ReadTPMode::Soft),
+    cl::values(clEnumValN(ReadTPMode::Soft, "soft",
+                          "Soft reading of thread pointer"),
+               clEnumValN(ReadTPMode::Cp15, "cp15",
+                          "Read thread pointer from register")),
+    cl::desc("The way of reading thread pointer"));
 
 // The APCS parameter registers.
 static const MCPhysReg GPRArgRegs[] = {
   ARM::R0, ARM::R1, ARM::R2, ARM::R3
 };
 
 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
                                        MVT PromotedBitwiseVT) {
ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
                                         SelectionDAG &DAG,
                                         TLSModel::Model model) const {
   const GlobalValue *GV = GA->getGlobal();
   SDLoc dl(GA);
   SDValue Offset;
   SDValue Chain = DAG.getEntryNode();
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   // Get the Thread Pointer
-  SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
+  SDValue ThreadPointer;
+  // Get the Thread Pointer
+  if (ReadThreadPointer == ReadTPMode::Soft)
+    ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
+  else if (ReadThreadPointer == ReadTPMode::Cp15) {
+    SDValue Ops[] = {Chain,
+                     DAG.getConstant(Intrinsic::arm_mrc, dl, MVT::i32),
+                     DAG.getConstant(15, dl, MVT::i32),
+                     DAG.getConstant(0, dl, MVT::i32),
+                     DAG.getConstant(13, dl, MVT::i32),
+                     DAG.getConstant(0, dl, MVT::i32),
+                     DAG.getConstant(3, dl, MVT::i32)};
+    ThreadPointer = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl,
+                                DAG.getVTList(MVT::i32, MVT::Other), Ops);
+  }
 
   if (model == TLSModel::InitialExec) {
     MachineFunction &MF = DAG.getMachineFunction();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
     // Initial exec model.
     unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
     ARMConstantPoolValue *CPV =

test/CodeGen/ARM/readtp.ll

+; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 -mtp=cp15 %s -o - | FileCheck %s -check-prefix=CHECK-HARD
+; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 -mtp=soft %s -o - | FileCheck %s -check-prefix=CHECK-SOFT
+; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 %s -o - | FileCheck %s -check-prefix=CHECK-DEFAULT
+
+
+; volatile __thread int counter;
+; void foo(int argc, char** argh) {
+;   counter = 5;
+; }
+
+
+@counter = thread_local global i32 0, align 4
+
+define void @foo()  {
+entry:
+  store volatile i32 5, i32* @counter, align 4
+  ret void
+}
+
+
+; CHECK-LABEL: foo:
+; CHECK-HARD:    mrc  p15, #0, {{r[0-9]+}}, {{c[0-9]+}}, {{c[0-9]+}}, #3
+; CHECK-SOFT:    bl __aeabi_read_tp
+; CHECK-DEFAULT: bl __aeabi_read_tp
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