[ARM] - Add the option to directly access TLS pointer

[spetrovic]

Summary

This patch enables choice for accessing thread local storage pointer (like '-mtp' in gcc).
The values are:
'-mtp=soft': generate call to __aeabi_read_tp() - before this patch this was the only way to access the pointer, and it remains default.
'-mtp=cp15': read the pointer directly from coprocessor cp15, with 'mrc' instruction.

[t.p.northover]

I think this fits in better as a subtarget feature controlled by "-mattr". The implementation could then be almost all in TableGen, just using different patterns for ARMthread_pointer (giving greater symmetry with the existing path). It would also make it much neater to pipe through to clang.

test/CodeGen/ARM/readtp.ll

22 ↗

(On Diff #103223)

Isn't the actual register a pretty critical ABI issue?

[spetrovic]

Comments addressed. I'm also preparing new patch for clang.

[t.p.northover]

Thanks Strahinja, this looks good to me.

[nickdesaulniers]

Follow up: https://reviews.llvm.org/D112600

llvm/trunk/lib/Target/ARM/ARM.td

 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
                                              "Enable fast computation of "
                                              "positive address offsets">;
 
 // Fast execution of AES crypto operations
 def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
                                              "CPU fuses AES crypto operations">;
 
+// The way of reading thread pointer                                             
+def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
+                                      "Reading thread pointer from register">;
+
 // Cyclone can zero VFP registers in 0 cycles.
 def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
                                              "Has zero-cycle zeroing instructions">;
 
 // Whether it is profitable to unpredicate certain instructions during if-conversion
 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
                                               "IsProfitableToUnpredicate", "true",
                                               "Is profitable to unpredicate">;

llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

def IsNotMClass      : Predicate<"!Subtarget->isMClass()">,
                                                     "!armv*m">;
 def IsARM            : Predicate<"!Subtarget->isThumb()">,
                                  AssemblerPredicate<"!ModeThumb", "arm-mode">;
 def IsMachO          : Predicate<"Subtarget->isTargetMachO()">;
 def IsNotMachO       : Predicate<"!Subtarget->isTargetMachO()">;
 def IsNaCl           : Predicate<"Subtarget->isTargetNaCl()">;
 def IsWindows        : Predicate<"Subtarget->isTargetWindows()">;
 def IsNotWindows     : Predicate<"!Subtarget->isTargetWindows()">;
+def IsReadTPHard     : Predicate<"Subtarget->isReadTPHard()">;
+def IsReadTPSoft     : Predicate<"!Subtarget->isReadTPHard()">;
 def UseNaClTrap      : Predicate<"Subtarget->useNaClTrap()">,
                                  AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
 def DontUseNaClTrap  : Predicate<"!Subtarget->useNaClTrap()">;
 
 def UseNegativeImmediates :
   Predicate<"false">,
             AssemblerPredicate<"!FeatureNoNegativeImmediates",
                                "NegativeImmediates">;

 // __aeabi_read_tp preserves the registers r1-r3.
 // This is a pseudo inst so that we can get the encoding right,
 // complete with fixup for the aeabi_read_tp function.
 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
 // is defined in "ARMInstrThumb.td".
 let isCall = 1,
   Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
   def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
-               [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
+               [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>,
+               Requires<[IsARM, IsReadTPSoft]>;
 }
 
+// Reading thread pointer from coprocessor register
+def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>,
+      Requires<[IsARM, IsReadTPHard]>;
+
 //===----------------------------------------------------------------------===//
 // SJLJ Exception handling intrinsics
 //   eh_sjlj_setjmp() is an instruction sequence to store the return
 //   address and save #0 in R0 for the non-longjmp case.
 //   Since by its nature we may be coming from some other function to get
 //   here, and we're using the stack frame for the containing function to
 //   save/restore registers, we can't keep anything live in regs across
 //   the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

protected:
   bool DontWidenVMOVS = false;
 
   /// If true, run the MLx expansion pass.
   bool ExpandMLx = false;
 
   /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
   bool HasVMLxHazards = false;
 
+  // If true, read thread pointer from coprocessor register.
+  bool ReadTPHard = false;
+
   /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
   bool UseNEONForFPMovs = false;
 
   /// If true, VLDn instructions take an extra cycle for unaligned accesses.
   bool CheckVLDnAlign = false;
 
   /// If true, VFP instructions are not pipelined.
   bool NonpipelinedVFP = false;
public:
   bool useSoftFloat() const { return UseSoftFloat; }
   bool isThumb() const { return InThumbMode; }
   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
   bool isThumb2() const { return InThumbMode && HasThumb2; }
   bool hasThumb2() const { return HasThumb2; }
   bool isMClass() const { return ARMProcClass == MClass; }
   bool isRClass() const { return ARMProcClass == RClass; }
   bool isAClass() const { return ARMProcClass == AClass; }
+  bool isReadTPHard() const { return ReadTPHard; }
 
   bool isR9Reserved() const {
     return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
   }
 
   bool useR7AsFramePointer() const {
     return isTargetDarwin() || (!isTargetWindows() && isThumb());
   }

llvm/trunk/test/CodeGen/ARM/readtp.ll

+; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 -mattr=+read-tp-hard %s -o - | FileCheck %s -check-prefix=CHECK-HARD
+; RUN: llc -mtriple=armeb-linux-gnueabihf -O2 %s -o - | FileCheck %s -check-prefix=CHECK-SOFT
+
+
+; __thread int counter;
+;  void foo() {
+;    counter = 5;
+;  }
+
+
+@counter = thread_local local_unnamed_addr global i32 0, align 4
+
+define void @foo() local_unnamed_addr #0 {
+entry:
+  store i32 5, i32* @counter, align 4
+  ret void
+}
+
+
+; CHECK-LABEL: foo:
+; CHECK-HARD:    mrc  p15, #0, {{r[0-9]+}}, c13, c0, #3
+; CHECK-SOFT:    bl __aeabi_read_tp
 No newline at end of file