[AArch64] PointerRegClass should be GPR64spRegClass

[kongyi]

Summary

XZR cannot be used to hold pointers, while SP can. Change the pointer register class from GPR64RegClass to GPR64spRegClass, which includes SP but excludes XZR.

[efriedma]

Testcase? (I think this affects inline asm.)

[kongyi]

In D34368#784693, @efriedma wrote:

Testcase? (I think this affects inline asm.)

This change is actually laying ground for fixing an inline asm bug (PR33134). Test cases will be added along with rest of the fix in a follow up change.

[kristof.beyls]

In D34368#784700, @kongyi wrote:

In D34368#784693, @efriedma wrote:

Testcase? (I think this affects inline asm.)

This change is actually laying ground for fixing an inline asm bug (PR33134). Test cases will be added along with rest of the fix in a follow up change.

This seems to be a fix for a correctness bug. If you do have a follow-up change that will have test cases that demonstrate this fixes things, maybe it's best to combine this change with the follow up change, especially since this patch is a single-line change?

[kongyi]

Will combine the changes into a single patch.

lib/Target/AArch64/AArch64RegisterInfo.cpp

 
 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
   return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
 }
 
 const TargetRegisterClass *
 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
                                       unsigned Kind) const {
-  return &AArch64::GPR64RegClass;
+  return &AArch64::GPR64spRegClass;
 }
 
 const TargetRegisterClass *
 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
   if (RC == &AArch64::CCRRegClass)
     return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
   return RC;
 }