[DAGCombiner] Add another combine from build vector to shuffle

[guyblank]

Summary

The patch adds support for combining a build vector to a shuffle.
When the build vector is of extracted elements from 2 vectors (vec1, vec2) where vec2 is 2 times smaller than vec1. Without the patch this would generate a bunch of extract/insert.

Not sure if the changed AArch64 test got better or worse though...

[RKSimon]

test/CodeGen/X86/vector-shuffle-v48.ll

39

Why do you have all this extra code (zext/mul/lshr/trunc)? Isn't the problem just in the shufflevector?

[delena]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14010

In the case above you'll find (VT.getSizeInBits() % InVT1.getSizeInBits() == 0). Is this your case
(VT.getSizeInBits() % InVT2.getSizeInBits() == 0) ?

[guyblank]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14010

The case in line 13962 also checks that InVT1 == InVT2.

if ((VT.getSizeInBits() % InVT1.getSizeInBits() == 0) && InVT1 == InVT2)

It then concats InVT1,InVT2 and a bunch of undef vectors to reach the size of VT.
The shuffle will be on the result of the concats and an undef vector of the same size.

In the case i've added, InVT2 is smaller than InVT1. So it is concated with undef to reach the size of InVT1 and VT.
The shuffle will be on InVT1 and the result of the concat.

test/CodeGen/X86/vector-shuffle-v48.ll

39

specifically in this case it causes the build vector result to be v32i8, and be caught by the if i've added.
but i should probably change the shufflevector to just return <32 x i8>, since it would demonstrate the issue as well, without the extra code.

Thanks!

[guyblank]

rebased after updating the test case

[guyblank]

ping

[guyblank]

Closed by commit rL305883: [DAGCombiner] Add another combine from build vector to shuffle

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if ((VT.getSizeInBits() % InVT1.getSizeInBits() == 0) && InVT1 == InVT2) {
         }
         ShuffleNumElems = NumElems * 2;
       } else {
         // Both VecIn1 and VecIn2 are wider than the output, and VecIn2 is wider
         // than VecIn1. We can't handle this for now - this case will disappear
         // when we start sorting the vectors by type.
         return SDValue();
       }
+    } else if (InVT2.getSizeInBits() * 2 == VT.getSizeInBits() &&
+               InVT1.getSizeInBits() == VT.getSizeInBits()) {
+      SmallVector<SDValue, 2> ConcatOps(2, DAG.getUNDEF(InVT2));
+      ConcatOps[0] = VecIn2;
+      VecIn2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
     } else {
       // TODO: Support cases where the length mismatch isn't exactly by a
       // factor of 2.
       // TODO: Move this check upwards, so that if we have bad type
       // mismatches, we don't create any DAG nodes.
       return SDValue();
     }
   }

test/CodeGen/AArch64/arm64-neon-copy.ll

entry:
   %vecext = extractelement <1 x i64> %x, i32 0
   %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
   %vecinit2 = shufflevector <2 x i64> %vecinit, <2 x i64> %y, <2 x i32> <i32 0, i32 2>
   ret <2 x i64> %vecinit2
 }
 
 define <2 x i64> @test_concat_v2i64_v2i64_v1i64(<2 x i64> %x, <1 x i64> %y) #0 {
 ; CHECK-LABEL: test_concat_v2i64_v2i64_v1i64:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
 entry:
   %vecext = extractelement <2 x i64> %x, i32 0
   %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
   %vecext1 = extractelement <1 x i64> %y, i32 0
   %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
   ret <2 x i64> %vecinit2
 }
 

test/CodeGen/X86/vector-shuffle-v48.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-pc-linux  -mattr=+avx2 < %s | FileCheck %s
 define <16 x i8> @foo(<48 x i8>* %x0, <16 x i32> %x1, <16 x i32> %x2) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmovdqu (%rdi), %ymm4
-; CHECK-NEXT:    vmovdqu 32(%rdi), %xmm5
-; CHECK-NEXT:    vpextrb $13, %xmm5, %eax
-; CHECK-NEXT:    vpextrb $10, %xmm5, %ecx
-; CHECK-NEXT:    vpextrb $7, %xmm5, %edx
-; CHECK-NEXT:    vpextrb $4, %xmm5, %esi
-; CHECK-NEXT:    vpextrb $1, %xmm5, %edi
-; CHECK-NEXT:    vextracti128 $1, %ymm4, %xmm5
-; CHECK-NEXT:    vpshufb {{.*#+}} xmm6 = xmm5[2,2,5,5,5,5,3,3,4,4,5,5,6,6,7,7]
-; CHECK-NEXT:    vpshufb {{.*#+}} xmm7 = xmm4[12,12,13,13,15,15,15,15,12,12,13,13,14,14,15,15]
-; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
-; CHECK-NEXT:    vpshufb {{.*#+}} xmm4 = xmm4[0,0,1,1,3,3,3,3,6,6,9,9,9,9,7,7]
-; CHECK-NEXT:    vinserti128 $1, %xmm6, %ymm4, %ymm4
+; CHECK-NEXT:    vmovdqu 32(%rdi), %xmm8
+; CHECK-NEXT:    vmovdqu (%rdi), %ymm5
+; CHECK-NEXT:    vextracti128 $1, %ymm5, %xmm6
+; CHECK-NEXT:    vpshufb {{.*#+}} xmm7 = xmm6[2,2,5,5,5,5,3,3,4,4,5,5,6,6,7,7]
+; CHECK-NEXT:    vpshufb {{.*#+}} xmm4 = xmm5[12,12,13,13,15,15,15,15,12,12,13,13,14,14,15,15]
+; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm7[0]
+; CHECK-NEXT:    vpshufb {{.*#+}} xmm5 = xmm5[0,0,1,1,3,3,3,3,6,6,9,9,9,9,7,7]
+; CHECK-NEXT:    vinserti128 $1, %xmm4, %ymm5, %ymm4
 ; CHECK-NEXT:    vpand {{.*}}(%rip), %ymm4, %ymm4
-; CHECK-NEXT:    vpshufb {{.*#+}} xmm5 = xmm5[8,11,14],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT:    vpinsrb $3, %edi, %xmm5, %xmm5
-; CHECK-NEXT:    vpinsrb $4, %esi, %xmm5, %xmm5
-; CHECK-NEXT:    vpinsrb $5, %edx, %xmm5, %xmm5
-; CHECK-NEXT:    vpinsrb $6, %ecx, %xmm5, %xmm5
-; CHECK-NEXT:    vpinsrb $7, %eax, %xmm5, %xmm5
+; CHECK-NEXT:    vpshufb {{.*#+}} xmm5 = zero,zero,zero,xmm8[1,4,7,10,13,u,u,u,u,u,u,u,u]
+; CHECK-NEXT:    vpshufb {{.*#+}} xmm6 = xmm6[8,11,14],zero,zero,zero,zero,zero,xmm6[u,u,u,u,u,u,u,u]
+; CHECK-NEXT:    vpor %xmm6, %xmm5, %xmm5
 ; CHECK-NEXT:    vpmovzxbd {{.*#+}} ymm5 = xmm5[0],zero,zero,zero,xmm5[1],zero,zero,zero,xmm5[2],zero,zero,zero,xmm5[3],zero,zero,zero,xmm5[4],zero,zero,zero,xmm5[5],zero,zero,zero,xmm5[6],zero,zero,zero,xmm5[7],zero,zero,zero
 ; CHECK-NEXT:    vpmulld %ymm0, %ymm4, %ymm0
 ; CHECK-NEXT:    vpmulld %ymm1, %ymm5, %ymm1
 ; CHECK-NEXT:    vpsrlvd %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vpsrlvd %ymm3, %ymm1, %ymm1
 ; CHECK-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
 ; CHECK-NEXT:    vpshufb %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
 ; CHECK-NEXT:    vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
 ; CHECK-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
 ; CHECK-NEXT:    vpshufb %ymm2, %ymm1, %ymm1
 ; CHECK-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
 ; CHECK-NEXT:    vpshufb %xmm3, %xmm1, %xmm1
 ; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %1 = load <48 x i8>, <48 x i8>* %x0, align 1
   %2 = shufflevector <48 x i8> %1, <48 x i8> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
   %3 = zext <16 x i8> %2 to <16 x i32>
   %4 = mul <16 x i32> %3, %x1
   %5 = lshr <16 x i32> %4, %x2
   %6 = trunc <16 x i32> %5 to <16 x i8>
   ret <16 x i8> %6
 }