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dorit (Dorit Nuzman)
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Dec 20 2015, 4:54 AM (178 w, 5 d)

Recent Activity

Jan 31 2019

Herald added a project to D57180: [LV] Avoid adding into interleaved group in presence of WAW dependency: Restricted Project.

I plan on having a look later this week. I am a little worried that the checks in-line here are already quite complex and I would like to have a think if that could be improved in some way.

Jan 31 2019, 11:19 PM · Restricted Project

Oct 31 2018

dorit committed rL345705: [LV] Support vectorization of interleave-groups that require an epilog under.
[LV] Support vectorization of interleave-groups that require an epilog under
Oct 31 2018, 3:01 AM
dorit closed D53668: [LV] Support vectorization of interleave-groups that require an epilog under optsize using masked wide loads .
Oct 31 2018, 3:01 AM

Oct 29 2018

dorit added a comment to D53668: [LV] Support vectorization of interleave-groups that require an epilog under optsize using masked wide loads .

Comments addressed. Thanks!

Oct 29 2018, 7:17 AM
dorit updated the diff for D53668: [LV] Support vectorization of interleave-groups that require an epilog under optsize using masked wide loads .

Addressed comments.
Also added a test with stride 3.

Oct 29 2018, 7:16 AM

Oct 24 2018

dorit accepted D53612: [LV] Avoid vectorizing loops under opt for size that involve SCEV checks.

Just minor comments on the tests.
LGTM.

Oct 24 2018, 1:56 PM
dorit created D53668: [LV] Support vectorization of interleave-groups that require an epilog under optsize using masked wide loads .
Oct 24 2018, 1:29 PM
dorit committed rL345115: [LV] Don't have fold-tail under optsize invalidate interleave-groups when.
[LV] Don't have fold-tail under optsize invalidate interleave-groups when
Oct 24 2018, 12:13 AM
dorit closed D53559: [LV] Don't have fold-tail under optsize invalidate interleave-groups when masked-interleaving is enabled.
Oct 24 2018, 12:13 AM

Oct 23 2018

dorit committed rL345021: Leftover bits from https://reviews.llvm.org/D53420 that were accidentally left.
Leftover bits from https://reviews.llvm.org/D53420 that were accidentally left
Oct 23 2018, 4:54 AM
dorit created D53559: [LV] Don't have fold-tail under optsize invalidate interleave-groups when masked-interleaving is enabled.
Oct 23 2018, 1:43 AM

Oct 21 2018

dorit added inline comments to D53420: [IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when optimizing for size.
Oct 21 2018, 11:25 PM
dorit committed rL344883: [IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when .
[IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when
Oct 21 2018, 11:19 PM
dorit closed D53420: [IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when optimizing for size.
Oct 21 2018, 11:19 PM
dorit added a comment to D53420: [IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when optimizing for size.

Addressed comments. See couple responses below. Thanks!

Oct 21 2018, 8:24 PM

Oct 20 2018

dorit updated the diff for D53420: [IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when optimizing for size.

updated to top of trunk.

Oct 20 2018, 11:34 AM

Oct 19 2018

dorit created D53420: [IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when optimizing for size.
Oct 19 2018, 1:17 AM

Oct 14 2018

dorit committed rL344475: recommit 344472 after fixing build failure on ARM and PPC..
recommit 344472 after fixing build failure on ARM and PPC.
Oct 14 2018, 1:52 AM
dorit committed rL344473: revert 344472 due to failures..
revert 344472 due to failures.
Oct 14 2018, 12:23 AM
dorit added a reverting change for rL344472: [IAI,LV] Add support for vectorizing predicated strided accesses using masked: rL344473: revert 344472 due to failures..
Oct 14 2018, 12:23 AM
dorit committed rL344472: [IAI,LV] Add support for vectorizing predicated strided accesses using masked.
[IAI,LV] Add support for vectorizing predicated strided accesses using masked
Oct 14 2018, 12:08 AM
dorit closed D53011: [LV] Add support for vectorizing predicated strided accesses using masked interleave-group.
Oct 14 2018, 12:08 AM

Oct 10 2018

dorit added a comment to D53011: [LV] Add support for vectorizing predicated strided accesses using masked interleave-group.

Comment addressed, thanks.

Oct 10 2018, 11:40 PM
dorit updated the diff for D53011: [LV] Add support for vectorizing predicated strided accesses using masked interleave-group.
Oct 10 2018, 11:34 PM

Oct 9 2018

dorit added inline comments to D53011: [LV] Add support for vectorizing predicated strided accesses using masked interleave-group.
Oct 9 2018, 5:35 AM
dorit updated the diff for D53011: [LV] Add support for vectorizing predicated strided accesses using masked interleave-group.

Addressed Ayal's comments. Thanks!

Oct 9 2018, 5:31 AM
dorit created D53011: [LV] Add support for vectorizing predicated strided accesses using masked interleave-group.
Oct 9 2018, 12:41 AM

Oct 6 2018

dorit committed rL343931: [IAI,LV] Avoid creating interleave-groups for predicated accesse.
[IAI,LV] Avoid creating interleave-groups for predicated accesse
Oct 6 2018, 11:59 PM
dorit closed D52682: [IAI,LV] Avoid creating interleave-groups for predicated accesses.
Oct 6 2018, 11:59 PM
dorit added a comment to D52682: [IAI,LV] Avoid creating interleave-groups for predicated accesses.

Thanks!

Oct 6 2018, 11:56 PM

Sep 28 2018

dorit created D52682: [IAI,LV] Avoid creating interleave-groups for predicated accesses.
Sep 28 2018, 10:31 PM

Mar 7 2018

dorit added a reviewer for D43812: [LV] Let recordVectorLoopValueForInductionCast to check if IV was created from the cast.: dcaballe.

Hopefully I can delegate the review to Diego...
Thanks for the fix, Andrei

Mar 7 2018, 12:31 PM

Jan 14 2018

dorit accepted D41913: [LV] Don't call recordVectorLoopValueForInductionCast for newly-created IV from a trunc..

LGTM. Thanks for the fix.

Jan 14 2018, 2:46 AM

Dec 14 2017

dorit closed D38948: [LV] Support efficient vectorization of an induction with redundant casts.
Dec 14 2017, 10:54 PM
dorit added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Thanks so much for all your help with this work!

Dec 14 2017, 6:21 AM

Dec 13 2017

dorit committed rL320672: [LV] Support efficient vectorization of an induction with redundant casts.
[LV] Support efficient vectorization of an induction with redundant casts
Dec 13 2017, 11:57 PM

Dec 12 2017

dorit added inline comments to D38948: [LV] Support efficient vectorization of an induction with redundant casts.
Dec 12 2017, 12:46 PM
dorit updated the diff for D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Addressed Ayal's and Silviu's comments.

Dec 12 2017, 12:40 PM
dorit committed rL320463: [LV] Ignore the cost of values that will not appear in the vectorized loop.
[LV] Ignore the cost of values that will not appear in the vectorized loop
Dec 12 2017, 12:58 AM
dorit closed D40883: [LV] Ignore the cost of values that will not appear in the vectorized loop by committing rL320463: [LV] Ignore the cost of values that will not appear in the vectorized loop.
Dec 12 2017, 12:58 AM

Dec 10 2017

dorit committed rL320298: [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts.
[SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts
Dec 10 2017, 3:14 AM
dorit closed D40641: [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts by committing rL320298: [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts.
Dec 10 2017, 3:14 AM

Dec 7 2017

dorit updated the diff for D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Dropped the parts that are uploaded for review separately (D40641, D40883), and hopefully addressed Silviu's last comments.

Dec 7 2017, 2:00 PM
dorit added a comment to D40641: [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts.

ping

Dec 7 2017, 1:29 PM

Dec 6 2017

dorit updated the diff for D40883: [LV] Ignore the cost of values that will not appear in the vectorized loop.

Thanks Florian. Uploaded the formatting fix.

Dec 6 2017, 2:37 AM
dorit added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Hi Ayal,

Dec 6 2017, 12:50 AM
dorit created D40883: [LV] Ignore the cost of values that will not appear in the vectorized loop.
Dec 6 2017, 12:43 AM

Nov 30 2017

dorit added inline comments to D38948: [LV] Support efficient vectorization of an induction with redundant casts.
Nov 30 2017, 2:00 AM
dorit created D40641: [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCasts.
Nov 30 2017, 1:43 AM

Nov 28 2017

dorit updated the diff for D38948: [LV] Support efficient vectorization of an induction with redundant casts.

(uploaded a fix to LoopUtils:getCastsForInductionPHI())

Nov 28 2017, 5:54 AM
dorit updated the diff for D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Hi Silviu,

Nov 28 2017, 1:55 AM

Nov 22 2017

dorit added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Hi Silviu,

Nov 22 2017, 2:03 PM

Nov 20 2017

dorit added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Hi Silviu,
I started to try out the approach you suggested, and I realized that our assumption doesn't hold... (see response to inlined comment).
Thanks,
Dorit

Nov 20 2017, 12:59 PM
dorit added inline comments to D38948: [LV] Support efficient vectorization of an induction with redundant casts.
Nov 20 2017, 1:29 AM

Nov 19 2017

dorit updated the diff for D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Addressed Ayal's comments.
Have yet to address Silviu's comments.

Nov 19 2017, 2:49 PM
dorit added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Yes, IndVarSimpify wouldn't fix this issue, but I was thinking more of using the techniques there that use the SCEV expressions to find these cases instead of doing the pattern matching (see the inline comment).

Nov 19 2017, 12:40 PM
dorit added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Hi Silviu,

Nov 19 2017, 5:24 AM

Nov 16 2017

dorit updated the diff for D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Thanks Ayal. Incorporated your suggestions.

Nov 16 2017, 9:58 AM
dorit added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

ping^2

Nov 16 2017, 1:58 AM

Nov 15 2017

dorit accepted D40008: [X86][TTI] update costs of interleaved load\store of i64\double.

You missed just one mcpu=skylake :)
LGTM with this change

Nov 15 2017, 11:57 PM
dorit added a comment to D40008: [X86][TTI] update costs of interleaved load\store of i64\double.

I think it would be nice to make the testcases smaller; Right now you have something like this:
for (…) {
Dst[2*i] = Dst[2*i] + Src[2*i] * k
Dst[2*i+1] = Dst[2*i+1] + Src[2*i+1] * k
}
...which actually tests both strided loads and strided stores.
So you could either use one test to check both store and load costs (and even then you probably don't need both a mul and an add just to check memops costs).
Or if you want to separate the load and store cases, the Load test could be something like:
for (…) {
s += Src[2*i]
s += Src[2*i+1]
}
The Store test could be something like:
For(…){

Dst[2*i] = k1;
Dst[2*i+1] = k2;

}

Nov 15 2017, 10:28 AM

Nov 7 2017

dorit added a comment to D38948: [LV] Support efficient vectorization of an induction with redundant casts.

ping :)

Nov 7 2017, 1:04 PM

Nov 5 2017

dorit updated the diff for D38948: [LV] Support efficient vectorization of an induction with redundant casts.

Incorporated Ayal's comments. Thanks!

Nov 5 2017, 10:23 AM
dorit committed rL317438.
Nov 5 2017, 8:53 AM
dorit closed D38785: [LV/LAA] Avoid specializing a loop for stride=1 when this predicate implies a single-iteration loop by committing rL317438.
Nov 5 2017, 8:53 AM

Nov 2 2017

dorit added a comment to D38785: [LV/LAA] Avoid specializing a loop for stride=1 when this predicate implies a single-iteration loop.

Hi Silviu,

Nov 2 2017, 4:50 AM

Oct 18 2017

dorit retitled D38785: [LV/LAA] Avoid specializing a loop for stride=1 when this predicate implies a single-iteration loop from [LV/LAA] Avoid secializing a loop for stride=1 when this predicate implies a single-iteration loop to [LV/LAA] Avoid specializing a loop for stride=1 when this predicate implies a single-iteration loop.
Oct 18 2017, 1:37 AM

Oct 17 2017

dorit accepted D38762: Cost calculation for interleave load/store patterns {v8i8,v16i8,v32i8,v64i8}.

LGTM with the last couple of comments.

Oct 17 2017, 3:47 AM
dorit added a comment to D38762: Cost calculation for interleave load/store patterns {v8i8,v16i8,v32i8,v64i8}.

AVX512 side of things now also looks good to me (with the tiny comments below).

Oct 17 2017, 3:32 AM

Oct 16 2017

dorit added a comment to D38762: Cost calculation for interleave load/store patterns {v8i8,v16i8,v32i8,v64i8}.

The AVX2 changes look ok to me now.
A couple comments about the AVX512 changes below.

Oct 16 2017, 5:57 AM
dorit created D38948: [LV] Support efficient vectorization of an induction with redundant casts.
Oct 16 2017, 5:29 AM

Oct 11 2017

dorit added a comment to D38785: [LV/LAA] Avoid specializing a loop for stride=1 when this predicate implies a single-iteration loop.

Hi Silviu,

Oct 11 2017, 5:10 AM

Oct 10 2017

dorit added reviewers for D38785: [LV/LAA] Avoid specializing a loop for stride=1 when this predicate implies a single-iteration loop: Ayal, hfinkel, silviu.baranga.
Oct 10 2017, 11:27 PM
dorit created D38785: [LV/LAA] Avoid specializing a loop for stride=1 when this predicate implies a single-iteration loop.
Oct 10 2017, 11:25 PM
dorit added a comment to D38762: Cost calculation for interleave load/store patterns {v8i8,v16i8,v32i8,v64i8}.

My only main concerns are with respect to interleave-group with gaps (see below), and the fact that we don't distinguish the AVX2 from the AVX512 case (also see below). Just minor comments beyond that.

Oct 10 2017, 11:01 PM

Sep 9 2017

dorit added a comment to D37507: Fix maximum legal VF calculation.

Looks fine to me (with a couple very minor dbg reports improvements).
@Ayal/@hfinkel - what do you say?

Sep 9 2017, 11:43 PM

Sep 6 2017

dorit added a comment to D37265: [SCEV] Ensure ScalarEvolution::createAddRecFromPHIWithCastsImpl properly handles out of range truncations of the start and accum values.
  1. FYI @dorit This fixes a bug in code you introduced in D30041
Sep 6 2017, 4:42 AM

Aug 20 2017

dorit added a comment to D30200: [SLP] Fix for PR31880: shuffle and vectorize repeated scalar ops on extracted elements.

@dorit I've implemented most of the x86 single source shuffle costs at rL310632, please can you see if this has improved things for you?

Aug 20 2017, 5:41 AM

Aug 10 2017

dorit added a comment to D30200: [SLP] Fix for PR31880: shuffle and vectorize repeated scalar ops on extracted elements.

Hi Alexey,

Aug 10 2017, 12:01 AM

Jul 18 2017

dorit committed rL308299: PSCEV] Create AddRec for Phis in cases of possible integer overflow,.
PSCEV] Create AddRec for Phis in cases of possible integer overflow,
Jul 18 2017, 4:57 AM
dorit closed D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks by committing rL308299: PSCEV] Create AddRec for Phis in cases of possible integer overflow,.
Jul 18 2017, 4:57 AM

Jul 16 2017

dorit updated the diff for D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

Hi Sanjoy,

Jul 16 2017, 2:35 PM

Jul 14 2017

dorit added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

Hi Sanjoy,
Thanks! Comments addressed,
Dorit

Jul 14 2017, 4:30 AM
dorit updated the diff for D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

Addressing Sanjoy's comments.

Jul 14 2017, 4:16 AM

Jul 9 2017

dorit added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

@sanjoy, is the patch ok with you?

Jul 9 2017, 6:14 AM

Jul 2 2017

dorit added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

ping^2

Jul 2 2017, 1:24 AM

Jun 27 2017

dorit added a comment to D34601: [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess..

Just a few minor comments. Looks good to me otherwise, but should give @RKSimon a chance to see if he's happy with your responses (and maybe also another day to give @Farhana/@DavidKreitzer a chance to comment).

Jun 27 2017, 3:18 AM

Jun 26 2017

dorit committed rL306238: [AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2.
[AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2
Jun 26 2017, 2:48 AM
dorit closed D34023: [AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2 by committing rL306238: [AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2.
Jun 26 2017, 2:47 AM

Jun 21 2017

dorit added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

@sbaranga, @sanjoy, ping :-)
thanks.
dorit

Jun 21 2017, 11:58 PM

Jun 18 2017

dorit updated the diff for D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

Addressed Silviu's last comments on the documentation:

  • Added the predicates that are added for each of the loops in the testcase
  • In the proof:
    • dropped all the introductory text and jump directly to the formal proof.
    • expanded the short notation I was using (SExTrunc) into the explicit notation (Ext ix (Trunc iy () to ix ) to iy)
Jun 18 2017, 12:34 AM

Jun 14 2017

dorit updated subscribers of D34023: [AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2.
Jun 14 2017, 4:20 AM

Jun 12 2017

dorit added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

Thanks Silviu. I'll iron the comments following your suggestions.

Jun 12 2017, 11:15 PM

Jun 8 2017

dorit added reviewers for D34023: [AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2: RKSimon, craig.topper.
Jun 8 2017, 4:11 AM
dorit created D34023: [AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2.
Jun 8 2017, 1:30 AM

Jun 5 2017

dorit added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

ping?
thanks,
Dorit

Jun 5 2017, 3:53 AM

May 24 2017

dorit added inline comments to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
May 24 2017, 12:43 PM
dorit updated the diff for D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.
  • We now require that Accum is loop invariant.
  • Added a simple Expr == ExtendedExpr check, and only if it fails we call isKnownPredicate().
  • Extended the testcase:

• Check that we have both the overflow runtime check and the equality runtime check in doit1 and doit2
• Added doit3: where step is not invariant (not very interesting - we do nothing)
• Added doit4: where we can figure out at compile time that step == sext(trunc(step)). Here we check that we only have the overflow runtime check (without the equality runtime check).

May 24 2017, 12:42 PM

May 18 2017

dorit added a comment to D17080: [LAA] Allow more run-time alias checks by coercing pointer expressions to AddRecExprs.

I think @anemet has reviewed patches in this part of the vectorizer… @anemet, would you be able to please take a look?

May 18 2017, 1:56 AM
dorit added a comment to D30041: [PSCEV] Create AddRec for Phis in cases of possible integer overflow, using runtime checks.

Ping :)

May 18 2017, 1:42 AM