Keep EXTRACT_VECTOR_ELT result type as f128 for Android x86_64.

[chh]

Summary

http://bugs.llvm.org/show_bug.cgi?id=32330
Android x86_64 target uses f128 type and stores f128 values
in %xmm* registers.
SoftenFloatRes_EXTRACT_VECTOR_ELT should not convert
result value from f128 to i128.

[pirama]

LGTM. Adding some other contributors to SelectionDAG to review.

test/CodeGen/X86/fp128-extract.ll

12

Remove hidden, local_unnamed_addr and align?

13

I also think the simplified version of the test below is preferable because it's easier to understand why the test fails without this fix.

define fp128 @foo(<2 x double> %x) {
    %a = fpext <2 x double> %x to <2 x fp128>
    %1 = extractelement <2 x fp128> %a, i32 0
    %2 = extractelement <2 x fp128> %a, i32 1
    %3 = fmul fp128 %1, %2
    ret fp128 %3
}

If you want to test this extended pattern from boost, consider adding both?

[niravd]

This also LGTM. Minor comments inline.

test/CodeGen/X86/fp128-extract.ll

13

Is TestExtract representive of pr32330 ? If so you should name it as such.

[chh]

test/CodeGen/X86/fp128-extract.ll

13

This test case is extremely simplified to contain only the extractelement operation,
which I believe is the only opcode missed.
With this change, we can now compile pr32330 test case and found no regression with Android source.

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

case ISD::CopyToReg:
       // Only when isLegalInHWReg, we can skip check of the operands.
       R = SDValue(N, ResNo);
       break;
     case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
     case ISD::BITCAST:     R = SoftenFloatRes_BITCAST(N, ResNo); break;
     case ISD::BUILD_PAIR:  R = SoftenFloatRes_BUILD_PAIR(N); break;
     case ISD::ConstantFP:  R = SoftenFloatRes_ConstantFP(N, ResNo); break;
     case ISD::EXTRACT_VECTOR_ELT:
-      R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N); break;
+      R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;
     case ISD::FABS:        R = SoftenFloatRes_FABS(N, ResNo); break;
     case ISD::FMINNUM:     R = SoftenFloatRes_FMINNUM(N); break;
     case ISD::FMAXNUM:     R = SoftenFloatRes_FMAXNUM(N); break;
     case ISD::FADD:        R = SoftenFloatRes_FADD(N); break;
     case ISD::FCEIL:       R = SoftenFloatRes_FCEIL(N); break;
     case ISD::FCOPYSIGN:   R = SoftenFloatRes_FCOPYSIGN(N, ResNo); break;
     case ISD::FCOS:        R = SoftenFloatRes_FCOS(N); break;
     case ISD::FDIV:        R = SoftenFloatRes_FDIV(N); break;
return DAG.getConstant(Val, SDLoc(CN),
                                                     CN->getValueType(0)));
   } else {
     return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
                            TLI.getTypeToTransformTo(*DAG.getContext(),
                                                     CN->getValueType(0)));
   }
 }
 
-SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) {
+  // When LegalInHWReg, keep the extracted value in register.
+  if (isLegalInHWReg(N->getValueType(ResNo)))
+    return SDValue(N, ResNo);
   SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
                      NewOp.getValueType().getVectorElementType(),
                      NewOp, N->getOperand(1));
 }
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N, unsigned ResNo) {
   // When LegalInHWReg, FABS can be implemented as native bitwise operations.

lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   }
 
   // Convert Float Results to Integer for Non-HW-supported Operations.
   bool SoftenFloatResult(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_BITCAST(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
   SDValue SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo);
-  SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);
+  SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_FABS(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_FMINNUM(SDNode *N);
   SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
   SDValue SoftenFloatRes_FADD(SDNode *N);
   SDValue SoftenFloatRes_FCEIL(SDNode *N);
   SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_FCOS(SDNode *N);
   SDValue SoftenFloatRes_FDIV(SDNode *N);

test/CodeGen/X86/extract-store.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2     | FileCheck %s --check-prefix=X32 --check-prefix=SSE-X32 --check-prefix=SSE2-X32
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2   | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE2-X64
 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1   | FileCheck %s --check-prefix=X32 --check-prefix=SSE-X32 --check-prefix=SSE41-X32
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE41-X64
 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx      | FileCheck %s --check-prefix=X32 --check-prefix=AVX-X32
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx    | FileCheck %s --check-prefix=X64 --check-prefix=AVX-X64
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx -enable-legalize-types-checking \
+; RUN:   | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE-F128
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx -enable-legalize-types-checking \
+; RUN:   | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE-F128
 
 define void @extract_i8_0(i8* nocapture %dst, <16 x i8> %foo) nounwind {
 ; SSE2-X32-LABEL: extract_i8_0:
 ; SSE2-X32:       # BB#0:
 ; SSE2-X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE2-X32-NEXT:    movd %xmm0, %ecx
 ; SSE2-X32-NEXT:    movb %cl, (%eax)
 ; SSE2-X32-NEXT:    retl

 ; AVX-X64:       # BB#0:
 ; AVX-X64-NEXT:    vmovhpd %xmm0, (%rdi)
 ; AVX-X64-NEXT:    retq
   %vecext = extractelement <2 x double> %foo, i32 1
   store double %vecext, double* %dst, align 1
   ret void
 }
 
+define void @extract_f128_0(fp128* nocapture %dst, <2 x fp128> %foo) nounwind {
+; SSE-F128-LABEL: extract_f128_0:
+; SSE-F128:       # BB#0:
+; SSE-F128-NEXT:    movaps  %xmm0, (%rdi)
+; SSE-F128-NEXT:    retq
+  %vecext = extractelement <2 x fp128> %foo, i32 0
+  store fp128 %vecext, fp128* %dst, align 1
+  ret void
+}
+
+define void @extract_f128_1(fp128* nocapture %dst, <2 x fp128> %foo) nounwind {
+; SSE-F128-LABEL: extract_f128_1:
+; SSE-F128:       # BB#0:
+; SSE-F128-NEXT:    movaps  %xmm1, (%rdi)
+; SSE-F128-NEXT:    retq
+  %vecext = extractelement <2 x fp128> %foo, i32 1
+  store fp128 %vecext, fp128* %dst, align 1
+  ret void
+}
+
 define void @extract_i8_undef(i8* nocapture %dst, <16 x i8> %foo) nounwind {
 ; X32-LABEL: extract_i8_undef:
 ; X32:       # BB#0:
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: extract_i8_undef:
 ; X64:       # BB#0:
 ; X64-NEXT:    retq

 ;
 ; X64-LABEL: extract_f64_undef:
 ; X64:       # BB#0:
 ; X64-NEXT:    retq
   %vecext = extractelement <2 x double> %foo, i32 2 ; undef
   store double %vecext, double* %dst, align 1
   ret void
 }
+
+define void @extract_f128_undef(fp128* nocapture %dst, <2 x fp128> %foo) nounwind {
+; X32-LABEL: extract_f128_undef:
+; X32:       # BB#0:
+; X32-NEXT:    retl
+;
+; X64-LABEL: extract_f128_undef:
+; X64:       # BB#0:
+; X64-NEXT:    retq
+  %vecext = extractelement <2 x fp128> %foo, i32 2 ; undef
+  store fp128 %vecext, fp128* %dst, align 1
+  ret void
+}

test/CodeGen/X86/fp128-extract.ll

+; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx \
+; RUN:     -enable-legalize-types-checking | FileCheck %s
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx \
+; RUN:     -enable-legalize-types-checking | FileCheck %s
+
+; Test the softened result of extractelement op code.
+define fp128 @TestExtract(<2 x double> %x) {
+entry:
+  ; Simplified instruction pattern from the output of llvm before r289042,
+  ; for a boost function ...::insert<...>::traverse<...>().
+  %a = fpext <2 x double> %x to <2 x fp128>
+  %0 = extractelement <2 x fp128> %a, i32 0
+  %1 = extractelement <2 x fp128> %a, i32 1
+  %2 = fmul fp128 %0, %1
+  ret fp128 %2
+; CHECK-LABEL: TestExtract:
+; CHECK:       movaps %xmm0, (%rsp)
+; CHECK:       callq  __extenddftf2
+; CHECK:       callq  __extenddftf2
+; CHECK:       callq    __multf3
+; CHECK:       retq
+}