Keep EXTRACT_VECTOR_ELT result type as f128 for Android x86_64.

[chh]

Summary

http://bugs.llvm.org/show_bug.cgi?id=32330
Android x86_64 target uses f128 type and stores f128 values
in %xmm* registers.
SoftenFloatRes_EXTRACT_VECTOR_ELT should not convert
result value from f128 to i128.

[pirama]

LGTM. Adding some other contributors to SelectionDAG to review.

test/CodeGen/X86/fp128-extract.ll

12

Remove hidden, local_unnamed_addr and align?

13

I also think the simplified version of the test below is preferable because it's easier to understand why the test fails without this fix.

define fp128 @foo(<2 x double> %x) {
    %a = fpext <2 x double> %x to <2 x fp128>
    %1 = extractelement <2 x fp128> %a, i32 0
    %2 = extractelement <2 x fp128> %a, i32 1
    %3 = fmul fp128 %1, %2
    ret fp128 %3
}

If you want to test this extended pattern from boost, consider adding both?

[niravd]

This also LGTM. Minor comments inline.

test/CodeGen/X86/fp128-extract.ll

13

Is TestExtract representive of pr32330 ? If so you should name it as such.

[chh]

test/CodeGen/X86/fp128-extract.ll

13

This test case is extremely simplified to contain only the extractelement operation,
which I believe is the only opcode missed.
With this change, we can now compile pr32330 test case and found no regression with Android source.

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

case ISD::CopyToReg:
       // Only when isLegalInHWReg, we can skip check of the operands.
       R = SDValue(N, ResNo);
       break;
     case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
     case ISD::BITCAST:     R = SoftenFloatRes_BITCAST(N, ResNo); break;
     case ISD::BUILD_PAIR:  R = SoftenFloatRes_BUILD_PAIR(N); break;
     case ISD::ConstantFP:  R = SoftenFloatRes_ConstantFP(N, ResNo); break;
     case ISD::EXTRACT_VECTOR_ELT:
-      R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N); break;
+      R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;
     case ISD::FABS:        R = SoftenFloatRes_FABS(N, ResNo); break;
     case ISD::FMINNUM:     R = SoftenFloatRes_FMINNUM(N); break;
     case ISD::FMAXNUM:     R = SoftenFloatRes_FMAXNUM(N); break;
     case ISD::FADD:        R = SoftenFloatRes_FADD(N); break;
     case ISD::FCEIL:       R = SoftenFloatRes_FCEIL(N); break;
     case ISD::FCOPYSIGN:   R = SoftenFloatRes_FCOPYSIGN(N, ResNo); break;
     case ISD::FCOS:        R = SoftenFloatRes_FCOS(N); break;
     case ISD::FDIV:        R = SoftenFloatRes_FDIV(N); break;
return DAG.getConstant(Val, SDLoc(CN),
                                                     CN->getValueType(0)));
   } else {
     return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
                            TLI.getTypeToTransformTo(*DAG.getContext(),
                                                     CN->getValueType(0)));
   }
 }
 
-SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) {
+  // When LegalInHWReg, keep the extracted value in register.
+  if (isLegalInHWReg(N->getValueType(ResNo)))
+    return SDValue(N, ResNo);
   SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
                      NewOp.getValueType().getVectorElementType(),
                      NewOp, N->getOperand(1));
 }
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N, unsigned ResNo) {
   // When LegalInHWReg, FABS can be implemented as native bitwise operations.

lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   }
 
   // Convert Float Results to Integer for Non-HW-supported Operations.
   bool SoftenFloatResult(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_BITCAST(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
   SDValue SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo);
-  SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);
+  SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_FABS(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_FMINNUM(SDNode *N);
   SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
   SDValue SoftenFloatRes_FADD(SDNode *N);
   SDValue SoftenFloatRes_FCEIL(SDNode *N);
   SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N, unsigned ResNo);
   SDValue SoftenFloatRes_FCOS(SDNode *N);
   SDValue SoftenFloatRes_FDIV(SDNode *N);

test/CodeGen/X86/fp128-extract.ll

+; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx \
+; RUN:     -enable-legalize-types-checking | FileCheck %s
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx \
+; RUN:     -enable-legalize-types-checking | FileCheck %s
+
+@my_fp128_v0 = global fp128 0xL0, align 16
+@my_fp128_v1 = global fp128 0xL0, align 16
+@my_fp128_v2 = global fp128 0xL0, align 16
+
+; Test the softened result of extractelement op code.
+define hidden fp128 @TestExtract() local_unnamed_addr align 2 {
+entry:
+  ; Simplified instruction pattern from the output of llvm before r289042,
+  ; for a boost function ...::insert<...>::traverse<...>().
+  %0 = fsub <2 x double> zeroinitializer, undef
+  %1 = fpext <2 x double> %0 to <2 x fp128>
+  %2 = extractelement <2 x fp128> %1, i32 1
+  %3 = fmul fp128 undef, %2
+  %4 = fcmp ogt fp128 %3, 0xL00000000000000003F8F000000000000
+  %5 = bitcast fp128* @my_fp128_v0 to <2 x double>*
+  %6 = load <2 x double>, <2 x double>* %5, align 8
+  %7 = bitcast fp128* @my_fp128_v1 to <2 x double>*
+  %8 = load <2 x double>, <2 x double>* %7, align 8
+  %9 = bitcast fp128* @my_fp128_v2 to <2 x double>*
+  %10 = load <2 x double>, <2 x double>* %9, align 8
+  %11 = fcmp olt <2 x double> %6, %8
+  %12 = select <2 x i1> %11, <2 x double> %6, <2 x double> %8
+  %13 = fcmp ogt <2 x double> %6, %10
+  %14 = select <2 x i1> %13, <2 x double> %6, <2 x double> %10
+  %15 = fsub <2 x double> %14, %12
+  %16 = fpext <2 x double> %15 to <2 x fp128>   ;
+  %17 = extractelement <2 x fp128> %16, i32 0
+  %18 = extractelement <2 x fp128> %16, i32 1
+  %mul.i36 = fmul fp128 %17, %18
+  %19 = extractelement <2 x double> %10, i32 0
+  %20 = extractelement <2 x double> %8, i32 0
+  %sub.i6 = fsub double %19, %20
+  %conv.i6 = fpext double %sub.i6 to fp128   ;
+  %21 = extractelement <2 x double> %10, i32 1
+  %22 = extractelement <2 x double> %8, i32 1
+  %23 = fsub double %21, %22
+  %conv.i5 = fpext double %23 to fp128
+  %mul.i5 = fmul fp128 %conv.i6, %conv.i5
+  %sub.i2 = fsub fp128 %mul.i36, %mul.i5
+  ret fp128 %sub.i2
+; CHECK-LABEL: TestExtract:
+; CHECK:     movapd my_fp128_v0(%rip), %xmm0
+; CHECK:     movapd my_fp128_v1(%rip), %xmm1
+; CHECK:     movapd my_fp128_v2(%rip), %xmm2
+; CHECK:     callq  __extenddftf2
+; CHECK:     callq  __extenddftf2
+; CHECK:     callq  __multf3
+; CHECK:     callq  __extenddftf2
+; CHECK:     callq  __extenddftf2
+; CHECK:     callq  __multf3
+; CHECK:     callq  __subtf3
+; CHECK:     ret
+}