[globalisel][tablegen] Make it possible to declare rules directly in GlobalISel.

[dsanders]

Summary

The syntax ought to be nicer but it's functional and enables testing
GlobalISelEmitter rules separately from the SelectionDAG importer.

The various emitTblgen() functions are primarily for debugging
SelectionDAG imports at this point. Rules now emit their tablegen
definition in a '#if 0' block so that we can easily see the rule the
emitter was emitting.

[dsanders]

Refresh

include/llvm/Target/GlobalISel/Target.td

 // descriptions written for SelectionDAG without requiring explicit GlobalISel
 // support.  It will eventually supersede SelectionDAG patterns.
 //
 //===----------------------------------------------------------------------===//
 
 // Definitions that inherit from LLT define types that will be used in the
 // GlobalISel matcher.
 class LLT;
+class LLTScalar<int sizeinbits> : LLT { int SizeInBits = sizeinbits; }
 
-def s32 : LLT;
-def s64 : LLT;
+def s32 : LLTScalar<32>;
+def s64 : LLTScalar<64>;
 
 // Defines a matcher for complex operands. This is analogous to ComplexPattern
 // from SelectionDAG.
 //
 // Definitions that inherit from this may also inherit from
 // GIComplexPatternEquiv to enable the import of SelectionDAG patterns involving
 // those ComplexPatterns.
 class GIComplexOperandMatcher<LLT type, dag operands, string matcherfn> {
class GIComplexOperandMatcher<LLT type, dag operands, string matcherfn> {
   // the form:
   //   bool select(const MatchOperand &Root, MatchOperand &Result1)
   // and should have the same number of ResultX arguments as the number of
   // result operands. It must return true on successful match and false
   // otherwise. If it returns true, then all the ResultX arguments must be
   // overwritten.
   string MatcherFn = matcherfn;
 }
+
+// === Operand predicates ===
+class GIMatchOperandPredicate;
+
+// Operand must be of the given type.
+class GIMatchLLT<LLT type> : GIMatchOperandPredicate {
+  LLT Type = type;
+}
+
+// Operand must match the given complex pattern.
+// FIXME: Merge with GIComplexOperandMatcher
+class GIMatchComplexPattern<GIComplexOperandMatcher matcher> : GIMatchOperandPredicate  {
+  GIComplexOperandMatcher Matcher = matcher;
+}
+
+// Operand must be in the register bank for the given register class.
+class GIMatchRegBankForClass<RegisterClass rc> : GIMatchOperandPredicate {
+  RegisterClass RC = rc;
+}
+
+// Operand must be an MBB.
+// This one is a def since classes cannot be anonymously defined without arguments.
+class GIMatchMBBImpl : GIMatchOperandPredicate;
+def GIMatchMBB : GIMatchMBBImpl;
+
+// Operand must match a specific integer.
+class GIMatchInt<int value> : GIMatchOperandPredicate {
+  int Value = value;
+}
+
+// TODO: Operand must match arbitrary code (for ImmLeaf).
+class GIMatchCode<code c> : GIMatchOperandPredicate {
+  code Code = c;
+}
+
+// Operand must be present and must match all the predicates. If name is
+// non-empty it can be used by the renderers.
+class GIMatchOperand<string name, list<GIMatchOperandPredicate> predicates> {
+  string Name = name;
+  list<GIMatchOperandPredicate> Predicates = predicates;
+}
+
+// === Instruction Predicates ===
+class GIMatchInsnPredicate;
+
+// Instruction must have the given opcode.
+class GIMatchOpcode<Instruction insn> : GIMatchInsnPredicate {
+  Instruction Insn = insn;
+}
+
+// Instruction must be present and must match all the predicates and operands.
+class GIMatchInsn<list<GIMatchInsnPredicate> predicates, list<GIMatchOperand> operands> {
+  list<GIMatchInsnPredicate> Predicates = predicates;
+  list<GIMatchOperand> Operands = operands;
+}
+
+// Operand must use a register that's defined by an instruction matching the
+// given instruction matcher.
+class GIMatchSubInsn<GIMatchInsn insn> : GIMatchOperandPredicate {
+  GIMatchInsn Insn = insn;
+}
+
+// === Operand Renderers ===
+class GIOperandRenderer;
+
+// Copy operand from match.
+class GICopyOperand<string name> : GIOperandRenderer {
+  string Name = name;
+}
+
+// Add a specific register.
+class GIAddRegister<Register reg> : GIOperandRenderer {
+  Register Reg = reg;
+}
+
+// Add a specific integer.
+class GIAddImm<int value> : GIOperandRenderer {
+  int Value = value;
+}
+
+// Render ComplexPattern results.
+class GIAddComplexOperand<GIComplexOperandMatcher matcher, string name> : GIOperandRenderer {
+  GIComplexOperandMatcher Matcher = matcher;
+  string Name = name;
+}
+
+// === Actions ===
+class GIAction;
+
+// Build an instruction.
+// Will automatically convert to an in-place mutation where possible.
+class GIBuildMI<Instruction i, list<GIOperandRenderer> renderers> : GIAction {
+  Instruction I = i;
+  list<GIOperandRenderer> Renderers = renderers;
+}
+
+// === Rules ===
+
+// Defines a GlobalISel matcher rule.
+class GIRule<list<GIMatchInsn> insnmatchers, list<GIAction> actions> {
+  // A list of instruction matchers. These form the roots of the match.
+  list<GIMatchInsn> InsnMatchers = insnmatchers;
+
+  // A list of actions to take in response to the rule.
+  list<GIAction> Actions = actions;
+}

test/TableGen/GlobalISelEmitter-GIRule.td

+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+//===- Define the necessary boilerplate for our test target. --------------===//
+
+def MyTargetISA : InstrInfo;
+def MyTarget : Target { let InstructionSet = MyTargetISA; }
+
+def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
+def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+
+class I<dag OOps, dag IOps, list<dag> Pat>
+  : Instruction {
+  let Namespace = "MyTarget";
+  let OutOperandList = OOps;
+  let InOperandList = IOps;
+  let Pattern = Pat;
+}
+
+def complex : Operand<i32>;
+def gi_complex :
+    GIComplexOperandMatcher<s32, (ops i32imm, i32imm), "selectComplexPattern">;
+
+def m1 : OperandWithDefaultOps <i32, (ops (i32 -1))>;
+def Z : OperandWithDefaultOps <i32, (ops R0)>;
+
+//===- Test the function definition boilerplate. --------------------------===//
+
+// CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I) const {
+// CHECK: MachineFunction &MF = *I.getParent()->getParent();
+// CHECK: const MachineRegisterInfo &MRI = MF.getRegInfo();
+
+//===- Test a pattern with multiple ComplexPattern operands. --------------===//
+//
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 4)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_SELECT) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        (selectComplexPattern(MI0.getOperand(2), TempOp0, TempOp1)))) &&
+// CHECK-NEXT:        ((/* src3 */ (MRI.getType(MI0.getOperand(3).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        (selectComplexPattern(MI0.getOperand(3), TempOp2, TempOp3))))) {
+// CHECK-NEXT:          // Rule1
+// CHECK-NEXT:          MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::INSN2));
+// CHECK-NEXT:          MIB.add(MI0.getOperand(0)/*dst*/);
+// CHECK-NEXT:          MIB.add(MI0.getOperand(1)/*src1*/);
+// CHECK-NEXT:          MIB.add(TempOp2);
+// CHECK-NEXT:          MIB.add(TempOp3);
+// CHECK-NEXT:          MIB.add(TempOp0);
+// CHECK-NEXT:          MIB.add(TempOp1);
+// CHECK-NEXT:          for (const auto *FromMI : {&MI0, })
+// CHECK-NEXT:            for (const auto &MMO : FromMI->memoperands())
+// CHECK-NEXT:              MIB.addMemOperand(MMO);
+// CHECK-NEXT:          I.eraseFromParent();
+// CHECK-NEXT:          MachineInstr &NewI = *MIB;
+// CHECK-NEXT:          constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:          return true;
+// CHECK-NEXT:        }
+
+def INSN2 : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2, complex:$src3), []>;
+def Rule1 : GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_SELECT>],
+              [GIMatchOperand<"dst", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+               GIMatchOperand<"src1", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+               GIMatchOperand<"src2", [GIMatchLLT<s32>, GIMatchComplexPattern<gi_complex>]>,
+               GIMatchOperand<"src3", [GIMatchLLT<s32>, GIMatchComplexPattern<gi_complex>]>
+              ]>],
+ [GIBuildMI<INSN2,
+  [GICopyOperand<"dst">,
+   GICopyOperand<"src1">,
+   GIAddComplexOperand<gi_complex, "src3"/* TempOp2, TempOp3 */>,
+   GIAddComplexOperand<gi_complex, "src2"/* TempOp0, TempOp1 */>
+  ]>
+ ]>;
+
+//===- Test a simple pattern with regclass operands. ----------------------===//
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_ADD) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(2).getReg(), MRI, TRI)))))) {
+
+// CHECK-NEXT:      // Rule2
+// CHECK-NEXT:      I.setDesc(TII.get(MyTarget::ADD));
+// CHECK-NEXT:      MachineInstr &NewI = I;
+// CHECK-NEXT:      constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:      return true;
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return false;
+// CHECK-NEXT:  }()) { return true; }
+
+
+def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
+def Rule2 : GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_ADD>], [
+   GIMatchOperand<"dst", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"src1", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"src2", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>]>],
+ [GIBuildMI<ADD, [GICopyOperand<"dst">, GICopyOperand<"src1">, GICopyOperand<"src2">]>]>;
+
+//===- Test a nested instruction match. -----------------------------------===//
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if (!MI0.getOperand(1).isReg())
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(1).getReg());
+// CHECK-NEXT:    if (MI1.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_MUL) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* Operand 1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        (((MI1.getOpcode() == TargetOpcode::G_ADD) &&
+// CHECK-NEXT:        ((/* Operand 0 */ (MRI.getType(MI1.getOperand(0).getReg()) == (LLT::scalar(32))))) &&
+// CHECK-NEXT:        ((/* src1 */ (MRI.getType(MI1.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src2 */ (MRI.getType(MI1.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1.getOperand(2).getReg(), MRI, TRI))))))
+// CHECK-NEXT:        ))) &&
+// CHECK-NEXT:        ((/* src3 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(2).getReg(), MRI, TRI)))))) {
+// CHECK-NEXT:        if (!isObviouslySafeToFold(MI1)) return false;
+// CHECK-NEXT:        // Rule3
+// CHECK-NEXT:     MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MULADD));
+// CHECK-NEXT:     MIB.add(MI0.getOperand(0)/*dst*/);
+// CHECK-NEXT:     MIB.add(MI1.getOperand(1)/*src1*/);
+// CHECK-NEXT:     MIB.add(MI1.getOperand(2)/*src2*/);
+// CHECK-NEXT:     MIB.add(MI0.getOperand(2)/*src3*/);
+// CHECK-NEXT:     for (const auto *FromMI : {&MI0, &MI1, })
+// CHECK-NEXT:       for (const auto &MMO : FromMI->memoperands())
+// CHECK-NEXT:         MIB.addMemOperand(MMO);
+// CHECK-NEXT:     I.eraseFromParent();
+// CHECK-NEXT:     MachineInstr &NewI = *MIB;
+// CHECK-NEXT:     constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:     return true;
+// CHECK-NEXT:   }
+
+// We also get a second rule by commutativity.
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if (!MI0.getOperand(2).isReg())
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(2).getReg());
+// CHECK-NEXT:    if (MI1.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_MUL) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src3 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        (((MI1.getOpcode() == TargetOpcode::G_ADD) &&
+// CHECK-NEXT:        ((/* Operand 0 */ (MRI.getType(MI1.getOperand(0).getReg()) == (LLT::scalar(32))))) &&
+// CHECK-NEXT:        ((/* src1 */ (MRI.getType(MI1.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src2 */ (MRI.getType(MI1.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI1.getOperand(2).getReg(), MRI, TRI))))))
+// CHECK-NEXT:        )))) {
+// CHECK-NEXT:        if (!isObviouslySafeToFold(MI1)) return false;
+// CHECK-NEXT:        // Rule3X
+// CHECK-NEXT:     MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MULADD));
+// CHECK-NEXT:     MIB.add(MI0.getOperand(0)/*dst*/);
+// CHECK-NEXT:     MIB.add(MI1.getOperand(1)/*src1*/);
+// CHECK-NEXT:     MIB.add(MI1.getOperand(2)/*src2*/);
+// CHECK-NEXT:     MIB.add(MI0.getOperand(1)/*src3*/);
+// CHECK-NEXT:     for (const auto *FromMI : {&MI0, &MI1, })
+// CHECK-NEXT:       for (const auto &MMO : FromMI->memoperands())
+// CHECK-NEXT:         MIB.addMemOperand(MMO);
+// CHECK-NEXT:     I.eraseFromParent();
+// CHECK-NEXT:     MachineInstr &NewI = *MIB;
+// CHECK-NEXT:     constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:     return true;
+// CHECK-NEXT:   }
+
+def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3), []>;
+def Rule3: GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_MUL>], [
+   GIMatchOperand<"dst", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"",
+    [GIMatchLLT<s32>,
+      GIMatchSubInsn<GIMatchInsn<[GIMatchOpcode<G_ADD>], [
+       GIMatchOperand<"", [GIMatchLLT<s32>]>,
+       GIMatchOperand<"src1", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+       GIMatchOperand<"src2", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>]>>]>,
+   GIMatchOperand<"src3", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>]>
+ ],
+ [GIBuildMI<MULADD, [
+   GICopyOperand<"dst">,
+   GICopyOperand<"src1">,
+   GICopyOperand<"src2">,
+   GICopyOperand<"src3">]>
+ ]>;
+
+// Commutativity is manual at the moment.
+def Rule3X: GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_MUL>], [
+   GIMatchOperand<"dst", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"src3", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"",
+    [GIMatchLLT<s32>,
+     GIMatchSubInsn<GIMatchInsn<[GIMatchOpcode<G_ADD>], [
+      GIMatchOperand<"", [GIMatchLLT<s32>]>,
+      GIMatchOperand<"src1", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+      GIMatchOperand<"src2", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>]>>]>]>],
+ [GIBuildMI<MULADD, [
+   GICopyOperand<"dst">,
+   GICopyOperand<"src1">,
+   GICopyOperand<"src2">,
+   GICopyOperand<"src3">]>
+ ]>;
+
+//===- Test another simple pattern with regclass operands. ----------------===//
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_MUL) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(2).getReg(), MRI, TRI)))))) {
+// CHECK-NEXT:      // Rule4
+// CHECK-NEXT:      MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MUL));
+// CHECK-NEXT:      MIB.add(MI0.getOperand(0)/*dst*/);
+// CHECK-NEXT:      MIB.add(MI0.getOperand(2)/*src2*/);
+// CHECK-NEXT:      MIB.add(MI0.getOperand(1)/*src1*/);
+// CHECK-NEXT:      for (const auto *FromMI : {&MI0, })
+// CHECK-NEXT:        for (const auto &MMO : FromMI->memoperands())
+// CHECK-NEXT:          MIB.addMemOperand(MMO);
+// CHECK-NEXT:      I.eraseFromParent();
+// CHECK-NEXT:      MachineInstr &NewI = *MIB;
+// CHECK-NEXT:      constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:      return true;
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return false;
+// CHECK-NEXT:  }()) { return true; }
+
+def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
+             []>;
+def Rule4: GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_MUL>], [
+   GIMatchOperand<"dst", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"src1", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"src2", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>]>
+ ],
+ [GIBuildMI<MUL, [GICopyOperand<"dst">, GICopyOperand<"src2">, GICopyOperand<"src1">]>]>;
+
+//===- Test a pattern with ComplexPattern operands. -----------------------===//
+//
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_SUB) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        (selectComplexPattern(MI0.getOperand(2), TempOp0, TempOp1))))) {
+// CHECK-NEXT:          // Rule5
+// CHECK-NEXT:          MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::INSN1));
+// CHECK-NEXT:          MIB.add(MI0.getOperand(0)/*dst*/);
+// CHECK-NEXT:          MIB.add(MI0.getOperand(1)/*src1*/);
+// CHECK-NEXT:          MIB.add(TempOp0);
+// CHECK-NEXT:          MIB.add(TempOp1);
+// CHECK-NEXT:          for (const auto *FromMI : {&MI0, })
+// CHECK-NEXT:            for (const auto &MMO : FromMI->memoperands())
+// CHECK-NEXT:              MIB.addMemOperand(MMO);
+// CHECK-NEXT:          I.eraseFromParent();
+// CHECK-NEXT:          MachineInstr &NewI = *MIB;
+// CHECK-NEXT:          constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:          return true;
+// CHECK-NEXT:        }
+
+def INSN1 : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
+def Rule5 : GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_SUB>], [
+   GIMatchOperand<"dst", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"src1", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"src2", [GIMatchLLT<s32>, GIMatchComplexPattern<gi_complex>]>]>
+ ],
+ [GIBuildMI<INSN1, [
+   GICopyOperand<"dst">,
+   GICopyOperand<"src1">,
+   GIAddComplexOperand<gi_complex, "src2">]>
+ ]>;
+
+//===- Test a simple pattern with a default operand. ----------------------===//
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_XOR) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        (isOperandImmEqual(MI0.getOperand(2), -2, MRI))))) {
+// CHECK-NEXT:      // Rule6
+// CHECK-NEXT:      MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XORI));
+// CHECK-NEXT:      MIB.add(MI0.getOperand(0)/*dst*/);
+// CHECK-NEXT:      MIB.addImm(-1);
+// CHECK-NEXT:      MIB.add(MI0.getOperand(1)/*src1*/);
+// CHECK-NEXT:      for (const auto *FromMI : {&MI0, })
+// CHECK-NEXT:        for (const auto &MMO : FromMI->memoperands())
+// CHECK-NEXT:          MIB.addMemOperand(MMO);
+// CHECK-NEXT:      I.eraseFromParent();
+// CHECK-NEXT:      MachineInstr &NewI = *MIB;
+// CHECK-NEXT:      constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:      return true;
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return false;
+// CHECK-NEXT:  }()) { return true; }
+
+// The -2 is just to distinguish it from the 'not' case below.
+def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1), []>;
+def Rule6 : GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_XOR>], [
+   GIMatchOperand<"dst", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"src1", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"", [GIMatchLLT<s32>, GIMatchInt<-2>]>]>
+ ],
+ [GIBuildMI<XORI, [GICopyOperand<"dst">, GIAddImm<-1>, GICopyOperand<"src1">]>]>;
+
+//===- Test a simple pattern with a default register operand. -------------===//
+//
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_XOR) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* src1 */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        (isOperandImmEqual(MI0.getOperand(2), -3, MRI))))) {
+// CHECK-NEXT:      // Rule7
+// CHECK-NEXT:      MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::XOR));
+// CHECK-NEXT:      MIB.add(MI0.getOperand(0)/*dst*/);
+// CHECK-NEXT:      MIB.addReg(MyTarget::R0);
+// CHECK-NEXT:      MIB.add(MI0.getOperand(1)/*src1*/);
+// CHECK-NEXT:      for (const auto *FromMI : {&MI0, })
+// CHECK-NEXT:        for (const auto &MMO : FromMI->memoperands())
+// CHECK-NEXT:          MIB.addMemOperand(MMO);
+// CHECK-NEXT:      I.eraseFromParent();
+// CHECK-NEXT:      MachineInstr &NewI = *MIB;
+// CHECK-NEXT:      constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:      return true;
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return false;
+// CHECK-NEXT:  }()) { return true; }
+
+// The -3 is just to distinguish it from the 'not' case below and the other default op case above.
+def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1), []>;
+def Rule7 : GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_XOR>], [
+   GIMatchOperand<"dst", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"src1", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"", [GIMatchLLT<s32>, GIMatchInt<-3>]>]>
+ ],
+ [GIBuildMI<XOR, [GICopyOperand<"dst">, GIAddRegister<R0>, GICopyOperand<"src1">]>]>;
+
+//===- Test a simple pattern with constant immediate operands. ------------===//
+//
+// This must precede the 3-register variants because constant immediates have
+// priority over register banks.
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:    MachineInstr &MI0 = I;
+// CHECK-NEXT:    if (MI0.getNumOperands() < 3)
+// CHECK-NEXT:      return false;
+// CHECK-NEXT:    if ((MI0.getOpcode() == TargetOpcode::G_XOR) &&
+// CHECK-NEXT:        ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* Wm */ (MRI.getType(MI0.getOperand(1).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:         ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(1).getReg(), MRI, TRI))))) &&
+// CHECK-NEXT:        ((/* Operand 2 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
+// CHECK-NEXT:        (isOperandImmEqual(MI0.getOperand(2), -1, MRI))))) {
+// CHECK-NEXT:      // Rule8
+// CHECK-NEXT:      MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::ORN));
+// CHECK-NEXT:      MIB.add(MI0.getOperand(0)/*dst*/);
+// CHECK-NEXT:      MIB.addReg(MyTarget::R0);
+// CHECK-NEXT:      MIB.add(MI0.getOperand(1)/*Wm*/);
+// CHECK-NEXT:      for (const auto *FromMI : {&MI0, })
+// CHECK-NEXT:        for (const auto &MMO : FromMI->memoperands())
+// CHECK-NEXT:          MIB.addMemOperand(MMO);
+// CHECK-NEXT:      I.eraseFromParent();
+// CHECK-NEXT:      MachineInstr &NewI = *MIB;
+// CHECK-NEXT:      constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:      return true;
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return false;
+// CHECK-NEXT:  }()) { return true; }
+
+def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
+def Rule8 : GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_XOR>], [
+   GIMatchOperand<"dst", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"Wm", [GIMatchLLT<s32>, GIMatchRegBankForClass<GPR32>]>,
+   GIMatchOperand<"", [GIMatchLLT<s32>, GIMatchInt<-1>]>]>
+ ],
+ [GIBuildMI<ORN, [GICopyOperand<"dst">, GIAddRegister<R0>, GICopyOperand<"Wm">]>]>;
+
+//===- Test a pattern with an MBB operand. --------------------------------===//
+
+// CHECK-LABEL: if ([&]() {
+// CHECK-NEXT:      MachineInstr &MI0 = I;
+// CHECK-NEXT:      if (MI0.getNumOperands() < 1)
+// CHECK-NEXT:        return false;
+// CHECK-NEXT:      if ((MI0.getOpcode() == TargetOpcode::G_BR) &&
+// CHECK-NEXT:          ((/* target */ (MI0.getOperand(0).isMBB())))) {
+
+// CHECK-NEXT:       // (br (bb:Other):$target) => (BR (bb:Other):$target)
+// CHECK-NEXT:       I.setDesc(TII.get(MyTarget::BR));
+// CHECK-NEXT:       MachineInstr &NewI = I;
+// CHECK-NEXT:       constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
+// CHECK-NEXT:       return true;
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return false;
+// CHECK-NEXT:  }()) { return true; }
+
+def BR : I<(outs), (ins unknown:$target),
+            [(br bb:$target)]>;
+def : GIRule<
+ [GIMatchInsn<[GIMatchOpcode<G_BR>], [GIMatchOperand<"target", [GIMatchMBB]>]>],
+ [GIBuildMI<BR, [GICopyOperand<"target">]>]>;

utils/TableGen/GlobalISelEmitter.cpp

static cl::opt<bool> WarnOnSkippedPatterns(
     "warn-on-skipped-patterns",
     cl::desc("Explain why a pattern was skipped for inclusion "
              "in the GlobalISel selector"),
     cl::init(false), cl::cat(GlobalISelEmitterCat));
 
 namespace {
 //===- Helper functions ---------------------------------------------------===//
 
+class IndentStr {
+private:
+  unsigned Indent;
+
+public:
+  IndentStr(unsigned Indent) : Indent(Indent) {}
+
+  unsigned get() const { return Indent; }
+};
+
+IndentStr operator+(IndentStr Indent, unsigned N) {
+  return IndentStr(Indent.get() + N);
+}
+
+raw_ostream &operator<<(raw_ostream &OS, IndentStr Indent) {
+  OS << std::string(Indent.get(), ' ');
+  return OS;
+}
+
 /// This class stands in for LLT wherever we want to tablegen-erate an
 /// equivalent at compiler run-time.
 class LLTCodeGen {
 private:
   LLT Ty;
 
 public:
   LLTCodeGen(const LLT &Ty) : Ty(Ty) {}
public:
 
   const LLT &get() const { return Ty; }
 };
 
 class InstructionMatcher;
 class OperandPlaceholder {
 private:
   enum PlaceholderKind {
-    OP_MatchReference,
     OP_Temporary,
   } Kind;
 
-  struct MatchReferenceData {
-    InstructionMatcher *InsnMatcher;
-    StringRef InsnVarName;
-    StringRef SymbolicName;
-  };
-
   struct TemporaryData {
     unsigned OpIdx;
   };
 
   union {
-    struct MatchReferenceData MatchReference;
     struct TemporaryData Temporary;
   };
 
   OperandPlaceholder(PlaceholderKind Kind) : Kind(Kind) {}
 
 public:
   ~OperandPlaceholder() {}
 
-  static OperandPlaceholder
-  CreateMatchReference(InstructionMatcher *InsnMatcher,
-                       StringRef InsnVarName, StringRef SymbolicName) {
-    OperandPlaceholder Result(OP_MatchReference);
-    Result.MatchReference.InsnMatcher = InsnMatcher;
-    Result.MatchReference.InsnVarName = InsnVarName;
-    Result.MatchReference.SymbolicName = SymbolicName;
-    return Result;
-  }
-
   static OperandPlaceholder CreateTemporary(unsigned OpIdx) {
     OperandPlaceholder Result(OP_Temporary);
     Result.Temporary.OpIdx = OpIdx;
     return Result;
   }
 
   void emitCxxValueExpr(raw_ostream &OS) const;
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const;
 };
 
 /// Convert an MVT to an equivalent LLT if possible, or the invalid LLT() for
 /// MVTs that don't map cleanly to an LLT (e.g., iPTR, *any, ...).
 static Optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) {
   MVT VT(SVT);
   if (VT.isVector() && VT.getVectorNumElements() != 1)
     return LLTCodeGen(LLT::vector(VT.getVectorNumElements(), VT.getScalarSizeInBits()));
public:
 
   std::string defineInsnVar(raw_ostream &OS, const InstructionMatcher &Matcher,
                             StringRef Value);
   StringRef getInsnVarName(const InstructionMatcher &InsnMatcher) const;
 
   void emitCxxCapturedInsnList(raw_ostream &OS);
   void emitCxxCaptureStmts(raw_ostream &OS, StringRef Expr);
 
+  void emitTblgen(raw_ostream &OS, IndentStr Indent);
   void emit(raw_ostream &OS);
 
   /// Compare the priority of this object and B.
   ///
   /// Returns true if this object is more important than B.
   bool isHigherPriorityThan(const RuleMatcher &B) const;
 
   /// Report the maximum number of temporary operands needed by the rule
   /// matcher.
   unsigned countTemporaryOperands() const;
+
+  // FIXME: Remove this as soon as possible
+  InstructionMatcher &insnmatcher_front() const { return *Matchers.front(); }
 };
 
 template <class PredicateTy> class PredicateListMatcher {
 private:
   typedef std::vector<std::unique_ptr<PredicateTy>> PredicateVec;
   PredicateVec Predicates;
 
 public:
public:
   /// This enum is used for RTTI and also defines the priority that is given to
   /// the predicate when generating the matcher code. Kinds with higher priority
   /// must be tested first.
   ///
   /// The relative priority of OPM_LLT, OPM_RegBank, and OPM_MBB do not matter
   /// but OPM_Int must have priority over OPM_RegBank since constant integers
   /// are represented by a virtual register defined by a G_CONSTANT instruction.
   enum PredicateKind {
+    OPM_Arbitrary,
     OPM_ComplexPattern,
     OPM_Instruction,
     OPM_Int,
     OPM_LLT,
     OPM_RegBank,
     OPM_MBB,
   };
 
public:
   /// Only InstructionOperandMatcher needs to do anything for this method.
   virtual void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule,
                                    StringRef Expr) const {}
 
   /// Emit a C++ expression that checks the predicate for the given operand.
   virtual void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
                                     StringRef OperandExpr) const = 0;
 
+  virtual void emitTblgen(raw_ostream &OS, IndentStr Indent) const = 0;
+
   /// Compare the priority of this object and B.
   ///
   /// Returns true if this object is more important than B.
   virtual bool isHigherPriorityThan(const OperandPredicateMatcher &B) const {
     return Kind < B.Kind;
   };
 
   /// Report the maximum number of temporary operands needed by the predicate
public:
   }
 
   void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
                             StringRef OperandExpr) const override {
     OS << "MRI.getType(" << OperandExpr << ".getReg()) == (";
     Ty.emitCxxConstructorCall(OS);
     OS << ")";
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GIMatchLLT<" << Ty.get() << ">";
+  }
 };
 
 /// Generates code to check that an operand is a particular target constant.
 class ComplexPatternOperandMatcher : public OperandPredicateMatcher {
 protected:
   const OperandMatcher &Operand;
   const Record &TheDef;
 
void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
     for (unsigned I = 0; I < getNumOperands(); ++I) {
       OS << ", ";
       OperandPlaceholder::CreateTemporary(getAllocatedTemporariesBaseID() + I)
           .emitCxxValueExpr(OS);
     }
     OS << ")";
   }
 
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GIMatchComplexPattern<" << TheDef.getName() << ">";
+  }
+
   unsigned countTemporaryOperands() const override {
     return getNumOperands();
   }
 };
 
 /// Generates code to check that an operand is in a particular register bank.
 class RegisterBankOperandMatcher : public OperandPredicateMatcher {
 protected:
   const CodeGenRegisterClass &RC;
 
 public:
   RegisterBankOperandMatcher(const CodeGenRegisterClass &RC)
       : OperandPredicateMatcher(OPM_RegBank), RC(RC) {}
 
   static bool classof(const OperandPredicateMatcher *P) {
     return P->getKind() == OPM_RegBank;
   }
 
   void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
                             StringRef OperandExpr) const override {
     OS << "(&RBI.getRegBankFromRegClass(" << RC.getQualifiedName()
        << "RegClass) == RBI.getRegBank(" << OperandExpr
        << ".getReg(), MRI, TRI))";
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GIMatchRegBankForClass<" << RC.getName() << ">";
+  }
 };
 
 /// Generates code to check that an operand is a basic block.
 class MBBOperandMatcher : public OperandPredicateMatcher {
 public:
   MBBOperandMatcher() : OperandPredicateMatcher(OPM_MBB) {}
 
   static bool classof(const OperandPredicateMatcher *P) {
     return P->getKind() == OPM_MBB;
   }
 
   void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
                             StringRef OperandExpr) const override {
     OS << OperandExpr << ".isMBB()";
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << "GIMatchMBB";
+  }
 };
 
 /// Generates code to check that an operand is a particular int.
 class IntOperandMatcher : public OperandPredicateMatcher {
 protected:
   int64_t Value;
 
 public:
   IntOperandMatcher(int64_t Value)
       : OperandPredicateMatcher(OPM_Int), Value(Value) {}
 
   static bool classof(const OperandPredicateMatcher *P) {
     return P->getKind() == OPM_Int;
   }
 
   void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
                             StringRef OperandExpr) const override {
     OS << "isOperandImmEqual(" << OperandExpr << ", " << Value << ", MRI)";
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << "GIMatchInt<" << Value << ">";
+  }
+};
+
+/// Generates code to check that an an arbitrary predicate.
+class ArbitraryOperandPredicateMatcher : public OperandPredicateMatcher {
+protected:
+  TreePredicateFn Predicate;
+
+public:
+  ArbitraryOperandPredicateMatcher(const TreePredicateFn &Predicate)
+      : OperandPredicateMatcher(OPM_Arbitrary), Predicate(Predicate) {}
+
+  static bool classof(const OperandPredicateMatcher *P) {
+    return P->getKind() == OPM_Arbitrary;
+  }
+
+  void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
+                            StringRef OperandExpr) const override {
+    OS << Predicate.getFnName() << "(" << OperandExpr << ", MRI)";
+  }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << "GIMatchCode<...>";
+  }
 };
 
 /// Generates code to check that a set of predicates match for a particular
 /// operand.
 class OperandMatcher : public PredicateListMatcher<OperandPredicateMatcher> {
 protected:
   InstructionMatcher &Insn;
   unsigned OpIdx;
if (SymbolicName.empty())
       OS << "Operand " << OpIdx;
     else
       OS << SymbolicName;
     OS << " */ ";
     emitCxxPredicateListExpr(OS, Rule, getOperandExpr(InsnVarName));
     OS << ")";
   }
 
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const {
+    OS << Indent << "GIMatchOperand<\"" << SymbolicName << "\", [\n";
+    Indent = Indent + 1;
+    StringRef Separator = "";
+    for (const auto &Predicate : predicates()) {
+      OS << Separator;
+      Predicate->emitTblgen(OS, Indent+1);
+      Separator = ",\n";
+    }
+    OS << "]>";
+  }
+
   /// Compare the priority of this object and B.
   ///
   /// Returns true if this object is more important than B.
   bool isHigherPriorityThan(const OperandMatcher &B) const {
     // Operand matchers involving more predicates have higher priority.
     if (predicates_size() > B.predicates_size())
       return true;
     if (predicates_size() < B.predicates_size())
public:
 
   PredicateKind getKind() const { return Kind; }
 
   /// Emit a C++ expression that tests whether the instruction named in
   /// InsnVarName matches the predicate.
   virtual void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
                                     StringRef InsnVarName) const = 0;
 
+  virtual void emitTblgen(raw_ostream &OS, IndentStr Indent) const = 0;
+
   /// Compare the priority of this object and B.
   ///
   /// Returns true if this object is more important than B.
   virtual bool isHigherPriorityThan(const InstructionPredicateMatcher &B) const {
     return Kind < B.Kind;
   };
 
   /// Report the maximum number of temporary operands needed by the predicate
public:
   }
 
   void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
                             StringRef InsnVarName) const override {
     OS << InsnVarName << ".getOpcode() == " << I->Namespace
        << "::" << I->TheDef->getName();
   }
 
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GIMatchOpcode<" << I->TheDef->getName() << ">";
+  }
+
   /// Compare the priority of this object and B.
   ///
   /// Returns true if this object is more important than B.
   bool isHigherPriorityThan(const InstructionPredicateMatcher &B) const override {
     if (InstructionPredicateMatcher::isHigherPriorityThan(B))
       return true;
     if (B.InstructionPredicateMatcher::isHigherPriorityThan(*this))
       return false;
getOptionalOperand(StringRef SymbolicName) const {
     }
     return None;
   }
 
   const OperandMatcher &getOperand(StringRef SymbolicName) const {
     Optional<const OperandMatcher *>OM = getOptionalOperand(SymbolicName);
     if (OM.hasValue())
       return *OM.getValue();
-    llvm_unreachable("Failed to lookup operand");
+    llvm_unreachable(("Failed to lookup operand " + SymbolicName).str().c_str());
   }
 
   unsigned getNumOperands() const { return Operands.size(); }
   OperandVec::iterator operands_begin() { return Operands.begin(); }
   OperandVec::iterator operands_end() { return Operands.end(); }
   iterator_range<OperandVec::iterator> operands() {
     return make_range(operands_begin(), operands_end());
   }
void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
     emitCxxPredicateListExpr(OS, Rule, InsnVarName);
     for (const auto &Operand : Operands) {
       OS << " &&\n(";
       Operand->emitCxxPredicateExpr(OS, Rule, InsnVarName);
       OS << ")";
     }
   }
 
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) {
+    OS << Indent << "GIMatchInsn<[\n";
+    Indent = Indent + 1;
+    StringRef Separator = "";
+    for (const auto &Predicate : predicates()) {
+      OS << Separator;
+      Predicate->emitTblgen(OS, Indent+1);
+      Separator = ",\n";
+    }
+    OS << "\n" << Indent << "], [\n";
+    Separator = "";
+    for (const auto &Operand : Operands) {
+      OS << Separator;
+      Operand->emitTblgen(OS, Indent+1);
+      Separator = ",\n";
+    }
+    OS << "]>\n";
+  }
+
   /// Compare the priority of this object and B.
   ///
   /// Returns true if this object is more important than B.
   bool isHigherPriorityThan(const InstructionMatcher &B) const {
     // Instruction matchers involving more operands have higher priority.
     if (Operands.size() > B.Operands.size())
       return true;
     if (Operands.size() < B.Operands.size())
public:
 
   void emitCxxPredicateExpr(raw_ostream &OS, RuleMatcher &Rule,
                             StringRef OperandExpr) const override {
     OperandExpr = Rule.getInsnVarName(*InsnMatcher);
     OS << "(";
     InsnMatcher->emitCxxPredicateExpr(OS, Rule, OperandExpr);
     OS << ")\n";
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GIMatchSubInsn<\n";
+    InsnMatcher->emitTblgen(OS, Indent + 1);
+    OS << ">";
+  }
 };
 
 //===- Actions ------------------------------------------------------------===//
 void OperandPlaceholder::emitCxxValueExpr(raw_ostream &OS) const {
   switch (Kind) {
-  case OP_MatchReference:
-    OS << MatchReference.InsnMatcher->getOperand(MatchReference.SymbolicName)
-              .getOperandExpr(MatchReference.InsnVarName);
+  case OP_Temporary:
+    OS << "TempOp" << Temporary.OpIdx;
     break;
+  }
+}
+
+void OperandPlaceholder::emitTblgen(raw_ostream &OS, IndentStr Indent) const {
+  switch (Kind) {
   case OP_Temporary:
     OS << "TempOp" << Temporary.OpIdx;
     break;
   }
 }
 
 class OperandRenderer {
 public:
   enum RendererKind { OR_Copy, OR_Imm, OR_Register, OR_ComplexPattern };
 
 protected:
   RendererKind Kind;
 
 public:
   OperandRenderer(RendererKind Kind) : Kind(Kind) {}
   virtual ~OperandRenderer() {}
 
   RendererKind getKind() const { return Kind; }
 
   virtual void emitCxxRenderStmts(raw_ostream &OS, RuleMatcher &Rule) const = 0;
+  virtual void emitTblgen(raw_ostream &OS, IndentStr Indent) const = 0;
 };
 
 /// A CopyRenderer emits code to copy a single operand from an existing
 /// instruction to the one being built.
 class CopyRenderer : public OperandRenderer {
 protected:
   /// The matcher for the instruction that this operand is copied from.
   /// This provides the facility for looking up an a operand by it's name so
   /// that it can be used as a source for the instruction being built.
   const InstructionMatcher &Matched;
   /// The name of the operand.
-  const StringRef SymbolicName;
+  std::string SymbolicName;
 
 public:
   CopyRenderer(const InstructionMatcher &Matched, StringRef SymbolicName)
       : OperandRenderer(OR_Copy), Matched(Matched), SymbolicName(SymbolicName) {
   }
 
   static bool classof(const OperandRenderer *R) {
     return R->getKind() == OR_Copy;
   }
 
   const StringRef getSymbolicName() const { return SymbolicName; }
 
   void emitCxxRenderStmts(raw_ostream &OS, RuleMatcher &Rule) const override {
     const OperandMatcher &Operand = Matched.getOperand(SymbolicName);
     StringRef InsnVarName =
         Rule.getInsnVarName(Operand.getInstructionMatcher());
     std::string OperandExpr = Operand.getOperandExpr(InsnVarName);
     OS << "    MIB.add(" << OperandExpr << "/*" << SymbolicName << "*/);\n";
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GICopyOperand<\"" << SymbolicName << "\">";
+  }
 };
 
 /// Adds a specific physical register to the instruction being built.
 /// This is typically useful for WZR/XZR on AArch64.
 class AddRegisterRenderer : public OperandRenderer {
 protected:
   const Record *RegisterDef;
 
 public:
   AddRegisterRenderer(const Record *RegisterDef)
       : OperandRenderer(OR_Register), RegisterDef(RegisterDef) {}
 
   static bool classof(const OperandRenderer *R) {
     return R->getKind() == OR_Register;
   }
 
   void emitCxxRenderStmts(raw_ostream &OS, RuleMatcher &Rule) const override {
     OS << "    MIB.addReg(" << RegisterDef->getValueAsString("Namespace")
        << "::" << RegisterDef->getName() << ");\n";
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GIAddRegister<" << RegisterDef->getName() << ">";
+  }
 };
 
 /// Adds a specific immediate to the instruction being built.
 class ImmRenderer : public OperandRenderer {
 protected:
   int64_t Imm;
 
 public:
   ImmRenderer(int64_t Imm)
       : OperandRenderer(OR_Imm), Imm(Imm) {}
 
   static bool classof(const OperandRenderer *R) {
     return R->getKind() == OR_Imm;
   }
 
   void emitCxxRenderStmts(raw_ostream &OS, RuleMatcher &Rule) const override {
     OS << "    MIB.addImm(" << Imm << ");\n";
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GIAddImm<" << Imm << ">";
+  }
 };
 
 class RenderComplexPatternOperand : public OperandRenderer {
 private:
   const Record &TheDef;
+  /// The name of the operand.
+  const StringRef SymbolicName;
   std::vector<OperandPlaceholder> Sources;
 
   unsigned getNumOperands() const {
     return TheDef.getValueAsDag("Operands")->getNumArgs();
   }
 
 public:
-  RenderComplexPatternOperand(const Record &TheDef,
+  RenderComplexPatternOperand(const Record &TheDef, StringRef SymbolicName,
                               const ArrayRef<OperandPlaceholder> Sources)
-      : OperandRenderer(OR_ComplexPattern), TheDef(TheDef), Sources(Sources) {}
+      : OperandRenderer(OR_ComplexPattern), TheDef(TheDef),
+        SymbolicName(SymbolicName), Sources(Sources) {}
 
   static bool classof(const OperandRenderer *R) {
     return R->getKind() == OR_ComplexPattern;
   }
 
   void emitCxxRenderStmts(raw_ostream &OS, RuleMatcher &Rule) const override {
     assert(Sources.size() == getNumOperands() && "Inconsistent number of operands");
     for (const auto &Source : Sources) {
       OS << "MIB.add(";
       Source.emitCxxValueExpr(OS);
       OS << ");\n";
     }
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GIAddComplexOperand<" << TheDef.getName() << ", \""
+       << SymbolicName << "\" /* ";
+    StringRef Separator = "";
+    for (const OperandPlaceholder &Placeholder : Sources) {
+      OS << Separator;
+      Placeholder.emitTblgen(OS, Indent);
+      Separator = ", ";
+    }
+    OS << " */>";
+  }
 };
 
 /// An action taken when all Matcher predicates succeeded for a parent rule.
 ///
 /// Typical actions include:
 /// * Changing the opcode of an instruction.
 /// * Adding an operand to an instruction.
 class MatchAction {
 public:
   virtual ~MatchAction() {}
 
   /// Emit the C++ statements to implement the action.
   ///
   /// \param RecycleVarName If given, it's an instruction to recycle. The
   ///                       requirements on the instruction vary from action to
   ///                       action.
   virtual void emitCxxActionStmts(raw_ostream &OS, RuleMatcher &Rule,
                                   StringRef RecycleVarName) const = 0;
+
+  virtual void emitTblgen(raw_ostream &OS, IndentStr Indent) const = 0;
 };
 
 /// Generates a comment describing the matched rule being acted upon.
 class DebugCommentAction : public MatchAction {
 private:
-  const PatternToMatch &P;
+  std::string Comment;
 
 public:
-  DebugCommentAction(const PatternToMatch &P) : P(P) {}
+  DebugCommentAction(StringRef Comment) : Comment(Comment) {}
 
   void emitCxxActionStmts(raw_ostream &OS, RuleMatcher &Rule,
                           StringRef RecycleVarName) const override {
-    OS << "// " << *P.getSrcPattern() << "  =>  " << *P.getDstPattern() << "\n";
+    OS << "// " << Comment << "\n";
+  }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "// " << Comment << "\n";
   }
 };
 
 /// Generates code to build an instruction or mutate an existing instruction
 /// into the desired instruction when this is possible.
 class BuildMIAction : public MatchAction {
 private:
   const CodeGenInstruction *I;
void emitCxxActionStmts(raw_ostream &OS, RuleMatcher &Rule,
     OS << "    for (const auto *FromMI : ";
     Rule.emitCxxCapturedInsnList(OS);
     OS << ")\n";
     OS << "      for (const auto &MMO : FromMI->memoperands())\n";
     OS << "        MIB.addMemOperand(MMO);\n";
     OS << "    " << RecycleVarName << ".eraseFromParent();\n";
     OS << "    MachineInstr &NewI = *MIB;\n";
   }
+
+  void emitTblgen(raw_ostream &OS, IndentStr Indent) const override {
+    OS << Indent << "GIBuildMI<" << I->TheDef->getName() << ", [\n";
+    Indent = Indent + 1;
+    StringRef Separator = "";
+    for (const auto &Renderer : OperandRenderers) {
+      OS << Separator;
+      Renderer->emitTblgen(OS, Indent + 1);
+      Separator = ",\n";
+    }
+    OS << Indent << "]>\n";
+  }
 };
 
 InstructionMatcher &RuleMatcher::addInstructionMatcher() {
   Matchers.emplace_back(new InstructionMatcher());
   return *Matchers.back();
 }
 
 template <class Kind, class... Args>

 /// Emit C++ statements to check the shape of the match and capture
 /// instructions into local variables.
 void RuleMatcher::emitCxxCaptureStmts(raw_ostream &OS, StringRef Expr) {
   assert(Matchers.size() == 1 && "Cannot handle multi-root matchers yet");
   std::string InsnVarName = defineInsnVar(OS, *Matchers.front(), Expr);
   Matchers.front()->emitCxxCaptureStmts(OS, *this, InsnVarName);
 }
 
+void RuleMatcher::emitTblgen(raw_ostream &OS, IndentStr Indent) {
+  OS << "#if 0\n";
+  OS << "GIRule<[\n";
+  Indent = Indent + 1;
+  for (const auto &Matcher : Matchers)
+    Matcher->emitTblgen(OS, Indent + 1);
+  OS << Indent << "], [\n";
+  for (const auto &Action : Actions)
+    Action->emitTblgen(OS, Indent + 1);
+  OS << Indent << "]>\n";
+  OS << "#endif // 0\n";
+}
+
 void RuleMatcher::emit(raw_ostream &OS) {
   if (Matchers.empty())
     llvm_unreachable("Unexpected empty matcher!");
 
   // The representation supports rules that require multiple roots such as:
   //    %ptr(p0) = ...
   //    %elt0(s32) = G_LOAD %ptr
   //    %1(p0) = G_ADD %ptr, 4
Expected<BuildMIAction &> createAndImportInstructionRenderer(
       const InstructionMatcher &InsnMatcher) const;
   Error importExplicitUseRenderer(BuildMIAction &DstMIBuilder,
                                   TreePatternNode *DstChild,
                                   const InstructionMatcher &InsnMatcher) const;
   Error
   importImplicitDefRenderers(BuildMIAction &DstMIBuilder,
                              const std::vector<Record *> &ImplicitDefs) const;
 
+  void parseGIMatchInsnPredicates(const std::vector<Record *> &PredicateDefs,
+                                  InstructionMatcher &InsnMatcher) const;
+  void parseGIMatchOperands(const std::vector<Record *> &OperandDefs,
+                            InstructionMatcher &InsnMatcher,
+                            unsigned &TempOpIdx) const;
+  void parseGIMatchOperandPredicates(const std::vector<Record *> &PredicateDefs,
+                                     OperandMatcher &OpndMatcher,
+                                     unsigned &TempOpIdx) const;
+  void parseGIMatchInsn(Record *InsnMatchDef, InstructionMatcher &InsnMatcher,
+                        unsigned &TempOpIdx) const;
+
   /// Analyze pattern \p P, returning a matcher for it if possible.
   /// Otherwise, return an Error explaining why we don't support it.
   Expected<RuleMatcher> runOnPattern(const PatternToMatch &P);
 };
 
 void GlobalISelEmitter::gatherNodeEquivs() {
   assert(NodeEquivs.empty());
   for (Record *Equiv : RK.getAllDerivedDefinitions("GINodeEquiv"))

 
 Error GlobalISelEmitter::importChildMatcher(InstructionMatcher &InsnMatcher,
                                             TreePatternNode *SrcChild,
                                             unsigned OpIdx,
                                             unsigned &TempOpIdx) const {
   OperandMatcher &OM =
       InsnMatcher.addOperand(OpIdx, SrcChild->getName(), TempOpIdx);
 
-  if (SrcChild->hasAnyPredicate())
-    return failedImport("Src pattern child has predicate (" +
-                        explainPredicates(SrcChild) + ")");
+  for (const auto &P : SrcChild->getPredicateFns()) {
+    if (P.isAlwaysTrue())
+      continue;
+    OM.addPredicate<ArbitraryOperandPredicateMatcher>(P);
+  }
 
   ArrayRef<EEVT::TypeSet> ChildTypes = SrcChild->getExtTypes();
   if (ChildTypes.size() != 1)
     return failedImport("Src pattern child has multiple results");
 
   // Check MBB's before the type check since they are not a known type.
   if (!SrcChild->isLeaf()) {
     if (SrcChild->getOperator()->isSubClassOf("SDNode")) {
if (!DstChild->isLeaf()) {
     if (DstChild->getOperator()->isSubClassOf("SDNode")) {
       auto &ChildSDNI = CGP.getSDNodeInfo(DstChild->getOperator());
       if (ChildSDNI.getSDClassName() == "BasicBlockSDNode") {
         DstMIBuilder.addRenderer<CopyRenderer>(InsnMatcher,
                                                DstChild->getName());
         return Error::success();
       }
     }
-    return failedImport("Dst pattern child isn't a leaf node or an MBB");
+
+    if (DstChild->getOperator()->isSubClassOf("SDNodeXForm"))
+      return failedImport("Dst pattern child isn't a leaf node or an MBB (it's "
+                          "an SDNodeXForm)");
+
+    return failedImport("Dst pattern child isn't a leaf node or an MBB (" +
+                        DstChild->getOperator()->getName() + ")");
   }
 
   // Otherwise, we're looking for a bog-standard RegisterClass operand.
   if (DstChild->hasAnyPredicate())
     return failedImport("Dst pattern child has predicate (" +
                         explainPredicates(DstChild) + ")");
 
   if (auto *ChildDefInit = dyn_cast<DefInit>(DstChild->getLeafValue())) {
if (ChildRec->isSubClassOf("ComplexPattern")) {
             "SelectionDAG ComplexPattern not mapped to GlobalISel");
 
       SmallVector<OperandPlaceholder, 2> RenderedOperands;
       const OperandMatcher &OM = InsnMatcher.getOperand(DstChild->getName());
       for (unsigned I = 0; I < OM.countTemporaryOperands(); ++I)
         RenderedOperands.push_back(OperandPlaceholder::CreateTemporary(
             OM.getAllocatedTemporariesBaseID() + I));
       DstMIBuilder.addRenderer<RenderComplexPatternOperand>(
-          *ComplexPattern->second, RenderedOperands);
+          *ComplexPattern->second, DstChild->getName(), RenderedOperands);
       return Error::success();
     }
 
     if (ChildRec->isSubClassOf("SDNodeXForm"))
       return failedImport("Dst pattern child def is an unsupported tablegen "
                           "class (SDNodeXForm)");
 
     return failedImport(
Error GlobalISelEmitter::importImplicitDefRenderers(
   if (!ImplicitDefs.empty())
     return failedImport("Pattern defines a physical register");
   return Error::success();
 }
 
 Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
   // Keep track of the matchers and actions to emit.
   RuleMatcher M;
-  M.addAction<DebugCommentAction>(P);
+  M.addAction<DebugCommentAction>(llvm::to_string(*P.getSrcPattern()) +
+                                  "  =>  " +
+                                  llvm::to_string(*P.getDstPattern()));
 
   if (auto Error = importRulePredicates(M, P.getPredicates()->getValues()))
     return std::move(Error);
 
   // Next, analyze the pattern operators.
   TreePatternNode *Src = P.getSrcPattern();
   TreePatternNode *Dst = P.getDstPattern();
 
Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
   if (auto Error = importImplicitDefRenderers(DstMIBuilder, P.getDstRegs()))
     return std::move(Error);
 
   // We're done with this pattern!  It's eligible for GISel emission; return it.
   ++NumPatternImported;
   return std::move(M);
 }
 
+void GlobalISelEmitter::parseGIMatchInsnPredicates(
+    const std::vector<Record *> &PredicateDefs,
+    InstructionMatcher &InsnMatcher) const {
+  for (Record *PredicateDef : PredicateDefs) {
+    if (PredicateDef->isSubClassOf("GIMatchOpcode")) {
+      InsnMatcher.addPredicate<InstructionOpcodeMatcher>(
+          &Target.getInstruction(PredicateDef->getValueAsDef("Insn")));
+
+      continue;
+    }
+
+    PrintFatalError(PredicateDef->getLoc(), "Matcher was not a GIMatchInsn");
+  }
+}
+
+void GlobalISelEmitter::parseGIMatchOperandPredicates(
+    const std::vector<Record *> &PredicateDefs, OperandMatcher &OpndMatcher,
+    unsigned &TempOpIdx) const {
+  for (Record *PredicateMatchDef : PredicateDefs) {
+    if (PredicateMatchDef->isSubClassOf("GIMatchLLT")) {
+      Record *LLTDef = PredicateMatchDef->getValueAsDef("Type");
+      if (LLTDef->isSubClassOf("LLTScalar")) {
+        OpndMatcher.addPredicate<LLTOperandMatcher>(
+            LLTCodeGen(LLT::scalar(LLTDef->getValueAsInt("SizeInBits"))));
+
+        continue;
+      }
+      PrintFatalError(LLTDef->getLoc(), "Unknown LLT");
+    }
+
+    if (PredicateMatchDef->isSubClassOf("GIMatchRegBankForClass")) {
+      Record *RCDef = PredicateMatchDef->getValueAsDef("RC");
+      OpndMatcher.addPredicate<RegisterBankOperandMatcher>(
+          Target.getRegisterClass(RCDef));
+
+      continue;
+    }
+
+    if (PredicateMatchDef->isSubClassOf("GIMatchComplexPattern")) {
+      Record *CPDef = PredicateMatchDef->getValueAsDef("Matcher");
+      auto &Predicate = OpndMatcher.addPredicate<ComplexPatternOperandMatcher>(
+          OpndMatcher, *CPDef);
+      TempOpIdx += Predicate.countTemporaryOperands();
+
+      continue;
+    }
+
+    if (PredicateMatchDef->isSubClassOf("GIMatchInt")) {
+      OpndMatcher.addPredicate<IntOperandMatcher>(
+          PredicateMatchDef->getValueAsInt("Value"));
+      continue;
+    }
+
+    if (PredicateMatchDef->isSubClassOf("GIMatchSubInsn")) {
+      auto &Predicate = OpndMatcher.addPredicate<InstructionOperandMatcher>();
+      parseGIMatchInsn(PredicateMatchDef->getValueAsDef("Insn"),
+                       Predicate.getInsnMatcher(), TempOpIdx);
+      continue;
+    }
+
+    if (PredicateMatchDef->isSubClassOf("GIMatchMBBImpl")) {
+      OpndMatcher.addPredicate<MBBOperandMatcher>();
+      continue;
+    }
+
+    PrintFatalError(PredicateMatchDef->getLoc(),
+                    "Matcher was not a GIMatchOperandPredicate");
+  }
+}
+
+void GlobalISelEmitter::parseGIMatchOperands(
+    const std::vector<Record *> &OperandDefs, InstructionMatcher &InsnMatcher,
+    unsigned &TempOpIdx) const {
+  unsigned OpIdx = 0;
+  for (Record *OperandMatchDef : OperandDefs) {
+    if (OperandMatchDef->isSubClassOf("GIMatchOperand")) {
+      OperandMatcher &OpndMatcher = InsnMatcher.addOperand(
+          OpIdx++, OperandMatchDef->getValueAsString("Name"), TempOpIdx);
+
+      parseGIMatchOperandPredicates(
+          OperandMatchDef->getValueAsListOfDefs("Predicates"), OpndMatcher,
+          TempOpIdx);
+      continue;
+    }
+
+    PrintFatalError(OperandMatchDef->getLoc(), "Matcher was not a GIMatchInsn");
+  }
+}
+
+void GlobalISelEmitter::parseGIMatchInsn(Record *InsnMatchDef,
+                                         InstructionMatcher &InsnMatcher,
+                                         unsigned &TempOpIdx) const {
+  assert(InsnMatchDef->isSubClassOf("GIMatchInsn"));
+  parseGIMatchInsnPredicates(InsnMatchDef->getValueAsListOfDefs("Predicates"),
+                             InsnMatcher);
+
+  parseGIMatchOperands(InsnMatchDef->getValueAsListOfDefs("Operands"),
+                       InsnMatcher, TempOpIdx);
+}
+
 void GlobalISelEmitter::run(raw_ostream &OS) {
   // Track the GINodeEquiv definitions.
   gatherNodeEquivs();
 
   emitSourceFileHeader(("Global Instruction Selector for the " +
                        Target.getName() + " target").str(), OS);
   std::vector<RuleMatcher> Rules;
   // Look through the SelectionDAG patterns we found, possibly emitting some.
if (auto Err = MatcherOrErr.takeError()) {
       }
       ++NumPatternImportsSkipped;
       continue;
     }
 
     Rules.push_back(std::move(MatcherOrErr.get()));
   }
 
+  for (Record *RuleDef : RK.getAllDerivedDefinitions("GIRule")) {
+    RuleMatcher Matcher;
+
+    unsigned TempOpIdx = 0;
+    for (Record *InsnMatchDef : RuleDef->getValueAsListOfDefs("InsnMatchers")) {
+      InstructionMatcher &InsnMatcher = Matcher.addInstructionMatcher();
+      parseGIMatchInsn(InsnMatchDef, InsnMatcher, TempOpIdx);
+    }
+
+    Matcher.addAction<DebugCommentAction>(RuleDef->getName());
+    for (Record *ActionDef : RuleDef->getValueAsListOfDefs("Actions")) {
+      if (ActionDef->isSubClassOf("GIBuildMI")) {
+        BuildMIAction &Action = Matcher.addAction<BuildMIAction>(
+            &Target.getInstruction(ActionDef->getValueAsDef("I")),
+            Matcher.insnmatcher_front());
+
+        for (Record *RendererDef : ActionDef->getValueAsListOfDefs("Renderers")) {
+          if (RendererDef->isSubClassOf("GICopyOperand")) {
+            Action.addRenderer<CopyRenderer>(
+                Matcher.insnmatcher_front(),
+                RendererDef->getValueAsString("Name"));
+            continue;
+          }
+
+          if (RendererDef->isSubClassOf("GIAddRegister")) {
+            Action.addRenderer<AddRegisterRenderer>(
+                RendererDef->getValueAsDef("Reg"));
+            continue;
+          }
+
+          if (RendererDef->isSubClassOf("GIAddImm")) {
+            Action.addRenderer<ImmRenderer>(
+                RendererDef->getValueAsInt("Value"));
+            continue;
+          }
+
+          if (RendererDef->isSubClassOf("GIAddComplexOperand")) {
+            std::string Name = RendererDef->getValueAsString("Name");
+
+            SmallVector<OperandPlaceholder, 2> RenderedOperands;
+            const OperandMatcher &OM = Matcher.insnmatcher_front().getOperand(Name);
+            for (unsigned I = 0; I < OM.countTemporaryOperands(); ++I)
+              RenderedOperands.push_back(OperandPlaceholder::CreateTemporary(
+                  OM.getAllocatedTemporariesBaseID() + I));
+
+            Action.addRenderer<RenderComplexPatternOperand>(
+                *RendererDef->getValueAsDef("Matcher"), Name, RenderedOperands);
+            continue;
+          }
+
+          PrintFatalError(RendererDef->getLoc(), "Renderer was not a GIOperandRenderer");
+        }
+
+        continue;
+      }
+
+      PrintFatalError(ActionDef->getLoc(), "Action was not a GIAction");
+    }
+
+    Rules.push_back(std::move(Matcher));
+  }
+
   std::stable_sort(Rules.begin(), Rules.end(),
             [&](const RuleMatcher &A, const RuleMatcher &B) {
               if (A.isHigherPriorityThan(B)) {
                 assert(!B.isHigherPriorityThan(A) && "Cannot be more important "
                                                      "and less important at "
                                                      "the same time");
                 return true;
               }
void GlobalISelEmitter::run(raw_ostream &OS) {
 
   OS << "#ifdef GET_GLOBALISEL_IMPL\n"
      << "bool " << Target.getName()
      << "InstructionSelector::selectImpl(MachineInstr &I) const {\n"
      << "  MachineFunction &MF = *I.getParent()->getParent();\n"
      << "  const MachineRegisterInfo &MRI = MF.getRegInfo();\n";
 
   for (auto &Rule : Rules) {
+    Rule.emitTblgen(OS, 0);
     Rule.emit(OS);
     ++NumPatternEmitted;
   }
 
   OS << "  return false;\n"
      << "}\n"
      << "#endif // ifdef GET_GLOBALISEL_IMPL\n";
 }