[PPC] Eliminate redundant sign- and zero-extensions in PPC MI Peephole pass

[inouehrs]

Summary

This patch enables redundant sign- and zero-extension elimination in PowerPC MI Peephole pass.
If the input value of a sign- or zero-extension is known to be already sign- or zero-extended, the operation is redundant and can be eliminated.
One common case is sign-extensions for a method parameter or for a method return value; they must be sign- or zero-extended as defined in PPC ELF ABI. For example of the following simple code, two extsw instructions are generated before the invocation of int_func and before the return. With this patch, both extsw are eliminated.

void int_func(int);
void ii_test(int a) {
    if (a & 1) return int_func(a);
}

Such redundant sign- or zero-extensions are common in many programs; e.g. I observed about 60,000 occurrences of the elimination while compiling the LLVM+CLANG for PPC.

[inouehrs]

• I added more code patterns in which we can eliminate sign- or zero-extensions.
• I added more test cases in the regression test.

[inouehrs]

• I reverted the recent change in the patch. I will submit it later as a separate patch.

Eric,
Thank you for the advice.

[nemanjai]

Temporarily commandeering this to update it to incorporate changes in https://reviews.llvm.org/D31847.

[nemanjai]

The update simply incorporates the related changes introduced by https://reviews.llvm.org/D31847.

[inouehrs]

This patch resolves PR32442 ( https://bugs.llvm.org/show_bug.cgi?id=32442 )

[echristo]

One question here: Where are the sign and zero extensions coming from? I want to make sure we're not producing extra ones where we could avoid it.

[inouehrs]

commandeered back to update the patch

[inouehrs]

• rebased to the latest tree
• some improvements for wider coverage

[inouehrs]

@echristo For the motivating example in summary, EXTSW is generated while selecting instructions for the method call since ABI requires sign-extended parameters.
For method that returns a value, a sign-/zero-entension is also often (conservatively) generated for the return value to be compliant with ABI.

[echristo]

LGTM.

lib/Target/PowerPC/PPCISelLowering.cpp

if (Flags.isByVal()) {
         if (!isLittleEndian) {
           SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
           Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
         }
         InVals.push_back(Arg);
 
         if (GPR_idx != Num_GPR_Regs) {
           unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
+          FuncInfo->addLiveInAttr(VReg, Flags);
           SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
           SDValue Store;
 
           if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
             EVT ObjType = (ObjSize == 1 ? MVT::i8 :
                            (ObjSize == 2 ? MVT::i16 : MVT::i32));
             Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
                                       MachinePointerInfo(&*FuncArg), ObjType);
if (Flags.isByVal()) {
       InVals.push_back(FIN);
 
       // Store whatever pieces of the object are in registers to memory.
       for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
         if (GPR_idx == Num_GPR_Regs)
           break;
 
         unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
+        FuncInfo->addLiveInAttr(VReg, Flags);
         SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
         SDValue Addr = FIN;
         if (j) {
           SDValue Off = DAG.getConstant(j, dl, PtrVT);
           Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
         }
         SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
                                      MachinePointerInfo(&*FuncArg, j));
case MVT::i64:
         break;
       }
 
       // These can be scalar arguments or elements of an integer array type
       // passed directly.  Clang may use those instead of "byval" aggregate
       // types to avoid forcing arguments to memory unnecessarily.
       if (GPR_idx != Num_GPR_Regs) {
         unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
+        FuncInfo->addLiveInAttr(VReg, Flags);
         ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
 
         if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
           // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
           // value to MVT::i64 and then truncate to the correct register size.
           ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
       } else {
         if (CallConv == CallingConv::Fast)
case MVT::f64:
       } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
         // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
         // once we support fp <-> gpr moves.
 
         // This can only ever happen in the presence of f32 array types,
         // since otherwise we never run out of FPRs before running out
         // of GPRs.
         unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
+        FuncInfo->addLiveInAttr(VReg, Flags);
         ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
 
         if (ObjectVT == MVT::f32) {
           if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
             ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
                                  DAG.getConstant(32, dl, MVT::i32));
           ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
         }

lib/Target/PowerPC/PPCInstrInfo.h

public:
 
   static bool isVFRegister(unsigned Reg) {
     return Reg >= PPC::VF0 && Reg <= PPC::VF31;
   }
   static bool isVRRegister(unsigned Reg) {
     return Reg >= PPC::V0 && Reg <= PPC::V31;
   }
   const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
+
+  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const;
+
+  /// Return true if the output of the instruction is always sign-extended.
+  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
+    return isSignOrZeroExtended(MI, true, depth);
+  }
+
+  /// Return true if the output of the instruction is always zero-extended.
+  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
+   return isSignOrZeroExtended(MI, false, depth);
+  }
 };
 
 }
 
 #endif

lib/Target/PowerPC/PPCInstrInfo.cpp

 }
 
 const TargetRegisterClass *
 PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
   if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
     return &PPC::VSRCRegClass;
   return RC;
 }
+
+static bool
+isSignExtendingOp(const MachineInstr &MI) {
+  int Opcode = MI.getOpcode();
+  if (Opcode == PPC::LI     || Opcode == PPC::LI8     ||
+      Opcode == PPC::LIS    || Opcode == PPC::LIS8    ||
+      Opcode == PPC::SRAW   || Opcode == PPC::SRAWo   ||
+      Opcode == PPC::SRAWI  || Opcode == PPC::SRAWIo  ||
+      Opcode == PPC::LWA    || Opcode == PPC::LWAX    ||
+      Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
+      Opcode == PPC::LHA    || Opcode == PPC::LHAX    ||
+      Opcode == PPC::LHA8   || Opcode == PPC::LHAX8   ||
+      Opcode == PPC::EXTSB  || Opcode == PPC::EXTSBo  ||
+      Opcode == PPC::EXTSH  || Opcode == PPC::EXTSHo  ||
+      Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8  ||
+      Opcode == PPC::EXTSW  || Opcode == PPC::EXTSWo  ||
+      Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
+      Opcode == PPC::EXTSB8_32_64)
+    return true;
+
+  else if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
+    return true;
+
+  else if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
+            Opcode == PPC::RLWNM  || Opcode == PPC::RLWNMo) &&
+           MI.getOperand(3).getImm() > 0 &&
+           MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+    return true;
+
+  return false;
+}
+
+static bool
+isZeroExtendingOp(const MachineInstr &MI) {
+  int Opcode = MI.getOpcode();
+  // The 16-bit immediate is sign-extended in li/lis.
+  // If the most significant bit is zero, all higher bits are zero.
+  if (Opcode == PPC::LI  || Opcode == PPC::LI8 ||
+      Opcode == PPC::LIS || Opcode == PPC::LIS8) {
+    int64_t Imm = MI.getOperand(1).getImm();
+    if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
+      return true;
+  }
+
+  // We have some variations of rotate-and-mask instructions
+  // that clear higher 32-bits
+  else if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
+            Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLo  ||
+            Opcode == PPC::RLDICL_32_64) &&
+           MI.getOperand(3).getImm() >= 32)
+    return true;
+
+  else if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
+           MI.getOperand(3).getImm() >= 32 &&
+           MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
+    return true;
+
+  else if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMo ||
+            Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMo  ||
+            Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
+           MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+    return true;
+
+  else if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWo ||
+           Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWo ||
+           Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
+           Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDo ||
+           Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDo ||
+           Opcode == PPC::POPCNTD ||
+           Opcode == PPC::SLW     || Opcode == PPC::SLWo    ||
+           Opcode == PPC::SRW     || Opcode == PPC::SRWo    ||
+           Opcode == PPC::SLW8    || Opcode == PPC::SRW8    ||
+           Opcode == PPC::SLWI    || Opcode == PPC::SLWIo   ||
+           Opcode == PPC::SRWI    || Opcode == PPC::SRWIo   ||
+           Opcode == PPC::LWZ     || Opcode == PPC::LWZX    ||
+           Opcode == PPC::LHZ     || Opcode == PPC::LHZX    ||
+           Opcode == PPC::LBZ     || Opcode == PPC::LBZX    ||
+           Opcode == PPC::LWZ8    || Opcode == PPC::LWZX8   ||
+           Opcode == PPC::LHZ8    || Opcode == PPC::LHZX8   ||
+           Opcode == PPC::LBZ8    || Opcode == PPC::LBZX8   ||
+           Opcode == PPC::ANDIo   || Opcode == PPC::ANDISo  ||
+           Opcode == PPC::ROTRWI  || Opcode == PPC::ROTRWIo ||
+           Opcode == PPC::EXTLWI  || Opcode == PPC::EXTLWIo)
+    return true;
+
+  return false;
+}
+
+// We limit the max depth to track incoming values of PHIs to avoid exsessive cost.
+const unsigned MAX_PHI_DEPTH = 1;
+
+bool
+PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
+                                   const unsigned PhiDepth) const {
+  const MachineFunction *MF = MI.getParent()->getParent();
+  const MachineRegisterInfo *MRI = &MF->getRegInfo();
+  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
+  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
+
+  switch (MI.getOpcode()) {
+  case PPC::COPY: {
+    unsigned SrcReg = MI.getOperand(1).getReg();
+
+    // In both ELFv1 and v2 ABI, method parameters and the return value
+    // are sign- or zero-extended.
+    if (Subtarget.isSVR4ABI()) {
+      // We check the ZExt/SExt flags for a method parameter.
+      if (MI.getParent()->getBasicBlock() == &MF->getFunction()->getEntryBlock()) {
+        unsigned VReg = MI.getOperand(0).getReg();
+        if (MF->getRegInfo().isLiveIn(VReg))
+          return SignExt?FuncInfo->isLiveInSExt(VReg):FuncInfo->isLiveInZExt(VReg);
+      }
+
+      // For a method return value, we check the ZExt/SExt flags in attribute.
+      // We assume the following code sequence for method call.
+      //   ADJCALLSTACKDOWN 32, %R1<imp-def,dead>, %R1<imp-use>
+      //   BL8_NOP <ga:@func>,...
+      //   ADJCALLSTACKUP 32, 0, %R1<imp-def,dead>, %R1<imp-use>
+      //   %vreg5<def> = COPY %X3; G8RC:%vreg5
+      if (SrcReg == PPC::X3) {
+        const MachineBasicBlock *MBB = MI.getParent();
+        MachineBasicBlock::const_instr_iterator II = MachineBasicBlock::const_instr_iterator(&MI);
+        if (II != MBB->instr_begin() && (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
+          const MachineInstr &CallMI = *(--II);
+          if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
+            const Function *CalleeFn = dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
+            const IntegerType *IntTy = dyn_cast<IntegerType>(CalleeFn->getReturnType());
+            const AttributeList &Attrs = CalleeFn->getAttributes().getRetAttributes();
+            if (IntTy && IntTy->getBitWidth() <= 32)
+              return Attrs.hasAttribute(AttributeList::ReturnIndex,
+                                        SignExt?Attribute::SExt:Attribute::ZExt);
+          }
+        }
+      }
+    }
+
+    // If this is a copy from another register, we recursively check the source.
+    if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+      return false;
+    const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
+    if (SrcMI != NULL)
+      return isSignOrZeroExtended(*SrcMI, SignExt, PhiDepth);
+
+    return false;
+  }
+
+  // If all incoming values are sign- or zero-extended,
+  // the output of the phi is also sign- or zero-extended.
+  case PPC::PHI: {
+    if (PhiDepth >= MAX_PHI_DEPTH)
+      return false;
+
+    for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
+      if (MI.getOperand(i).isReg()) {
+        unsigned SrcReg = MI.getOperand(i).getReg();
+        if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+          return false;
+        const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
+        if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, PhiDepth+1))
+          return false;
+      }
+      else
+        return false;
+    }
+    return true;
+  }
+
+  default:
+    return SignExt?isSignExtendingOp(MI):
+                   isZeroExtendingOp(MI);
+  }
+  return false;
+}

lib/Target/PowerPC/PPCMIPeephole.cpp

 // swap removal.
 //
 //===---------------------------------------------------------------------===//
 
 #include "PPCInstrInfo.h"
 #include "PPC.h"
 #include "PPCInstrBuilder.h"
 #include "PPCTargetMachine.h"
+#include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "ppc-mi-peepholes"
 
+STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions");
+STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions");
+
+static cl::opt<bool>
+    EnableSExtElimination("ppc-eliminate-signext",
+                          cl::desc("enable elimination of sign-extensions"),
+                          cl::init(true), cl::Hidden);
+
+static cl::opt<bool>
+    EnableZExtElimination("ppc-eliminate-zeroext",
+                          cl::desc("enable elimination of zero-extensions"),
+                          cl::init(true), cl::Hidden);
+
 namespace llvm {
   void initializePPCMIPeepholePass(PassRegistry&);
 }
 
 namespace {
 
 struct PPCMIPeephole : public MachineFunctionPass {
 
for (MachineInstr &MI : MBB) {
             removeFRSPIfPossible(P1);
             removeFRSPIfPossible(P2);
             break;
           }
           removeFRSPIfPossible(P1);
         }
         break;
       }
+
+      case PPC::EXTSW_32_64: {
+        // We can eliminate EXTSW if the input is known to be already sign-extended.
+        // expected input code sequence:
+        //   %vreg3<def> = EXTSW_32_64 %vreg1; G8RC:%vreg3 GPRC:%vreg1
+        // expected transformed code sequence:
+        //   %vreg5<def> = IMPLICIT_DEF; G8RC:%vreg5 # TmpReg
+        //   %vreg3<def,tied1> = INSERT_SUBREG %vreg5<tied0>, %vreg1, sub_32; G8RC:%vreg3,%vreg5 GPRC:%vreg1
+        if (!EnableSExtElimination) break;
+
+        unsigned SrcReg = MI.getOperand(1).getReg();
+        if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+          break;
+        MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
+
+        if (SrcMI && TII->isSignExtended(*SrcMI)) {
+          DEBUG(dbgs() << "Removing redundant sign-extension\n");
+          unsigned TmpReg = MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
+          BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), TmpReg);
+          BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
+                  MI.getOperand(0).getReg())
+              .addReg(TmpReg)
+              .addReg(SrcReg)
+              .addImm(PPC::sub_32);
+          ToErase = &MI;
+          Simplified = true;
+          NumEliminatedSExt++;
+        }
+        break;
+      }
+
+      case PPC::RLDICL: {
+        // We can eliminate RLDICL for zero-extension
+        // if the input is known to be already zero-extended.
+        // exptected input pattern for zero extension for %vreg1:
+        //   %vreg4<def> = IMPLICIT_DEF; G8RC:%vreg4
+        //   %vreg3<def,tied1> = INSERT_SUBREG %vreg4<tied0>, %vreg1, sub_32; G8RC:%vreg3,%vreg4 GPRC:%vreg1
+        //   %vreg5<def> = RLDICL %vreg3<kill>, 0, 32; G8RC:%vreg5,%vreg3
+        if (!EnableZExtElimination) break;
+        if (MI.getOperand(2).getImm() != 0 ||
+            MI.getOperand(3).getImm() > 32)
+          break;
+        unsigned SrcReg = MI.getOperand(1).getReg();
+        if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+          break;
+        MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
+
+        if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG &&
+              SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
+          break;
+
+        MachineInstr *ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
+        MachineInstr *SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg());
+        if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break;
+
+        if (TII->isZeroExtended(*SubRegMI)) {
+          DEBUG(dbgs() << "Removing redundant zero-extension\n");
+          BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
+                  MI.getOperand(0).getReg())
+              .addReg(SrcReg);
+          ToErase = &MI;
+          Simplified = true;
+          NumEliminatedZExt++;
+        }
+        break;
+      }
       }
     }
     // If the last instruction was marked for elimination,
     // remove it now.
     if (ToErase) {
       ToErase->eraseFromParent();
       ToErase = nullptr;
     }

lib/Target/PowerPC/PPCMachineFunctionInfo.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
 #define LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
 
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/Target/TargetCallingConv.h"
 
 namespace llvm {
 
 /// PPCFunctionInfo - This class is derived from MachineFunction private
 /// PowerPC target-specific information for each MachineFunction.
 class PPCFunctionInfo : public MachineFunctionInfo {
   virtual void anchor();
 
class PPCFunctionInfo : public MachineFunctionInfo {
 
   /// Whether this uses the PIC Base register or not.
   bool UsesPICBase = false;
 
   /// True if this function has a subset of CSRs that is handled explicitly via
   /// copies
   bool IsSplitCSR = false;
 
+  /// We keep track attributes for each live-in virtual registers
+  /// to use SExt/ZExt flags in later optimization.
+  std::vector<std::pair<unsigned, ISD::ArgFlagsTy>> LiveInAttrs;
+
 public:
   explicit PPCFunctionInfo(MachineFunction &MF) : MF(MF) {}
 
   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
   
   int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; }
   void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; }
public:
   void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; }
 
   unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; }
   void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; }
 
   unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; }
   void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; }
 
+  /// This function associates attributes for each live-in virtual register.
+  void addLiveInAttr(unsigned VReg, ISD::ArgFlagsTy Flags) {
+    LiveInAttrs.push_back(std::make_pair(VReg, Flags));
+  }
+
+  /// This function returns true if the spesified vreg is
+  /// a live-in register and sign-extended.
+  bool isLiveInSExt(unsigned VReg) const;
+
+  /// This function returns true if the spesified vreg is
+  /// a live-in register and zero-extended.
+  bool isLiveInZExt(unsigned VReg) const;
+
   int getCRSpillFrameIndex() const { return CRSpillFrameIndex; }
   void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; }
 
   const SmallVectorImpl<unsigned> &
     getMustSaveCRs() const { return MustSaveCRs; }
   void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); }
 
   void setUsesPICBase(bool uses) { UsesPICBase = uses; }

lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

 }
 
 MCSymbol *PPCFunctionInfo::getTOCOffsetSymbol() const {
   const DataLayout &DL = MF.getDataLayout();
   return MF.getContext().getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
                                            "func_toc" +
                                            Twine(MF.getFunctionNumber()));
 }
+
+bool PPCFunctionInfo::isLiveInSExt(unsigned VReg) const {
+  for (const std::pair<unsigned, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
+    if (LiveIn.first == VReg)
+      return LiveIn.second.isSExt();
+  return false;
+}
+
+bool PPCFunctionInfo::isLiveInZExt(unsigned VReg) const {
+  for (const std::pair<unsigned, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
+    if (LiveIn.first == VReg)
+      return LiveIn.second.isZExt();
+  return false;
+}

test/CodeGen/PowerPC/eliminate_ext.ll

+; RUN: llc -verify-machineinstrs -O1 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -O1 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+
+define signext i32 @sext_test(i32 signext %a) {
+; We can eliminate extsw before and after the call for int_func.
+; CHECK-LABEL: sext_test:
+; CHECK-NOT: extsw
+; CHECK: bl int_func
+; CHECK-NOT: extsw
+entry:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %call = tail call signext i32 @int_func(i32 signext %a)
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %call, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define signext i32 @sext_test2(i32 signext %a) {
+; We can eliminate extsw before the call for long_func.
+; We should not eliminate extsw after the call.
+; CHECK-LABEL: sext_test2:
+; CHECK-NOT: extsw
+; CHECK: bl long_func
+; CHECK: extsw
+entry:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %conv = sext i32 %a to i64
+  %call = tail call i64 @long_func(i64 %conv)
+  %conv1 = trunc i64 %call to i32
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %conv1, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define zeroext i32 @zext_test(i32 zeroext %a) {
+; We can eliminate zero-extension before and after the call for uint_func.
+; CHECK-LABEL: zext_test:
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+; CHECK: bl uint_func
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+entry:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %call = tail call zeroext i32 @uint_func(i32 zeroext %a)
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %call, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define zeroext i32 @zext_test2(i32 zeroext %a) {
+; We can eliminate zero-extension before the call for ulong_func.
+; CHECK-LABEL: zext_test2:
+; CHECK-NOT: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+; CHECK: bl ulong_func
+; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
+entry:
+  %and = and i32 %a, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %return, label %if.then
+
+if.then:
+  %conv = zext i32 %a to i64
+  %call = tail call i64 @ulong_func(i64 %conv)
+  %conv1 = trunc i64 %call to i32
+  br label %return
+
+return:
+  %retval.0 = phi i32 [ %conv1, %if.then ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+declare signext i32 @int_func(i32 signext)
+declare zeroext i32 @uint_func(i32 zeroext)
+declare i64 @long_func(i64)
+declare i64 @ulong_func(i64)