[PowerPC] Eliminate compares - add i32 sext/zext handling

[nemanjai]

Summary

This revision adds the functionality and testing for sign/zero extending i32 comparisons.

[nemanjai]

Temporarily commandeering this patch to update it with a more reasonable split of the original patch.

[nemanjai]

This is being split into smaller patches. Abandoning the large patch.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 #include <new>
 #include <tuple>
 #include <utility>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "ppc-codegen"
 
+STATISTIC(NumSextSetcc,
+          "Number of (sext(setcc)) nodes expanded into GPR sequence.");
+STATISTIC(NumZextSetcc,
+          "Number of (zext(setcc)) nodes expanded into GPR sequence.");
 STATISTIC(SignExtensionsAdded,
           "Number of sign extensions for compare inputs added.");
 STATISTIC(ZeroExtensionsAdded,
           "Number of zero extensions for compare inputs added.");
 // FIXME: Remove this once the bug has been fixed!
 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
 

 bool PPCDAGToDAGISel::trySELECT(SDNode *N) {
   return false;
 }
 
 /// If this node is a sign/zero extension of an integer comparison,
 /// it can usually be computed in GPR's rather than using comparison
 /// instructions and ISEL.
 bool PPCDAGToDAGISel::tryEXTEND(SDNode *N) {
+  if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
     return false;
+  assert((N->getOpcode() == ISD::ZERO_EXTEND ||
+          N->getOpcode() == ISD::SIGN_EXTEND) &&
+          "Expecting a zero/sign extend node!");
+  if (N->getOperand(0).getOpcode() != ISD::SETCC)
+    return false;
+
+  SDLoc dl(N);
+  SDValue WideRes = getSETCCInGPR(N->getOperand(0),
+                                  N->getOpcode() == ISD::SIGN_EXTEND);
+
+  bool Inputs32Bit = N->getOperand(0).getOperand(0).getValueType() == MVT::i32;
+  bool Output32Bit = N->getValueType(0) == MVT::i32;
+  if (!WideRes)
+    return false;
+
+  if (N->getOpcode() == ISD::SIGN_EXTEND)
+    NumSextSetcc++;
+  else
+    NumZextSetcc++;
+
+  SDValue ConvOp = addExtOrTrunc(WideRes, Inputs32Bit, Output32Bit);
+  ReplaceNode(N, ConvOp.getNode());
+
+  return true;
 }
 
 // Is this a comparison operator (i.e. returns 0 if the values are equal,
 // -1 if the first value is less and 1 if the first value is greater)?
 static bool isComparisonOp(SDNode *N) {
   return false;
 }
 
ConvOp = SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32,
                                             NatWidthRes, SubRegIdx), 0);
   }
   return ConvOp;
 }
 
 // Produces a sign/zero extended result of comparing whether a 32-bit value is
 // greater than or equal to zero.
 SDValue PPCDAGToDAGISel::getSETGE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext) {
-  return SDValue();
+  SDValue Not =
+    SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, LHS, LHS), 0);
+  if (IsSext)
+    return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, Not,
+                                          getI32Imm(31, dl)), 0);
+  SDValue ShiftOps[] =
+    { Not, getI32Imm(1, dl), getI32Imm(31, dl), getI32Imm(31, dl) };
+  return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
+                                        ShiftOps), 0);
 }
 
 // Produces a sign/zero extended result of comparing whether a 64-bit value is
 // greater than or equal to zero.
 SDValue PPCDAGToDAGISel::getSETGE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext) {
   return SDValue();
 }
 
 // Produces a sign/zero extended result of comparing whether a 32-bit value is
 // less than or equal to zero.
 SDValue PPCDAGToDAGISel::getSETLE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext) {
-  return SDValue();
+  SDValue Neg =
+    SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
+  SDValue Srdi =
+    SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
+                                   Neg, getI64Imm(1, dl),
+                                   getI64Imm(63, dl)), 0);
+  if (IsSext)
+    return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
+                                          getI32Imm(-1, dl)), 0);
+  return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Srdi,
+                 getI32Imm(1, dl)), 0);
 }
 
 // Produces a sign/zero extended result of comparing whether a 64-bit value is
 // less than or equal to zero.
 SDValue PPCDAGToDAGISel::getSETLE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext) {
   return SDValue();
 }
 
 static void swapAndReset(SDValue &LHS, SDValue &RHS, bool &IsRHSZero,
                          bool &IsRHSOne, bool &IsRHSNegOne) {
   std::swap(LHS, RHS);
   ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
   IsRHSZero = RHSConst && RHSConst->isNullValue();
   IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
   IsRHSNegOne = RHSConst && RHSConst->isAllOnesValue();
 }
 
 /// Produces a zero-extended result of comparing two 32-bit values according to
 /// the passed condition code.
 SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
                                              ISD::CondCode CC,
                                              int64_t RHSValue, SDLoc dl) {
-  return SDValue();
+  bool IsRHSZero = RHSValue == 0;
+  bool IsRHSOne = RHSValue == 1;
+  bool IsRHSNegOne = RHSValue == -1LL;
+  switch (CC) {
+  default: llvm_unreachable("Unknown condition!");
+  case ISD::SETEQ: {
+    SDValue Xor = IsRHSZero ? LHS :
+      SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
+    SDValue Clz =
+      SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
+    SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
+      getI32Imm(31, dl) };
+    return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
+                                          ShiftOps), 0);
+  }
+  case ISD::SETNE: {
+    SDValue Xor = IsRHSZero ? LHS :
+      SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
+    SDValue Clz =
+      SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
+    SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
+      getI32Imm(31, dl) };
+    SDValue Shift =
+      SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
+                                          getI32Imm(1, dl)), 0);
+  }
+  case ISD::SETGE: {
+    if(IsRHSZero)
+      return getSETGE0I32InGPR(LHS, dl, false);
+    swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
+    LLVM_FALLTHROUGH;
+  }
+  case ISD::SETLE: {
+    SDValue SubOrNeg = IsRHSZero ?
+      SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0) :
+      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
+    SDValue Shift =
+      SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, SubOrNeg,
+                                     getI64Imm(1, dl), getI64Imm(63, dl)), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,
+                   MVT::i32, Shift, getI32Imm(1, dl)), 0);
+  }
+  case ISD::SETGT: {
+    if (IsRHSNegOne)
+      return getSETGE0I32InGPR(LHS, dl, false);
+    if (IsRHSZero) {
+      SDValue Neg =
+        SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
+      return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
+                     Neg, getI32Imm(1, dl), getI32Imm(63, dl)), 0);
+    }
+    swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
+    LLVM_FALLTHROUGH;
+  }
+  case ISD::SETLT: {
+    // Handle SETLT 1 (which is equivalent to SETLE 0)
+    if (IsRHSOne)
+      return getSETLE0I32InGPR(LHS, dl, false);
+    if (IsRHSZero) {
+      SDValue ShiftOps[] = { LHS, getI32Imm(1, dl), getI32Imm(31, dl),
+                                  getI32Imm(31, dl) };
+      return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
+                                            ShiftOps), 0);
+    }
+    SDValue SUBFNode =
+      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
+                                    SUBFNode, getI64Imm(1, dl),
+                                    getI64Imm(63, dl)), 0);
+  }
+  case ISD::SETUGE:
+    swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
+    LLVM_FALLTHROUGH;
+  case ISD::SETULE: {
+    SDValue Subtract =
+      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
+    SDValue SrdiNode =
+      SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
+                                          Subtract, getI64Imm(1, dl),
+                                          getI64Imm(63, dl)), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, SrdiNode,
+                                            getI32Imm(1, dl)), 0);
+  }
+  case ISD::SETUGT:
+    swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
+    LLVM_FALLTHROUGH;
+  case ISD::SETULT: {
+    // FIXME: This is converted upstream to a shift/subtract sequence that
+    //  does excessive zero extension/truncation for i8 and i16.
+    SDValue Subtract =
+      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
+                                          Subtract, getI64Imm(1, dl),
+                                          getI64Imm(63, dl)), 0);
+  }
+  }
 }
 
 /// Produces a sign-extended result of comparing two 32-bit values according to
 /// the passed condition code.
 SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
                                              ISD::CondCode CC,
                                              int64_t RHSValue, SDLoc dl) {
-  return SDValue();
+  bool IsRHSZero = RHSValue == 0;
+  bool IsRHSOne = RHSValue == 1;
+  bool IsRHSNegOne = RHSValue == -1LL;
+  switch (CC) {
+  default: llvm_unreachable("Unknown condition!");
+  case ISD::SETEQ: {
+    SDValue CountInput = IsRHSZero ? LHS :
+      SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
+    SDValue Cntlzw =
+      SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
+    SDValue LSHROps[] =
+      { Cntlzw, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) };
+    SDValue Srwi =
+      SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, LSHROps), 0);
+    SDValue SHLOps[] = { Srwi, getI32Imm(63, dl), getI32Imm(0, dl) };
+    SDValue Sldi =
+      SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi,
+                                          getI32Imm(63, dl)), 0);
+  }
+  case ISD::SETNE: {
+    SDValue Xor = IsRHSZero ? LHS :
+      SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
+    SDValue Clz =
+      SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
+    SDValue ShiftOps[] =
+      { Clz, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) };
+    SDValue Shift =
+      SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
+    SDValue Xori =
+      SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
+                                     getI32Imm(1, dl)), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
+  }
+  case ISD::SETGE: {
+    if(IsRHSZero)
+      return getSETGE0I32InGPR(LHS, dl, true);
+    swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
+    LLVM_FALLTHROUGH;
+  }
+  case ISD::SETLE: {
+    if (IsRHSZero)
+      return getSETLE0I32InGPR(LHS, dl, true);
+    SDValue SUBFNode =
+      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,
+                                     LHS, RHS), 0);
+    SDValue Srdi =
+      SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, MVT::Glue,
+                                     SUBFNode, getI64Imm(1, dl),
+                                     getI64Imm(63, dl)), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
+                                          getI32Imm(-1, dl)), 0);
+  }
+  case ISD::SETGT: {
+    if (IsRHSNegOne)
+      return getSETGE0I32InGPR(LHS, dl, true);
+    if (IsRHSZero) {
+      SDValue Neg =
+        SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
+        return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Neg,
+                                              getI64Imm(63, dl)), 0);
+    }
+    swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
+    LLVM_FALLTHROUGH;
+  }
+  case ISD::SETLT: {
+    if (IsRHSOne)
+      return getSETLE0I32InGPR(LHS, dl, true);
+    if (IsRHSZero)
+      return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, LHS,
+                                            getI32Imm(31, dl)), 0);
+    SDValue SUBFNode =
+      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32,
+                                          SUBFNode, getI64Imm(63, dl)), 0);
+  }
+  case ISD::SETUGE:
+    swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
+    LLVM_FALLTHROUGH;
+  case ISD::SETULE: {
+    SDValue Subtract =
+      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
+    SDValue Shift =
+      SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Subtract,
+                                     getI32Imm(1, dl), getI32Imm(63,dl)), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Shift,
+                                          getI32Imm(-1, dl)), 0);
+  }
+  case ISD::SETUGT:
+    swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
+    LLVM_FALLTHROUGH;
+  case ISD::SETULT: {
+    SDValue Subtract =
+      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
+    return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32,
+                                          Subtract, getI64Imm(63, dl)), 0);
+  }
+  }
 }
 
 /// Produces a zero-extended result of comparing two 64-bit values according to
 /// the passed condition code.
 SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
                                              ISD::CondCode CC,
                                              int64_t RHSValue, SDLoc dl) {
   return SDValue();
 }
 
 /// Produces a sign-extended result of comparing two 64-bit values according to
 /// the passed condition code.
 SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
                                              ISD::CondCode CC,
                                              int64_t RHSValue, SDLoc dl) {
   return SDValue();
 }
 
 /// Returns an equivalent of a SETCC node but with the result the same width as
 /// the inputs. This can nalso be used for SELECT_CC if either the true or false
 /// values is a power of two while the other is zero.
 SDValue PPCDAGToDAGISel::getSETCCInGPR(SDValue Compare, bool IsSext,
                                        bool InvertCC) {
+  assert((Compare.getOpcode() == ISD::SETCC ||
+          Compare.getOpcode() == ISD::SELECT_CC) &&
+         "An ISD::SETCC node required here.");
+
+  SDValue LHS = Compare.getOperand(0);
+  SDValue RHS = Compare.getOperand(1);
+  bool IsSelectCC = Compare.getOpcode() == ISD::SELECT_CC;
+  ISD::CondCode CC =
+    cast<CondCodeSDNode>(Compare.getOperand(IsSelectCC ? 4 : 2))->get();
+  EVT InputVT = LHS.getValueType();
+  if (InputVT != MVT::i32 && InputVT != MVT::i64)
     return SDValue();
+
+  SDLoc dl(Compare);
+  ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
+  bool Inputs32Bit = InputVT == MVT::i32;
+  int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
+
+  if (InvertCC)
+    CC = ISD::getSetCCInverse(CC, true);
+  if (ISD::isSignedIntSetCC(CC) && Inputs32Bit) {
+    LHS = signExtendInputIfNeeded(LHS);
+    RHS = signExtendInputIfNeeded(RHS);
+  } else if (ISD::isUnsignedIntSetCC(CC) && Inputs32Bit) {
+    LHS = zeroExtendInputIfNeeded(LHS);
+    RHS = zeroExtendInputIfNeeded(RHS);
+  }
+
+  if (Inputs32Bit && IsSext)
+    return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
+  else if (Inputs32Bit)
+    return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
+  else if (IsSext)
+    return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
+  return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
 }
 
 void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
   // Transfer memoperands.
   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
   MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
   cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
 }

test/CodeGen/PowerPC/setcc-logic.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s
 
 define zeroext i1 @all_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_bits_clear:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    srwi 3, 3, 5
 ; CHECK-NEXT:    blr
   %a = icmp eq i32 %P, 0
   %b = icmp eq i32 %Q, 0
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_clear:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    or 3, 3, 4
+; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    nor 3, 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @all_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_bits_set:
 ; CHECK:       # BB#0:
+; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    li 5, 0
-; CHECK-NEXT:    li 12, 1
-; CHECK-NEXT:    cmpwi 0, 3, -1
-; CHECK-NEXT:    isel 3, 12, 5, 2
+; CHECK-NEXT:    xor 3, 3, 5
+; CHECK-NEXT:    cntlzw 3, 3
+; CHECK-NEXT:    srwi 3, 3, 5
 ; CHECK-NEXT:    blr
   %a = icmp eq i32 %P, -1
   %b = icmp eq i32 %Q, -1
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_set:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %a = icmp slt i32 %P, 0
   %b = icmp slt i32 %Q, 0
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_bits_set:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    nor 3, 3, 3
-; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    srwi 3, 3, 5
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %a = icmp ne i32 %P, 0
   %b = icmp ne i32 %Q, 0
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_set:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    or 3, 3, 4
+; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %a = icmp slt i32 %P, 0
   %b = icmp slt i32 %Q, 0
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_bits_clear:
 ; CHECK:       # BB#0:
+; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    li 5, 1
-; CHECK-NEXT:    cmpwi 0, 3, -1
-; CHECK-NEXT:    isel 3, 0, 5, 2
+; CHECK-NEXT:    xor 3, 3, 5
+; CHECK-NEXT:    cntlzw 3, 3
+; CHECK-NEXT:    srwi 3, 3, 5
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %a = icmp ne i32 %P, -1
   %b = icmp ne i32 %Q, -1
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_clear:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    nor 3, 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
   %c = or i1 %a, %b
   ret i1 %c
 }

 }
 
 define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
 ; CHECK-LABEL: ne_neg1_and_ne_zero:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    li 12, 1
-; CHECK-NEXT:    cmpldi 3, 1
+; CHECK-NEXT:    cmpldi   3, 1
 ; CHECK-NEXT:    isel 3, 12, 4, 1
 ; CHECK-NEXT:    blr
   %cmp1 = icmp ne i64 %x, -1
   %cmp2 = icmp ne i64 %x, 0
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 ; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
 
 define zeroext i1 @and_eq(i16 zeroext  %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
 ; CHECK-LABEL: and_eq:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    xor 5, 5, 6
 ; CHECK-NEXT:    xor 3, 3, 4
 ; CHECK-NEXT:    or 3, 3, 5
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    srwi 3, 3, 5
 ; CHECK-NEXT:    blr
   %cmp1 = icmp eq i16 %a, %b
   %cmp2 = icmp eq i16 %c, %d
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {
 ; CHECK-LABEL: or_ne:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    xor 5, 5, 6
 ; CHECK-NEXT:    xor 3, 3, 4
 ; CHECK-NEXT:    or 3, 3, 5
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    nor 3, 3, 3
-; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    srwi 3, 3, 5
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %cmp1 = icmp ne i32 %a, %b
   %cmp2 = icmp ne i32 %c, %d
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 ; This should not be transformed because vector compares + bitwise logic are faster.

test/CodeGen/PowerPC/testComparesi32gtu.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+%struct.tree_common = type { i8, [3 x i8] }
+declare signext i32 @fn2(...) local_unnamed_addr #1
+
+; Function Attrs: nounwind
+define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
+; CHECK-LABEL: testCompare1:
+; CHECK:       # BB#0: # %entry
+; CHECK:         lbz r3, 0(r3)
+; CHECK-DAG:     clrlwi r3, r3, 31
+; CHECK-DAG:     clrldi r3, r3, 32
+; CHECK:         lbz  r4, 0(r4)
+; CHECK-DAG:     clrlwi r4, r4, 31
+; CHECK-DAG:     clrldi r4, r4, 32
+; CHECK:         subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+entry:
+  %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
+  %bf.clear = and i8 %bf.load, 1
+  %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
+  %bf.load1 = load i8, i8* %0, align 4
+  %bf.clear2 = and i8 %bf.load1, 1
+  %cmp = icmp ugt i8 %bf.clear, %bf.clear2
+  %conv = zext i1 %cmp to i32
+  %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
+  ret i32 undef
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: testCompare2:
+; CHECK:       # BB#0: # %entry
+; CHECK-DAG:     rlwinm r3, r3, 0, 31, 31
+; CHECK-DAG:     rlwinm r4, r4, 0, 31, 31
+; CHECK-DAG:     clrldi r3, r3, 32
+; CHECK-DAG:     clrldi r4, r4, 32
+; CHECK:         subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %and = and i32 %a, 1
+  %and1 = and i32 %b, 1
+  %cmp = icmp ugt i32 %and, %and1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}

test/CodeGen/PowerPC/testComparesi32leu.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rlwinm r3, r3, 0, 31, 31
+; CHECK-NEXT:    rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = and i8 %a, 1
+  %1 = and i8 %b, 1
+  %cmp = icmp ule i8 %0, %1
+  %conv3 = zext i1 %cmp to i32
+  ret i32 %conv3
+}

test/CodeGen/PowerPC/testComparesi32ltu.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+%struct.tree_common = type { i8, [3 x i8] }
+declare signext i32 @fn2(...) local_unnamed_addr #1
+
+; Function Attrs: nounwind
+define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
+; CHECK-LABEL: testCompare1:
+; CHECK:       # BB#0: # %entry
+; CHECK:         lbz r3, 0(r3)
+; CHECK-DAG:     clrlwi r3, r3, 31
+; CHECK-DAG:     clrldi r3, r3, 32
+; CHECK:         lbz  r4, 0(r4)
+; CHECK-DAG:     clrlwi r4, r4, 31
+; CHECK-DAG:     clrldi r4, r4, 32
+; CHECK:         subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+entry:
+  %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
+  %bf.clear = and i8 %bf.load, 1
+  %0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
+  %bf.load1 = load i8, i8* %0, align 4
+  %bf.clear2 = and i8 %bf.load1, 1
+  %cmp = icmp ult i8 %bf.clear, %bf.clear2
+  %conv = zext i1 %cmp to i32
+  %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
+  ret i32 undef
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: testCompare2:
+; CHECK:       # BB#0: # %entry
+; CHECK-DAG:     rlwinm r3, r3, 0, 31, 31
+; CHECK-DAG:     rlwinm r4, r4, 0, 31, 31
+; CHECK-DAG:     clrldi r3, r3, 32
+; CHECK-DAG:     clrldi r4, r4, 32
+; CHECK:         subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %and = and i32 %a, 1
+  %and1 = and i32 %b, 1
+  %cmp = icmp ult i32 %and, %and1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}

test/CodeGen/PowerPC/testComparesieqsc.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesieqsc.c'
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ieqsc:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ieqsc_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsc_z(i8 signext %a) {
+; CHECK-LABEL: test_ieqsc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_ieqsc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ieqsc_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ieqsc_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_ieqsc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_ieqsc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesieqsi.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesieqsi.c'
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ieqsi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ieqsi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsi_z(i32 signext %a) {
+; CHECK-LABEL: test_ieqsi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_ieqsi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ieqsi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ieqsi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_ieqsi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_ieqsi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesieqss.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesieqss.c'
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_ieqss:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_ieqss_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqss_z(i16 signext %a) {
+; CHECK-LABEL: test_ieqss_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ieqss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_ieqss_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_ieqss_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_ieqss_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_ieqss_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ieqss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_ieqss_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesiequc.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesiequc.c'
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iequc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iequc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_iequc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_iequc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iequc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iequc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_iequc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_iequc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesiequi.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesiequi.c'
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iequi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iequi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequi_z(i32 zeroext %a) {
+; CHECK-LABEL: test_iequi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequi_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_iequi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iequi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iequi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequi_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_iequi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequi_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_iequi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesiequs.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testComparesiequs.c'
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iequs:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iequs_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequs_z(i16 zeroext %a) {
+; CHECK-LABEL: test_iequs_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_iequs_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iequs_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iequs_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequs_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_iequs_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iequs_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_iequs_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesigesc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igesc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igesc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_igesc_z(i8 signext %a) {
+; CHECK-LABEL: test_igesc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_igesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_igesc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_igesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igesc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igesc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_igesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igesc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rlwinm r3, r3, 25, 31, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_igesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igesc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 7
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesigesi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igesi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igesi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_igesi_z(i32 signext %a) {
+; CHECK-LABEL: test_igesi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_igesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_igesi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_igesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igesi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igesi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_igesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igesi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_igesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igesi_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesigess.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igess:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igess_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_igess_z(i16 signext %a) {
+; CHECK-LABEL: test_igess_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_igess_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_igess_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_igess_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igess_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igess_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_igess_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igess_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rlwinm r3, r3, 17, 31, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_igess_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igess_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 15
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesigeuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: test_igeuc:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeuc_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr  
+  
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeuc_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: @test_igeuc_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr  
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv2 = sext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: @test_igeuc_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK_LABEL: test_igeuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-TBD-LABEL: @test_igeuc_sext_store
+; CHECK-TBD: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-TBD: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-TBD: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-TBD: stb  [[REG3]]
+; CHECK-TBD: blr    
+}
+
+; Function Attrs : norecurse nounwind
+define void @test_igeuc_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_igeuc_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: stb [[REG1]]
+; CHECK: blr    
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeuc_sext_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_igeuc_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], 255
+; CHECK: stb [[REG1]]
+; CHECK: blr
+}

test/CodeGen/PowerPC/testComparesigeui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+; CHECK-LABEL: test_igeui:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeui_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr    
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeui_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %sub = zext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeui_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeui_sext_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeui_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob
+  ret void
+; CHECK_LABEL: test_igeuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_igeui_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stw  [[REG3]]
+; CHECK: blr    
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeui_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  store i32 %conv1, i32* @glob
+  ret void
+; CHECK-LABEL: @test_igeui_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: stw [[REG1]]
+; CHECK: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeui_sext_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0 
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @glob
+  ret void
+; CHECK-LABEL: @test_igeui_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
+; CHECK: blr  
+}
+

test/CodeGen/PowerPC/testComparesigeus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: test_igeus:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_igeus_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeus_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: @test_igeus_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igeus_sext_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: @test_igeus_sext_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK_LABEL: test_igeus_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_igeus_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: sth  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeus_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_igeus_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: sth [[REG1]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igeus_sext_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_igeus_sext_z_store
+; CHECK: lis [[REG1:r[0-9]+]], 0
+; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
+; CHECK: sth [[REG2]]
+; CHECK: blr
+}
+

test/CodeGen/PowerPC/testComparesigtsc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_z(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_sext_z:
+; CHECK: neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_sext_z_store:
+; CHECK:       neg [[REG2:r[0-9]+]], r3
+; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesigtsi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_z(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_sext_z:
+; CHECK:  neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesigtss.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_z(i16 signext %a) {
+; CHECK-LABEL: test_igtss_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_igtss_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK:    neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT:    sradi r3, [[REG2]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igtss_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igtss_sext_z_store:
+; CHECK:       neg [[REG2:r[0-9]+]], r3
+; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesigtuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc:
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igtuc_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_igtuc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesigtui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui:
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igtui_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_igtui_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+

test/CodeGen/PowerPC/testComparesigtus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus:
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK:         blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igtus_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK:         blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_igtus_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+

test/CodeGen/PowerPC/testComparesilesc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ilesc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ilesc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ilesc_z(i8 signext %a) {
+; CHECK-LABEL: test_ilesc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_ilesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_ilesc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ilesc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_ilesc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ilesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_ilesc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ilesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_ilesc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesilesi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ilesi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ilesi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ilesi_z(i32 signext %a) {
+; CHECK-LABEL: test_ilesi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ilesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_ilesi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ilesi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_ilesi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ilesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_ilesi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ilesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_ilesi_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesiless.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iless:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iless_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_iless_z(i16 signext %a) {
+; CHECK-LABEL: test_iless_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_iless_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_iless_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_iless_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iless_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iless_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iless_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iless_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iless_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iless_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesileuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: test_ileuc:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileuc_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileuc_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+; CHECK-LABEL: test_ileuc_z:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi r3, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileuc_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: test_ileuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_ileuc_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stb  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileuc_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob
+  ret void
+; CHECK-LABEL: test_ileuc_z_store:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileuc_sext_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob
+  ret void
+; CHECK-LABEL: @test_ileuc_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: stb [[REG4]]
+; CHECK: blr
+}
+

test/CodeGen/PowerPC/testComparesileui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = zext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: test_ileui:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileui_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileui_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = zext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: test_ileui_z:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi r3, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileui_sext_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileui_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi r3, [[REG3]], 63
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = zext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: test_ileui_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_ileui_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stw  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileui_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = zext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: test_ileui_z_store:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileui_sext_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_ileui_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: stw [[REG4]]
+; CHECK: blr
+}
+

test/CodeGen/PowerPC/testComparesileus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+; CHECK-LABEL: test_ileus:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileus_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileus_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+; CHECK-LABEL: test_ileus_z:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi r3, [[REG1]], 5
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_ileus_sext_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+; CHECK-LABEL: @test_ileus_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: test_ileus_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_ileus_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: sth  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileus_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob
+  ret void
+; CHECK-LABEL: test_ileus_z_store:
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_ileus_sext_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob
+  ret void
+; CHECK-LABEL: @test_ileus_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: sth [[REG4]]
+; CHECK: blr
+}
+

test/CodeGen/PowerPC/testComparesiltsc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_iltsc_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_iltsc_sext_z_store:
+; CHECK: srwi {{r[0-9]+}}, r3, 7
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesiltsi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_iltsi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_iltsi_sext_z_store:
+; CHECK:    srawi {{r[0-9]+}}, r3, 31
+; CHECK:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesiltss.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_iltss_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iltss_sext_z_store:
+; CHECK:       srwi {{r[0-9]+}}, r3, 15
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i16
+  store i16 %sub, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesiltuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc:
+; CHECK:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_store:
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:    rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_iltuc_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesiltui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui:
+; CHECK:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_store:
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_iltui_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesiltus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus:
+; CHECK:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_store:
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_iltus_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesinesc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_inesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_inesc:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_inesc_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_inesc_z(i8 signext %a) {
+; CHECK-LABEL: test_inesc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_inesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_inesc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_inesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_inesc_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_inesc_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_inesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_inesc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_inesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_inesc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesinesi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_inesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_inesi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_inesi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_inesi_z(i32 signext %a) {
+; CHECK-LABEL: test_inesi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_inesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_inesi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_inesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_inesi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_inesi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_inesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_inesi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_inesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_inesi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesiness.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @test_iness(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iness:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iness_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_iness_z(i16 signext %a) {
+; CHECK-LABEL: test_iness_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_iness_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_iness_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_iness_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iness_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iness_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iness_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iness_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_iness_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iness_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesineuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ineuc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ineuc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ineuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_ineuc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_ineuc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ineuc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ineuc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ineuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_ineuc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_ineuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_ineuc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesineui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ineui:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ineui_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ineui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_ineui_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ineui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_ineui_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ineui_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ineui_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ineui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_ineui_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_ineui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_ineui_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesineus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ineus:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ineus_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ineus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_ineus_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+define signext i32 @test_ineus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_ineus_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ineus_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ineus_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_ineus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_ineus_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_ineus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_ineus_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testCompareslleqsc.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c'
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lleqsc:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lleqsc_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsc_z(i8 signext %a) {
+; CHECK-LABEL: test_lleqsc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_lleqsc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lleqsc_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lleqsc_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_lleqsc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_lleqsc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stb r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testCompareslleqsi.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lleqsi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lleqsi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsi_z(i32 signext %a) {
+; CHECK-LABEL: test_lleqsi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_lleqsi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lleqsi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lleqsi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_lleqsi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3
+; CHECKNEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_lleqsi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testCompareslleqss.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_lleqss:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_lleqss_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqss_z(i16 signext %a) {
+; CHECK-LABEL: test_lleqss_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lleqss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_lleqss_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_lleqss_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_lleqss_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_lleqss_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lleqss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_lleqss_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    sth r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesllequc.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llequc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llequc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llequc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llequc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llequc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llequc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llequc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llequc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesllequi.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llequi:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llequi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequi_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llequi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequi_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llequi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llequi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llequi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequi_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llequi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequi_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llequi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    sldi r3, r3, 63
+; CHECK:    sradi r3, r3, 63
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesllequs.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llequs:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llequs_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequs_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llequs_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llequs_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llequs_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llequs_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llequs_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequs_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llequs_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llequs_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llequs_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sldi r3, r3, 63
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesllgesc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgesc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgesc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgesc_z(i8 signext %a) {
+; CHECK-LABEL: test_llgesc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_llgesc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgesc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgesc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llgesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llgesc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rlwinm r3, r3, 25, 31, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llgesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llgesc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 7
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, -1
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesllgesi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesi_z(i32 signext %a) {
+; CHECK-LABEL: test_llgesi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_llgesi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgesi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llgesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llgesi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llgesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llgesi_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, -1
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesllgess.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_llgess(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgess:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgess_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgess_z(i16 signext %a) {
+; CHECK-LABEL: test_llgess_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srwi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llgess_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_llgess_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @test_llgess_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgess_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgess_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r4, r3
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llgess_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llgess_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rlwinm r3, r3, 17, 31, 31
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llgess_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llgess_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    srwi r3, r3, 15
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesllgeuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: test_llgeuc:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeuc_sext(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: @test_llgeuc_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeuc_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeuc_z
+; CHECK: li r3, 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeuc_sext_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeuc_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK_LABEL: test_llgeuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llgeuc_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stb  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeuc_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv1 = zext i1 %cmp to i8
+  store i8 %conv1, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llgeuc_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: stb [[REG1]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeuc_sext_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp uge i8 %a, 0
+  %conv1 = sext i1 %cmp to i8
+  store i8 %conv1, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llgeuc_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], 255
+; CHECK: stb [[REG1]]
+; CHECK: blr
+}
+

test/CodeGen/PowerPC/testComparesllgeui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: test_llgeui:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeui_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr    
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeui_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeui_z
+; CHECK: li r3, 1
+; CHECK: blr    
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeui_sext_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeui_sext_z
+; CHECK: li r3, -1
+; CHECK-NEXT: blr    
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob
+  ret void
+; CHECK_LABEL: test_igeuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llgeui_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stw  [[REG3]]
+; CHECK: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeui_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %sub = zext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llgeui_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: stw [[REG1]]
+; CHECK: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeui_sext_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp uge i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llgeui_sext_z_store
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
+; CHECK: blr  
+}
+

test/CodeGen/PowerPC/testComparesllgeus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: test_llgeus:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: @test_llgeus_sext
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeus_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeus_z
+; CHECK: li r3, 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgeus_sext_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llgeus_sext_z
+; CHECK: li r3, -1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK_LABEL: test_llgeus_store:
+; CHECK: sub [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llgeus_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: sth  [[REG3]]
+; CHECK: blr    
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeus_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv1 = zext i1 %cmp to i16
+  store i16 %conv1, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llgeus_z_store
+; CHECK: li [[REG1:r[0-9]+]], 1
+; CHECK: sth [[REG1]]
+; CHECK: blr  
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgeus_sext_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp uge i16 %a, 0
+  %conv1 = sext i1 %cmp to i16
+  store i16 %conv1, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llgeus_sext_z_store
+; CHECK: lis [[REG1:r[0-9]+]], 0
+; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
+; CHECK: sth [[REG2]]
+; CHECK: blr  
+}
+

test/CodeGen/PowerPC/testComparesllgtsc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgtsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgtsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsc_z(i8 signext %a) {
+; CHECK-LABEL: test_llgtsc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_llgtsc_sext_z:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgtsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llgtsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_llgtsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llgtsc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llgtsc_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesllgtsi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgtsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgtsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsi_z(i32 signext %a) {
+; CHECK-LABEL: test_llgtsi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_llgtsi_sext_z:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgtsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llgtsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_llgtsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llgtsi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llgtsi_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesllgtss.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgtss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgtss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtss_z(i16 signext %a) {
+; CHECK-LABEL: test_llgtss_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_llgtss_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg [[REG:r[0-9]+]], r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgtss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG1:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llgtss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_llgtss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llgtss_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llgtss_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesllgtuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc:
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgtuc_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llgtuc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesllgtui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui:
+; CHECK-NOT:     clrldi
+; CHECK:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui_sext:
+; CHECK:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui_store:
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgtui_sext_store:
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llgtui_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesllgtus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llgtus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgtus_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llgtus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llgtus_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+

test/CodeGen/PowerPC/testCompareslllesc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lllesc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lllesc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_lllesc_z(i8 signext %a) {
+; CHECK-LABEL: test_lllesc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_lllesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_lllesc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lllesc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_lllesc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_lllesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_lllesc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_lllesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_lllesc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testCompareslllesi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_lllesi(i32 signext %a, i32 signext %b)  {
+; CHECK-LABEL: test_lllesi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b)  {
+; CHECK-LABEL: test_lllesi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_lllesi_z(i32 signext %a)  {
+; CHECK-LABEL: test_lllesi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_lllesi_sext_z(i32 signext %a)  {
+; CHECK-LABEL: test_lllesi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lllesi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_lllesi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_lllesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_lllesi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_lllesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_lllesi_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesllless.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_llless(i16 signext %a, i16 signext %b)  {
+; CHECK-LABEL: test_llless:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llless_sext(i16 signext %a, i16 signext %b)  {
+; CHECK-LABEL: test_llless_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llless_z(i16 signext %a)  {
+; CHECK-LABEL: test_llless_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llless_sext_z(i16 signext %a)  {
+; CHECK-LABEL: test_llless_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llless_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llless_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llless_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subf r3, r3, r4
+; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r12)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llless_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llless_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llless_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llless_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesllleuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: test_llleuc:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleuc_sext(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: @test_llleuc_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleuc_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+; CHECK-LABEL: test_llleuc_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleuc_sext_z(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+; CHECK-LABEL: @test_llleuc_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: test_llleuc_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llleuc_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stb  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleuc_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob
+  ret void
+; CHECK-LABEL: test_llleuc_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi {{r[0-9]}}, r3, 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleuc_sext_z_store(i8 zeroext %a) {
+entry:
+  %cmp = icmp ule i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob
+  ret void
+; CHECK-LABEL: @test_llleuc_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: stb [[REG4]]
+; CHECK: blr
+}

test/CodeGen/PowerPC/testComparesllleui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: test_llleui:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleui_sext(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llleui_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleui_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp ule i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: test_llleui_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleui_sext_z(i32 zeroext %a) {
+entry:
+  %cmp = icmp ule i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+; CHECK-LABEL: @test_llleui_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi r3, [[REG3]], 63
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob
+  ret void
+; CHECK-LABEL: test_llleui_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llleui_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: stw  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleui_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp ule i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob
+  ret void
+; CHECK-LABEL: test_llleui_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleui_sext_z_store(i32 zeroext %a) {
+entry:
+  %cmp = icmp ule i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob
+  ret void
+; CHECK-LABEL: @test_llleui_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: stw [[REG4]]
+; CHECK: blr
+}
+

test/CodeGen/PowerPC/testComparesllleus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: test_llleus:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: xori r3, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleus_sext(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+; CHECK-LABEL: @test_llleus_sext
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleus_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+; CHECK-LABEL: test_llleus_z:
+; CHECK: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llleus_sext_z(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+; CHECK-LABEL: @test_llleus_sext_z
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: test_llleus_store:
+; CHECK: sub [[REG1:r[0-9]+]], r4, r3
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llleus_sext_store
+; CHECK: subf [[REG1:r[0-9]+]], r3, r4
+; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
+; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
+; CHECK: sth  [[REG3]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleus_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob
+  ret void
+; CHECK-LABEL: test_llleus_z_store:
+; CHECK: cntlzw r3, r3
+; CHECK: srwi r3, r3, 5
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llleus_sext_z_store(i16 zeroext %a) {
+entry:
+  %cmp = icmp ule i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob
+  ret void
+; CHECK-LABEL: @test_llleus_sext_z_store
+; CHECK: cntlzw [[REG1:r[0-9]+]], r3
+; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
+; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
+; CHECK: sth [[REG4]]
+; CHECK: blr
+}
+

test/CodeGen/PowerPC/testComparesllltsc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llltsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llltsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_llltsc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llltsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llltsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llltsc_sext_z_store:
+; CHECK:    srwi {{r[0-9]+}}, r3, 7
+; CHECK:    blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesllltsi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llltsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llltsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltsi_sext_z(i32 signext %a)  {
+; CHECK-LABEL: test_llltsi_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llltsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llltsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llltsi_sext_z_store:
+; CHECK:    srawi r3, r3, 31
+; CHECK:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesllltss.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llltss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llltss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_llltss_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llltss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llltss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llltss_sext_z_store:
+; CHECK: srwi r3, r3, 15
+; CHECK: blr
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesllltuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llltuc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesllltui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui:
+; CHECK:       # BB#0: # %entry
+; CHECK-NOT:     clrldi
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rldicl r3, r3, 0, 32
+; CHECK-NEXT:    rldicl r4, r4, 0, 32
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i64 0
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+entry:
+  ret i64 0
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NOT:     clrldi
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llltui_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NOT:     clrldi
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         stw [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i32 0, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llltui_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         li [[REG:r[0-9]+]], 0
+; CHECK:         stw [[REG]], 0(r3)
+; CHECK-NEXT:    blr
+entry:
+  store i32 0, i32* @glob, align 4
+  ret void
+}
+

test/CodeGen/PowerPC/testComparesllltus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    subf [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_store:
+; CHECK:         sub [[REG:r[2-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llltus_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         subf [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesllnesc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define i64 @test_llnesc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llnesc:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llnesc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llnesc_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llnesc_z(i8 signext %a) {
+; CHECK-LABEL: test_llnesc_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llnesc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_llnesc_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llnesc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llnesc_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llnesc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_llnesc_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llnesc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llnesc_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llnesc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_llnesc_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesllnesi.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_llnesi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llnesi:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llnesi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llnesi_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llnesi_z(i32 signext %a) {
+; CHECK-LABEL: test_llnesi_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llnesi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_llnesi_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llnesi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llnesi_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llnesi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_llnesi_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llnesi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llnesi_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llnesi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_llnesi_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesllness.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_llness(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llness:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llness_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llness_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llness_z(i16 signext %a) {
+; CHECK-LABEL: test_llness_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llness_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_llness_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llness_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llness_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llness_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_llness_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llness_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llness_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llness_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_llness_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}

test/CodeGen/PowerPC/testComparesllneuc.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+define i64 @test_llneuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llneuc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llneuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llneuc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llneuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llneuc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llneuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llneuc_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llneuc_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llneuc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llneuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llneuc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llneuc_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llneuc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+define void @test_llneuc_sext_z_store(i8 zeroext %a) {
+; CHECK-LABEL: test_llneuc_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}

test/CodeGen/PowerPC/testComparesllneui.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+define i64 @test_llneui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llneui:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llneui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llneui_sext:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llneui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llneui_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llneui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llneui_sext_z:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llneui_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llneui_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llneui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llneui_sext_store:
+; CHECK:    xor r3, r3, r4
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llneui_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llneui_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+define void @test_llneui_sext_z_store(i32 zeroext %a) {
+; CHECK-LABEL: test_llneui_sext_z_store:
+; CHECK:    cntlzw r3, r3
+; CHECK:    srwi r3, r3, 5
+; CHECK:    xori r3, r3, 1
+; CHECK:    neg r3, r3
+; CHECK:    stw r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}

test/CodeGen/PowerPC/testComparesllneus.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+define i64 @test_llneus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llneus:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llneus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llneus_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define i64 @test_llneus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llneus_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define i64 @test_llneus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llneus_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i64
+  ret i64 %conv2
+}
+
+define void @test_llneus_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llneus_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llneus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llneus_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llneus_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llneus_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+define void @test_llneus_sext_z_store(i16 zeroext %a) {
+; CHECK-LABEL: test_llneus_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}