[PPC] Eliminate redundant sign- and zero-extensions in PPC MI Peephole pass

[inouehrs]

Summary

This patch enables redundant sign- and zero-extension elimination in PowerPC MI Peephole pass.
If the input value of a sign- or zero-extension is known to be already sign- or zero-extended, the operation is redundant and can be eliminated.
One common case is sign-extensions for a method parameter or for a method return value; they must be sign- or zero-extended as defined in PPC ELF ABI. For example of the following simple code, two extsw instructions are generated before the invocation of int_func and before the return. With this patch, both extsw are eliminated.

void int_func(int);
void ii_test(int a) {
    if (a & 1) return int_func(a);
}

Such redundant sign- or zero-extensions are common in many programs; e.g. I observed about 60,000 occurrences of the elimination while compiling the LLVM+CLANG for PPC.

[inouehrs]

• I added more code patterns in which we can eliminate sign- or zero-extensions.
• I added more test cases in the regression test.

[inouehrs]

• I reverted the recent change in the patch. I will submit it later as a separate patch.

Eric,
Thank you for the advice.

[nemanjai]

Temporarily commandeering this to update it to incorporate changes in https://reviews.llvm.org/D31847.

[nemanjai]

The update simply incorporates the related changes introduced by https://reviews.llvm.org/D31847.

[inouehrs]

This patch resolves PR32442 ( https://bugs.llvm.org/show_bug.cgi?id=32442 )

[echristo]

One question here: Where are the sign and zero extensions coming from? I want to make sure we're not producing extra ones where we could avoid it.

[inouehrs]

commandeered back to update the patch

[inouehrs]

• rebased to the latest tree
• some improvements for wider coverage

[inouehrs]

@echristo For the motivating example in summary, EXTSW is generated while selecting instructions for the method call since ABI requires sign-extended parameters.
For method that returns a value, a sign-/zero-entension is also often (conservatively) generated for the return value to be compliant with ABI.

[echristo]

LGTM.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

if (Flags.isByVal()) {
         if (!isLittleEndian) {
           SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
           Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
         }
         InVals.push_back(Arg);
 
         if (GPR_idx != Num_GPR_Regs) {
           unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
+          FuncInfo->addLiveInAttr(VReg, Flags);
           SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
           SDValue Store;
 
           if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
             EVT ObjType = (ObjSize == 1 ? MVT::i8 :
                            (ObjSize == 2 ? MVT::i16 : MVT::i32));
             Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
                                       MachinePointerInfo(&*FuncArg), ObjType);
if (Flags.isByVal()) {
       InVals.push_back(FIN);
 
       // Store whatever pieces of the object are in registers to memory.
       for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
         if (GPR_idx == Num_GPR_Regs)
           break;
 
         unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
+        FuncInfo->addLiveInAttr(VReg, Flags);
         SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
         SDValue Addr = FIN;
         if (j) {
           SDValue Off = DAG.getConstant(j, dl, PtrVT);
           Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
         }
         SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
                                      MachinePointerInfo(&*FuncArg, j));
case MVT::i64:
         break;
       }
 
       // These can be scalar arguments or elements of an integer array type
       // passed directly.  Clang may use those instead of "byval" aggregate
       // types to avoid forcing arguments to memory unnecessarily.
       if (GPR_idx != Num_GPR_Regs) {
         unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
+        FuncInfo->addLiveInAttr(VReg, Flags);
         ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
 
         if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
           // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
           // value to MVT::i64 and then truncate to the correct register size.
           ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
       } else {
         if (CallConv == CallingConv::Fast)
case MVT::f64:
       } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
         // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
         // once we support fp <-> gpr moves.
 
         // This can only ever happen in the presence of f32 array types,
         // since otherwise we never run out of FPRs before running out
         // of GPRs.
         unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
+        FuncInfo->addLiveInAttr(VReg, Flags);
         ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
 
         if (ObjectVT == MVT::f32) {
           if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
             ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
                                  DAG.getConstant(32, dl, MVT::i32));
           ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
         }

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h

public:
   static bool isVFRegister(unsigned Reg) {
     return Reg >= PPC::VF0 && Reg <= PPC::VF31;
   }
   static bool isVRRegister(unsigned Reg) {
     return Reg >= PPC::V0 && Reg <= PPC::V31;
   }
   const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
   static int getRecordFormOpcode(unsigned Opcode);
+
+  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
+                            const unsigned PhiDepth) const;
+
+  /// Return true if the output of the instruction is always a sign-extended,
+  /// i.e. 0 to 31-th bits are same as 32-th bit.
+  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
+    return isSignOrZeroExtended(MI, true, depth);
+  }
+
+  /// Return true if the output of the instruction is always zero-extended,
+  /// i.e. 0 to 31-th bits are all zeros
+  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
+   return isSignOrZeroExtended(MI, false, depth);
+  }
 };
 
 }
 
 #endif

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

 
 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
                                          unsigned &SrcReg, unsigned &DstReg,
                                          unsigned &SubIdx) const {
   switch (MI.getOpcode()) {
   default: return false;
   case PPC::EXTSW:
+  case PPC::EXTSW_32:
   case PPC::EXTSW_32_64:
     SrcReg = MI.getOperand(1).getReg();
     DstReg = MI.getOperand(0).getReg();
     SubIdx = PPC::sub_32;
     return true;
   }
 }
 
PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
   if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
     return &PPC::VSRCRegClass;
   return RC;
 }
 
 int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
   return PPC::getRecordFormOpcode(Opcode);
 }
+
+// This function returns true if the machine instruction
+// always outputs a value by sign-extending a 32 bit value,
+// i.e. 0 to 31-th bits are same as 32-th bit.
+static bool isSignExtendingOp(const MachineInstr &MI) {
+  int Opcode = MI.getOpcode();
+  if (Opcode == PPC::LI     || Opcode == PPC::LI8     ||
+      Opcode == PPC::LIS    || Opcode == PPC::LIS8    ||
+      Opcode == PPC::SRAW   || Opcode == PPC::SRAWo   ||
+      Opcode == PPC::SRAWI  || Opcode == PPC::SRAWIo  ||
+      Opcode == PPC::LWA    || Opcode == PPC::LWAX    ||
+      Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
+      Opcode == PPC::LHA    || Opcode == PPC::LHAX    ||
+      Opcode == PPC::LHA8   || Opcode == PPC::LHAX8   ||
+      Opcode == PPC::LBZ    || Opcode == PPC::LBZX    ||
+      Opcode == PPC::LBZ8   || Opcode == PPC::LBZX8   ||
+      Opcode == PPC::LBZU   || Opcode == PPC::LBZUX   ||
+      Opcode == PPC::LBZU8  || Opcode == PPC::LBZUX8  ||
+      Opcode == PPC::LHZ    || Opcode == PPC::LHZX    ||
+      Opcode == PPC::LHZ8   || Opcode == PPC::LHZX8   ||
+      Opcode == PPC::LHZU   || Opcode == PPC::LHZUX   ||
+      Opcode == PPC::LHZU8  || Opcode == PPC::LHZUX8  ||
+      Opcode == PPC::EXTSB  || Opcode == PPC::EXTSBo  ||
+      Opcode == PPC::EXTSH  || Opcode == PPC::EXTSHo  ||
+      Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8  ||
+      Opcode == PPC::EXTSW  || Opcode == PPC::EXTSWo  ||
+      Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
+      Opcode == PPC::EXTSB8_32_64)
+    return true;
+
+  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
+    return true;
+
+  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
+       Opcode == PPC::RLWNM  || Opcode == PPC::RLWNMo) &&
+      MI.getOperand(3).getImm() > 0 &&
+      MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+    return true;
+
+  return false;
+}
+
+// This function returns true if the machine instruction
+// always outputs zeros in higher 32 bits.
+static bool isZeroExtendingOp(const MachineInstr &MI) {
+  int Opcode = MI.getOpcode();
+  // The 16-bit immediate is sign-extended in li/lis.
+  // If the most significant bit is zero, all higher bits are zero.
+  if (Opcode == PPC::LI  || Opcode == PPC::LI8 ||
+      Opcode == PPC::LIS || Opcode == PPC::LIS8) {
+    int64_t Imm = MI.getOperand(1).getImm();
+    if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
+      return true;
+  }
+
+  // We have some variations of rotate-and-mask instructions
+  // that clear higher 32-bits.
+  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
+       Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLo  ||
+       Opcode == PPC::RLDICL_32_64) &&
+      MI.getOperand(3).getImm() >= 32)
+    return true;
+
+  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
+      MI.getOperand(3).getImm() >= 32 &&
+      MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
+    return true;
+
+  if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMo ||
+       Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMo  ||
+       Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
+      MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
+    return true;
+
+  // There are other instructions that clear higher 32-bits.
+  if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWo ||
+      Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWo ||
+      Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
+      Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDo ||
+      Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDo ||
+      Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
+      Opcode == PPC::SLW     || Opcode == PPC::SLWo    ||
+      Opcode == PPC::SRW     || Opcode == PPC::SRWo    ||
+      Opcode == PPC::SLW8    || Opcode == PPC::SRW8    ||
+      Opcode == PPC::SLWI    || Opcode == PPC::SLWIo   ||
+      Opcode == PPC::SRWI    || Opcode == PPC::SRWIo   ||
+      Opcode == PPC::LWZ     || Opcode == PPC::LWZX    ||
+      Opcode == PPC::LWZU    || Opcode == PPC::LWZUX   ||
+      Opcode == PPC::LWBRX   || Opcode == PPC::LHBRX   ||
+      Opcode == PPC::LHZ     || Opcode == PPC::LHZX    ||
+      Opcode == PPC::LHZU    || Opcode == PPC::LHZUX   ||
+      Opcode == PPC::LBZ     || Opcode == PPC::LBZX    ||
+      Opcode == PPC::LBZU    || Opcode == PPC::LBZUX   ||
+      Opcode == PPC::LWZ8    || Opcode == PPC::LWZX8   ||
+      Opcode == PPC::LWZU8   || Opcode == PPC::LWZUX8  ||
+      Opcode == PPC::LWBRX8  || Opcode == PPC::LHBRX8  ||
+      Opcode == PPC::LHZ8    || Opcode == PPC::LHZX8   ||
+      Opcode == PPC::LHZU8   || Opcode == PPC::LHZUX8  ||
+      Opcode == PPC::LBZ8    || Opcode == PPC::LBZX8   ||
+      Opcode == PPC::LBZU8   || Opcode == PPC::LBZUX8  ||
+      Opcode == PPC::ANDIo   || Opcode == PPC::ANDISo  ||
+      Opcode == PPC::ROTRWI  || Opcode == PPC::ROTRWIo ||
+      Opcode == PPC::EXTLWI  || Opcode == PPC::EXTLWIo ||
+      Opcode == PPC::MFVSRWZ)
+    return true;
+
+  return false;
+}
+
+// We limit the max depth to track incoming values of PHIs or binary ops
+// (e.g. AND) to avoid exsessive cost.
+const unsigned MAX_DEPTH = 1;
+
+bool
+PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
+                                   const unsigned Depth) const {
+  const MachineFunction *MF = MI.getParent()->getParent();
+  const MachineRegisterInfo *MRI = &MF->getRegInfo();
+
+  switch (MI.getOpcode()) {
+  case PPC::COPY: {
+    unsigned SrcReg = MI.getOperand(1).getReg();
+
+    // In both ELFv1 and v2 ABI, method parameters and the return value
+    // are sign- or zero-extended.
+    if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
+      const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
+      // We check the ZExt/SExt flags for a method parameter.
+      if (MI.getParent()->getBasicBlock() ==
+          &MF->getFunction()->getEntryBlock()) {
+        unsigned VReg = MI.getOperand(0).getReg();
+        if (MF->getRegInfo().isLiveIn(VReg))
+          return SignExt ? FuncInfo->isLiveInSExt(VReg) :
+                           FuncInfo->isLiveInZExt(VReg);
+      }
+
+      // For a method return value, we check the ZExt/SExt flags in attribute.
+      // We assume the following code sequence for method call.
+      //   ADJCALLSTACKDOWN 32, %R1<imp-def,dead>, %R1<imp-use>
+      //   BL8_NOP <ga:@func>,...
+      //   ADJCALLSTACKUP 32, 0, %R1<imp-def,dead>, %R1<imp-use>
+      //   %vreg5<def> = COPY %X3; G8RC:%vreg5
+      if (SrcReg == PPC::X3) {
+        const MachineBasicBlock *MBB = MI.getParent();
+        MachineBasicBlock::const_instr_iterator II =
+          MachineBasicBlock::const_instr_iterator(&MI);
+        if (II != MBB->instr_begin() &&
+            (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
+          const MachineInstr &CallMI = *(--II);
+          if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
+            const Function *CalleeFn =
+              dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
+            const IntegerType *IntTy =
+              dyn_cast<IntegerType>(CalleeFn->getReturnType());
+            const AttributeSet &Attrs =
+              CalleeFn->getAttributes().getRetAttributes();
+            if (IntTy && IntTy->getBitWidth() <= 32)
+              return Attrs.hasAttribute(SignExt ? Attribute::SExt :
+                                                  Attribute::ZExt);
+          }
+        }
+      }
+    }
+
+    // If this is a copy from another register, we recursively check source.
+    if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+      return false;
+    const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
+    if (SrcMI != NULL)
+      return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
+
+    return false;
+  }
+
+  case PPC::ANDIo:
+  case PPC::ANDISo:
+  case PPC::ORI:
+  case PPC::ORIS:
+  case PPC::XORI:
+  case PPC::XORIS:
+  case PPC::ANDIo8:
+  case PPC::ANDISo8:
+  case PPC::ORI8:
+  case PPC::ORIS8:
+  case PPC::XORI8:
+  case PPC::XORIS8: {
+    // logical operation with 16-bit immediate does not change the upper bits.
+    // So, we track the operand register as we do for register copy.
+    unsigned SrcReg = MI.getOperand(1).getReg();
+    if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+      return false;
+    const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
+    if (SrcMI != NULL)
+      return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
+
+    return false;
+  }
+
+  // If all incoming values are sign-/zero-extended,
+  // the output of AND, OR, ISEL or PHI is also sign-/zero-extended.
+  case PPC::AND:
+  case PPC::AND8:
+  case PPC::OR:
+  case PPC::OR8:
+  case PPC::ISEL:
+  case PPC::PHI: {
+    if (Depth >= MAX_DEPTH)
+      return false;
+
+    // The input registers for PHI are operand 1, 3, ...
+    // The input registers for others are operand 1 and 2.
+    unsigned E = 3, D = 1;
+    if (MI.getOpcode() == PPC::PHI) {
+      E = MI.getNumOperands();
+      D = 2;
+    }
+
+    for (unsigned I = 1; I != E; I += D) {
+      if (MI.getOperand(I).isReg()) {
+        unsigned SrcReg = MI.getOperand(I).getReg();
+        if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+          return false;
+        const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
+        if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
+          return false;
+      }
+      else
+        return false;
+    }
+    return true;
+  }
+
+  default:
+    return SignExt?isSignExtendingOp(MI):
+                   isZeroExtendingOp(MI);
+  }
+  return false;
+}

llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp

 #include "PPCInstrInfo.h"
 #include "PPCTargetMachine.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/ADT/Statistic.h"
 #include "MCTargetDesc/PPCPredicates.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "ppc-mi-peepholes"
 
+STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions");
+STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions");
 STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI");
 
+static cl::opt<bool>
+    EnableSExtElimination("ppc-eliminate-signext",
+                          cl::desc("enable elimination of sign-extensions"),
+                          cl::init(true), cl::Hidden);
+
+static cl::opt<bool>
+    EnableZExtElimination("ppc-eliminate-zeroext",
+                          cl::desc("enable elimination of zero-extensions"),
+                          cl::init(true), cl::Hidden);
+
 namespace llvm {
   void initializePPCMIPeepholePass(PassRegistry&);
 }
 
 namespace {
 
 struct PPCMIPeephole : public MachineFunctionPass {
 
static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
 
   unsigned Reg = Op->getReg();
   if (!TargetRegisterInfo::isVirtualRegister(Reg))
     return nullptr;
 
   return MRI->getVRegDef(Reg);
 }
 
+// This function returns number of known zero bits in output of MI
+// starting from the most significant bit.
+static unsigned
+getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
+  unsigned Opcode = MI->getOpcode();
+  if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
+      Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLo)
+    return MI->getOperand(3).getImm();
+
+  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
+       MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
+    return MI->getOperand(3).getImm();
+
+  if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMo ||
+       Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMo  ||
+       Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
+       MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
+    return 32 + MI->getOperand(3).getImm();
+
+  if (Opcode == PPC::ANDIo) {
+    uint16_t Imm = MI->getOperand(2).getImm();
+    return 48 + countLeadingZeros(Imm);
+  }
+
+  if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWo ||
+      Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWo ||
+      Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8)
+    // The result ranges from 0 to 32.
+    return 58;
+
+  if (Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDo ||
+      Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDo)
+    // The result ranges from 0 to 64.
+    return 57;
+
+  if (Opcode == PPC::LHZ   || Opcode == PPC::LHZX  ||
+      Opcode == PPC::LHZ8  || Opcode == PPC::LHZX8 ||
+      Opcode == PPC::LHZU  || Opcode == PPC::LHZUX ||
+      Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8)
+    return 48;
+
+  if (Opcode == PPC::LBZ   || Opcode == PPC::LBZX  ||
+      Opcode == PPC::LBZ8  || Opcode == PPC::LBZX8 ||
+      Opcode == PPC::LBZU  || Opcode == PPC::LBZUX ||
+      Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
+    return 56;
+
+  if (TII->isZeroExtended(*MI))
+    return 32;
+
+  return 0;
+}
+
 // Perform peephole optimizations.
 bool PPCMIPeephole::simplifyCode(void) {
   bool Simplified = false;
   MachineInstr* ToErase = nullptr;
 
   for (MachineBasicBlock &MBB : *MF) {
     for (MachineInstr &MI : MBB) {
 
for (MachineInstr &MI : MBB) {
             removeFRSPIfPossible(P1);
             removeFRSPIfPossible(P2);
             break;
           }
           removeFRSPIfPossible(P1);
         }
         break;
       }
+      case PPC::EXTSH:
+      case PPC::EXTSH8:
+      case PPC::EXTSH8_32_64: {
+        if (!EnableSExtElimination) break;
+        unsigned NarrowReg = MI.getOperand(1).getReg();
+        if (!TargetRegisterInfo::isVirtualRegister(NarrowReg))
+          break;
+
+        MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
+        // If we've used a zero-extending load that we will sign-extend,
+        // just do a sign-extending load.
+        if (SrcMI->getOpcode() == PPC::LHZ ||
+            SrcMI->getOpcode() == PPC::LHZX) {
+          if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
+            break;
+          auto is64Bit = [] (unsigned Opcode) {
+            return Opcode == PPC::EXTSH8;
+          };
+          auto isXForm = [] (unsigned Opcode) {
+            return Opcode == PPC::LHZX;
+          };
+          auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
+            if (is64Bit)
+              if (isXForm) return PPC::LHAX8;
+              else         return PPC::LHA8;
+            else
+              if (isXForm) return PPC::LHAX;
+              else         return PPC::LHA;
+          };
+          unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
+                                       isXForm(SrcMI->getOpcode()));
+          DEBUG(dbgs() << "Zero-extending load\n");
+          DEBUG(SrcMI->dump());
+          DEBUG(dbgs() << "and sign-extension\n");
+          DEBUG(MI.dump());
+          DEBUG(dbgs() << "are merged into sign-extending load\n");
+          SrcMI->setDesc(TII->get(Opc));
+          SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
+          ToErase = &MI;
+          Simplified = true;
+          NumEliminatedSExt++;
+        }
+        break;
+      }
+      case PPC::EXTSW:
+      case PPC::EXTSW_32:
+      case PPC::EXTSW_32_64: {
+        if (!EnableSExtElimination) break;
+        unsigned NarrowReg = MI.getOperand(1).getReg();
+        if (!TargetRegisterInfo::isVirtualRegister(NarrowReg))
+          break;
+
+        MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
+        // If we've used a zero-extending load that we will sign-extend,
+        // just do a sign-extending load.
+        if (SrcMI->getOpcode() == PPC::LWZ ||
+            SrcMI->getOpcode() == PPC::LWZX) {
+          if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
+            break;
+          auto is64Bit = [] (unsigned Opcode) {
+            return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64;
+          };
+          auto isXForm = [] (unsigned Opcode) {
+            return Opcode == PPC::LWZX;
+          };
+          auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
+            if (is64Bit)
+              if (isXForm) return PPC::LWAX;
+              else         return PPC::LWA;
+            else
+              if (isXForm) return PPC::LWAX_32;
+              else         return PPC::LWA_32;
+          };
+          unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
+                                       isXForm(SrcMI->getOpcode()));
+          DEBUG(dbgs() << "Zero-extending load\n");
+          DEBUG(SrcMI->dump());
+          DEBUG(dbgs() << "and sign-extension\n");
+          DEBUG(MI.dump());
+          DEBUG(dbgs() << "are merged into sign-extending load\n");
+          SrcMI->setDesc(TII->get(Opc));
+          SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
+          ToErase = &MI;
+          Simplified = true;
+          NumEliminatedSExt++;
+        } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
+                   TII->isSignExtended(*SrcMI)) {
+          // We can eliminate EXTSW if the input is known to be already
+          // sign-extended.
+          DEBUG(dbgs() << "Removing redundant sign-extension\n");
+          unsigned TmpReg =
+            MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
+          BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
+                  TmpReg);
+          BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
+                  MI.getOperand(0).getReg())
+              .addReg(TmpReg)
+              .addReg(NarrowReg)
+              .addImm(PPC::sub_32);
+          ToErase = &MI;
+          Simplified = true;
+          NumEliminatedSExt++;
+        }
+        break;
+      }
+      case PPC::RLDICL: {
+        // We can eliminate RLDICL (e.g. for zero-extension)
+        // if all bits to clear are already zero in the input.
+        // This code assume following code sequence for zero-extension.
+        //   %vreg6<def> = COPY %vreg5:sub_32; (optional)
+        //   %vreg8<def> = IMPLICIT_DEF;
+        //   %vreg7<def,tied1> = INSERT_SUBREG %vreg8<tied0>, %vreg6, sub_32;
+        if (!EnableZExtElimination) break;
+
+        if (MI.getOperand(2).getImm() != 0)
+          break;
+
+        unsigned SrcReg = MI.getOperand(1).getReg();
+        if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+          break;
+
+        MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
+        if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG &&
+              SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
+          break;
+
+        MachineInstr *ImpDefMI, *SubRegMI;
+        ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
+        SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg());
+        if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break;
+
+        SrcMI = SubRegMI;
+        if (SubRegMI->getOpcode() == PPC::COPY) {
+          unsigned CopyReg = SubRegMI->getOperand(1).getReg();
+          if (TargetRegisterInfo::isVirtualRegister(CopyReg))
+            SrcMI = MRI->getVRegDef(CopyReg);
+        }
+
+        unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
+        if (MI.getOperand(3).getImm() <= KnownZeroCount) {
+          DEBUG(dbgs() << "Removing redundant zero-extension\n");
+          BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
+                  MI.getOperand(0).getReg())
+              .addReg(SrcReg);
+          ToErase = &MI;
+          Simplified = true;
+          NumEliminatedZExt++;
+        }
+        break;
+      }
 
       // TODO: Any instruction that has an immediate form fed only by a PHI
       // whose operands are all load immediate can be folded away. We currently
       // do this for ADD instructions, but should expand it to arithmetic and
       // binary instructions with immediate forms in the future.
       case PPC::ADD4:
       case PPC::ADD8: {
         auto isSingleUsePHI = [&](MachineOperand *PhiOp) {

llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
 #define LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
 
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/Target/TargetCallingConv.h"
 
 namespace llvm {
 
 /// PPCFunctionInfo - This class is derived from MachineFunction private
 /// PowerPC target-specific information for each MachineFunction.
 class PPCFunctionInfo : public MachineFunctionInfo {
   virtual void anchor();
 
class PPCFunctionInfo : public MachineFunctionInfo {
 
   /// Whether this uses the PIC Base register or not.
   bool UsesPICBase = false;
 
   /// True if this function has a subset of CSRs that is handled explicitly via
   /// copies
   bool IsSplitCSR = false;
 
+  /// We keep track attributes for each live-in virtual registers
+  /// to use SExt/ZExt flags in later optimization.
+  std::vector<std::pair<unsigned, ISD::ArgFlagsTy>> LiveInAttrs;
+
 public:
   explicit PPCFunctionInfo(MachineFunction &MF) : MF(MF) {}
 
   int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
   void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
   
   int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; }
   void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; }
public:
   void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; }
 
   unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; }
   void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; }
 
   unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; }
   void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; }
 
+  /// This function associates attributes for each live-in virtual register.
+  void addLiveInAttr(unsigned VReg, ISD::ArgFlagsTy Flags) {
+    LiveInAttrs.push_back(std::make_pair(VReg, Flags));
+  }
+
+  /// This function returns true if the spesified vreg is
+  /// a live-in register and sign-extended.
+  bool isLiveInSExt(unsigned VReg) const;
+
+  /// This function returns true if the spesified vreg is
+  /// a live-in register and zero-extended.
+  bool isLiveInZExt(unsigned VReg) const;
+
   int getCRSpillFrameIndex() const { return CRSpillFrameIndex; }
   void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; }
 
   const SmallVectorImpl<unsigned> &
     getMustSaveCRs() const { return MustSaveCRs; }
   void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); }
 
   void setUsesPICBase(bool uses) { UsesPICBase = uses; }

llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

 }
 
 MCSymbol *PPCFunctionInfo::getTOCOffsetSymbol() const {
   const DataLayout &DL = MF.getDataLayout();
   return MF.getContext().getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
                                            "func_toc" +
                                            Twine(MF.getFunctionNumber()));
 }
+
+bool PPCFunctionInfo::isLiveInSExt(unsigned VReg) const {
+  for (const std::pair<unsigned, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
+    if (LiveIn.first == VReg)
+      return LiveIn.second.isSExt();
+  return false;
+}
+
+bool PPCFunctionInfo::isLiveInZExt(unsigned VReg) const {
+  for (const std::pair<unsigned, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
+    if (LiveIn.first == VReg)
+      return LiveIn.second.isZExt();
+  return false;
+}

llvm/trunk/test/CodeGen/PowerPC/expand-isel.ll

 
 cleanup:
   %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ]
   ret i32 %retval.0
 
 ; CHECK-LABEL: @testComplexISEL
 ; CHECK-DAG: [[LI:r[0-9]+]], 1
 ; CHECK-DAG: cmplwi [[LD:r[0-9]+]], 0
-; CHECK: beq cr0, [[EQ:.LBB[0-9_]+]]
-; CHECK: blr
-; CHECK: [[EQ]]
+; CHECK: bnelr cr0
 ; CHECK: xor [[XOR:r[0-9]+]]
 ; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
 ; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
 }
 
 !1 = !{!2, !2, i64 0}
 !2 = !{!"int", !3, i64 0}
 !3 = !{!"omnipotent char", !4, i64 0}
 !4 = !{!"Simple C/C++ TBAA"}

llvm/trunk/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll

 ; CHECK-NEXT:    ld 6, 0(4)
 ; CHECK-NEXT:    cmpld 5, 6
 ; CHECK-NEXT:    bne 0, .LBB1_2
 ; CHECK-NEXT:  # BB#1: # %loadbb1
 ; CHECK-NEXT:    ld 3, 8(3)
 ; CHECK-NEXT:    ld 4, 8(4)
 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    beq 0, .LBB1_3
+; CHECK-NEXT:    beqlr 0
 ; CHECK-NEXT:  .LBB1_2: # %res_block
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    clrldi 3, 3, 32
-; CHECK-NEXT:    blr
-; CHECK-NEXT:  .LBB1_3: # %endblock
-; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 16)
   %not.tobool = icmp ne i32 %call, 0
   %. = zext i1 %not.tobool to i32
   ret i32 %.
 }
 
 ; Check 7 bytes - requires 3 loads for each param.

 ; CHECK-NEXT:    lhz 6, 4(4)
 ; CHECK-NEXT:    cmplw 5, 6
 ; CHECK-NEXT:    bne 0, .LBB2_3
 ; CHECK-NEXT:  # BB#2: # %loadbb2
 ; CHECK-NEXT:    lbz 3, 6(3)
 ; CHECK-NEXT:    lbz 4, 6(4)
 ; CHECK-NEXT:    cmplw 3, 4
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    beq 0, .LBB2_4
+; CHECK-NEXT:    beqlr 0
 ; CHECK-NEXT:  .LBB2_3: # %res_block
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    clrldi 3, 3, 32
-; CHECK-NEXT:    blr
-; CHECK-NEXT:  .LBB2_4: # %endblock
-; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 7)
   %not.lnot = icmp ne i32 %call, 0
   %cond = zext i1 %not.lnot to i32
   ret i32 %cond
 }
 
 ; Validate with > 0

llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc0(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 0
   ret i8 %vecext
 ; CHECK-LABEL: @getuc0
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 8, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc0
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc1(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 1
   ret i8 %vecext
 ; CHECK-LABEL: @getuc1
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 16, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc1
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 56, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc2(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 2
   ret i8 %vecext
 ; CHECK-LABEL: @getuc2
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 24, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc2
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 48, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc3(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 3
   ret i8 %vecext
 ; CHECK-LABEL: @getuc3
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 32, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc3
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 40, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc4(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 4
   ret i8 %vecext
 ; CHECK-LABEL: @getuc4
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 40, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc4
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 32, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc5(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 5
   ret i8 %vecext
 ; CHECK-LABEL: @getuc5
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 48, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc5
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 24, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc6(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 6
   ret i8 %vecext
 ; CHECK-LABEL: @getuc6
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 56, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc6
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 16, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc7(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 7
   ret i8 %vecext
 ; CHECK-LABEL: @getuc7
 ; CHECK: mfvsrd 3, 34
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc7
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 8, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc8(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 8
   ret i8 %vecext
 ; CHECK-LABEL: @getuc8
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 8, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc8
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc9(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 9
   ret i8 %vecext
 ; CHECK-LABEL: @getuc9
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 16, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc9
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 56, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc10(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 10
   ret i8 %vecext
 ; CHECK-LABEL: @getuc10
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 24, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc10
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 48, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc11(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 11
   ret i8 %vecext
 ; CHECK-LABEL: @getuc11
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 32, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc11
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 40, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc12(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 12
   ret i8 %vecext
 ; CHECK-LABEL: @getuc12
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 40, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc12
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 32, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc13(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 13
   ret i8 %vecext
 ; CHECK-LABEL: @getuc13
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 48, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc13
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 24, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc14(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 14
   ret i8 %vecext
 ; CHECK-LABEL: @getuc14
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 56, 56
-; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc14
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 16, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc15(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 15
   ret i8 %vecext
 ; CHECK-LABEL: @getuc15
 ; CHECK: mfvsrd 3,
 ; CHECK: clrldi   3, 3, 56
 ; CHECK-LE-LABEL: @getuc15
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 8, 56
-; CHECK-LE: clrldi   3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 %i
   ret i8 %vecext
 ; CHECK-LABEL: @getvelsc

 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus0(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 0
   ret i16 %vecext
 ; CHECK-LABEL: @getus0
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 16, 48
-; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus0
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus1(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 1
   ret i16 %vecext
 ; CHECK-LABEL: @getus1
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 32, 48
-; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus1
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 48, 48
-; CHECK-LE: clrldi   3, 3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus2(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 2
   ret i16 %vecext
 ; CHECK-LABEL: @getus2
 ; CHECK: mfvsrd 3, 34
 ; CHECK: rldicl 3, 3, 48, 48
-; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus2
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 32, 48
-; CHECK-LE: clrldi   3, 3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus3(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 3
   ret i16 %vecext
 ; CHECK-LABEL: @getus3
 ; CHECK: mfvsrd 3, 34
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus3
 ; CHECK-LE: mfvsrd 3,
 ; CHECK-LE: rldicl 3, 3, 16, 48
-; CHECK-LE: clrldi   3, 3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus4(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 4
   ret i16 %vecext
 ; CHECK-LABEL: @getus4
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 16, 48
-; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus4
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: clrldi   3, 3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus5(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 5
   ret i16 %vecext
 ; CHECK-LABEL: @getus5
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 32, 48
-; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus5
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 48, 48
-; CHECK-LE: clrldi   3, 3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus6(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 6
   ret i16 %vecext
 ; CHECK-LABEL: @getus6
 ; CHECK: mfvsrd 3,
 ; CHECK: rldicl 3, 3, 48, 48
-; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus6
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 32, 48
-; CHECK-LE: clrldi   3, 3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus7(<8 x i16> %vus) {
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 7
   ret i16 %vecext
 ; CHECK-LABEL: @getus7
 ; CHECK: mfvsrd 3,
 ; CHECK: clrldi   3, 3, 48
 ; CHECK-LE-LABEL: @getus7
 ; CHECK-LE: mfvsrd 3, 34
 ; CHECK-LE: rldicl 3, 3, 16, 48
-; CHECK-LE: clrldi   3, 3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 %i
   ret i16 %vecext
 ; CHECK-LABEL: @getvelss

 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui0(<4 x i32> %vui) {
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 0
   ret i32 %vecext
 ; CHECK-LABEL: @getui0
 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
 ; CHECK: mfvsrwz 3, [[SHL]]
-; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui0
 ; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
-; CHECK-LE: clrldi   3, 3, 32
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui1(<4 x i32> %vui) {
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 1
   ret i32 %vecext
 ; CHECK-LABEL: @getui1
 ; CHECK: mfvsrwz 3, 34
-; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui1
 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
-; CHECK-LE: clrldi   3, 3, 32
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui2(<4 x i32> %vui) {
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 2
   ret i32 %vecext
 ; CHECK-LABEL: @getui2
 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
 ; CHECK: mfvsrwz 3, [[SHL]]
-; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui2
 ; CHECK-LE: mfvsrwz 3, 34
-; CHECK-LE: clrldi   3, 3, 32
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui3(<4 x i32> %vui) {
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 3
   ret i32 %vecext
 ; CHECK-LABEL: @getui3
 ; CHECK: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK: mfvsrwz 3, [[SHL]]
-; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui3
 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
-; CHECK-LE: clrldi   3, 3, 32
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) {
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 %i
   ret i32 %vecext
 ; CHECK-LABEL: @getvelsi

llvm/trunk/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll

for.body:                                         ; preds = %for.body.preheader, %for.cond
   br i1 %cmp1, label %for.cond, label %cleanup
 
 cleanup:                                          ; preds = %for.body, %for.cond, %entry
   %2 = phi i32 [ 0, %entry ], [ 0, %for.cond ], [ 1, %for.body ]
   ret i32 %2
 ; CHECK-LABEL: limit_loop
 ; CHECK: mtctr
 ; CHECK-NOT: addi {{[0-9]+}}, {{[0-9]+}}, 1
-; CHECK: bdnz
+; CHECK: bdzlr
 ; CHECK: blr
 }