This is an archive of the discontinued LLVM Phabricator instance.

Differential D31240

[PowerPC] Instruction Selection to eliminate compare instructions
AbandonedPublic

Authored by lei on Mar 22 2017, 6:47 AM.

Details

Reviewers
echristo
inouehrs
syzaara
kbarton
sfertile
jtony
hfinkel
nemanjai
Summary

Remove compare instructions from the code generation based on patterns outlined in the Compiler Writer's Guide (Appendix D).

D.1 Comparisons and Comparisons Against Zero
D.2 Negated Comparisons and Negated Comparisons Against Zero
D.3 ComparisonOperators

Diff Detail

Event Timeline

lei created this revision.Mar 22 2017, 6:47 AM
lei edited the summary of this revision. (Show Details)Mar 22 2017, 6:51 AM
lei edited the summary of this revision. (Show Details)Mar 22 2017, 6:55 AM
jtony added inline comments.Mar 22 2017, 7:01 AM
test/CodeGen/PowerPC/testComparesllgeuc.ll
19

I noticed that in some test cases we use generic registers (like here [[REG1]] ), and in some other test cases, we use the specific register (like r4,r5), I know this is caused by this patch are created by multiple people. But I think maybe it is worthwhile to use one format for all ? ( I personally prefer the auto generated one, but I am OK with both, as long as they are consistent)

lei added a reviewer: hfinkel.Mar 22 2017, 8:24 AM
lei added a subscriber: uweigand.
jtony added inline comments.Mar 22 2017, 8:55 AM
test/CodeGen/PowerPC/testComparesllgeuc.ll
19

I maybe not be clear enough, What I mean here is some test cases use generic names [[REG1:r[0-9]+]] (like this file testComparesllgeuc.ll), while the others just use whatever generated, like the setcc eqtest/CodeGen/PowerPC/testComparesieqsc.ll, there is no [[REG:r[0-9]+]] at all.

sfertile added inline comments.Mar 22 2017, 10:45 AM
test/CodeGen/PowerPC/testComparesllgeuc.ll
19

When writing these tests we want to use a specific register for the places where the abi dictates what register must be used, and variables for all other registers. For example in the next test (@test_llgeuc_sext):

subf [[REG1:r[0-9]+]], r4, r3 --> %a must be in register r3, and %b must be in register r4. The subf instruction isn't constrained to putting the result into a specific register so we shouldn't make any assumptions about which register it goes into as long as that result is used as the second operand of the rldicl instruction.

echristo added a reviewer: echristo.Mar 23 2017, 6:59 PM
echristo edited edge metadata.Mar 30 2017, 11:46 AM

Hi Lei,

This patch is pretty enormous. Is there any way you can split this out into multiple smaller patches that each implement a specific thing? It'll optimize a bit better for reviewer time here.

Thanks!

-eric

nemanjai edited edge metadata.Mar 30 2017, 2:17 PM
In D31240#714366, @echristo wrote:

Hi Lei,

This patch is pretty enormous. Is there any way you can split this out into multiple smaller patches that each implement a specific thing? It'll optimize a bit better for reviewer time here.

Thanks!

-eric

We initially discussed this a bit to try to come up with a way to split this out but didn't come up with particularly great ideas. The issues with splitting it up are:

  • The heart of the change is really the handling of ISD::SETCC nodes so is conceptually contained in one place
  • Majority of the changes are to the test cases

That being said, the least unreasonable way to split this up that I can suggest is the following:

  • Set of 4 patches corresponding to the 32/64 bit and ZEXT/SEXT functions that handle ISD::SETCC
  • Throughout the 4 patches, only use this for zero/sign extensions
  • In each patch, the remaining 3 functions are implemented but are stubs returning SDValue()
  • The fifth patch adds handling of ISD::SELECT
  • The sixth patch adds handling of ISD::SELECT_CC (including comparison operators)

All patches include test cases covering that patch

Let me know what you think.

echristo added a comment.Mar 30 2017, 2:19 PM

SGTM. Anything you can do to help manage complexity helps :)

-eric

spatel added a subscriber: spatel.Apr 5 2017, 6:34 AM
lei abandoned this revision.Apr 10 2017, 12:33 PM

Split into 6 different reviews:
https://reviews.llvm.org/D31847
https://reviews.llvm.org/D31848
https://reviews.llvm.org/D31849
https://reviews.llvm.org/D31850
https://reviews.llvm.org/D31851
https://reviews.llvm.org/D31852

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Diff 92628

lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
O << "\tmr "; O << "\tmr ";
printOperand(MI, 0, O); printOperand(MI, 0, O);
O << ", "; O << ", ";
printOperand(MI, 1, O); printOperand(MI, 1, O);
printAnnotation(O, Annot); printAnnotation(O, Annot);
return; return;
} }
if (MI->getOpcode() == PPC::RLDICR) { if (MI->getOpcode() == PPC::RLDICR ||
MI->getOpcode() == PPC::RLDICR_32) {
unsigned char SH = MI->getOperand(2).getImm(); unsigned char SH = MI->getOperand(2).getImm();
unsigned char ME = MI->getOperand(3).getImm(); unsigned char ME = MI->getOperand(3).getImm();
// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
if (63-SH == ME) { if (63-SH == ME) {
O << "\tsldi "; O << "\tsldi ";
printOperand(MI, 0, O); printOperand(MI, 0, O);
O << ", "; O << ", ";
printOperand(MI, 1, O); printOperand(MI, 1, O);
▲ Show 20 Lines • Show All 400 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCFastISel.cpp

Show First 20 Lines • Show All 2,240 Lines • ▼ Show 20 Lines switch(MI->getOpcode()) {
case PPC::EXTSH8: case PPC::EXTSH8:
case PPC::EXTSH8_32_64: { case PPC::EXTSH8_32_64: {
if (VT != MVT::i16 && VT != MVT::i8) if (VT != MVT::i16 && VT != MVT::i8)
return false; return false;
break; break;
} }
case PPC::EXTSW: case PPC::EXTSW:
case PPC::EXTSW_32:
case PPC::EXTSW_32_64: { case PPC::EXTSW_32_64: {
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8) if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
return false; return false;
break; break;
} }
} }
// See if we can handle this address. // See if we can handle this address.
▲ Show 20 Lines • Show All 118 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/Statistic.h"
#include <algorithm> #include <algorithm>
#include <cassert> #include <cassert>
#include <cstdint> #include <cstdint>
#include <iterator> #include <iterator>
#include <limits> #include <limits>
#include <memory> #include <memory>
#include <new> #include <new>
#include <tuple> #include <tuple>
#include <utility> #include <utility>
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "ppc-codegen" #define DEBUG_TYPE "ppc-codegen"
STATISTIC(NumSextSetcc,
"Number of (sext(setcc)) nodes expanded into GPR sequence.");
STATISTIC(NumZextSetcc,
"Number of (zext(setcc)) nodes expanded into GPR sequence.");
STATISTIC(NumSelectSetcc,
"Number of (select (setcc), PwrOf2, 0) nodes calculated in GPR.");
STATISTIC(NumSelectCCPow2True,
"Number of (select_cc a, b, PwrOf2, 0) nodes calculated in GPR.");
STATISTIC(NumSelectCCPow2False,
"Number of (select_cc a, b, 0, PwrOf2) nodes calculated in GPR.");
STATISTIC(NumComparisonOps,
"Number of cmp(a, b) => { 0, 1, -1 } calculated in GPR.");
STATISTIC(SignExtensionsAdded,
"Number of sign extensions for compare inputs added.");
STATISTIC(ZeroExtensionsAdded,
"Number of zero extensions for compare inputs added.");
// FIXME: Remove this once the bug has been fixed! // FIXME: Remove this once the bug has been fixed!
cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug", cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden); cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
static cl::opt<bool> static cl::opt<bool>
UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true), UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
cl::desc("use aggressive ppc isel for bit permutations"), cl::desc("use aggressive ppc isel for bit permutations"),
cl::Hidden); cl::Hidden);
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines StringRef getPassName() const override {
return "PowerPC DAG->DAG Pattern Instruction Selection"; return "PowerPC DAG->DAG Pattern Instruction Selection";
} }
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
#include "PPCGenDAGISel.inc" #include "PPCGenDAGISel.inc"
private: private:
bool trySETCC(SDNode *N); bool trySETCC(SDNode *N);
SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl);
SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl);
SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl);
SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
int64_t RHSValue, SDLoc dl);
bool trySELECT(SDNode *N);
bool tryEXTEND(SDNode *N);
bool trySELECT_CC(SDNode *N);
SDValue signExtendInputIfNeeded(SDValue Input);
SDValue zeroExtendInputIfNeeded(SDValue Input);
SDValue getSETCCInGPR(SDValue Compare, bool IsSext, bool InvertCC = false);
SDValue getSETGE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext);
SDValue getSETGE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext);
SDValue getSETLE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext);
SDValue getSETLE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext);
SDValue addExtOrTrunc(SDValue NatWidthRes, bool From32Bit,
bool To32Bit);
void PeepholePPC64(); void PeepholePPC64();
void PeepholePPC64ZExt(); void PeepholePPC64ZExt();
void PeepholeCROps(); void PeepholeCROps();
SDValue combineToCMPB(SDNode *N); SDValue combineToCMPB(SDNode *N);
void foldBoolExts(SDValue &Res, SDNode *&N); void foldBoolExts(SDValue &Res, SDNode *&N);
▲ Show 20 Lines • Show All 2,050 Lines • ▼ Show 20 Lines switch (CC) {
break; break;
default: default:
break; break;
} }
llvm_unreachable("Invalid integer vector compare condition"); llvm_unreachable("Invalid integer vector compare condition");
} }
} }
/// If the value isn't guaranteed to be sign-extended to 64-bits, extend it.
/// Useful when emitting comparison code for 32-bit values without using
/// the compare instruction (which only considers the lower 32-bits).
SDValue PPCDAGToDAGISel::signExtendInputIfNeeded(SDValue Input) {
ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
unsigned Opc = Input.getOpcode();
bool IsTruncateOfSext = Opc == ISD::TRUNCATE &&
(Input.getOperand(0).getOpcode() == ISD::AssertSext ||
Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND);
bool IsSextLoad = InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD;
if (InputConst || IsTruncateOfSext || Opc == ISD::AssertSext ||
Opc == ISD::SIGN_EXTEND_INREG || Opc == ISD::SIGN_EXTEND || IsSextLoad)
return Input;
SDLoc dl(Input);
SignExtensionsAdded++;
return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32, dl, MVT::i32, Input), 0);
}
/// If the value isn't guaranteed to be zero-extended to 64-bits, extend it.
/// Useful when emitting comparison code for 32-bit values without using
/// the compare instruction (which only considers the lower 32-bits).
SDValue PPCDAGToDAGISel::zeroExtendInputIfNeeded(SDValue Input) {
ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input);
LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input);
unsigned Opc = Input.getOpcode();
bool NonSextLoad =
InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD;
if (InputConst || Opc == ISD::TRUNCATE || Opc == ISD::AssertZext ||
Opc == ISD::ZERO_EXTEND || NonSextLoad)
return Input;
SDLoc dl(Input);
ZeroExtensionsAdded++;
return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Input,
getI64Imm(0, dl), getI64Imm(32, dl)),
0);
}
// Produces a sign/zero extended result of comparing whether a 32-bit value is
// less than or equal to zero.
SDValue PPCDAGToDAGISel::getSETLE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext) {
SDValue Neg =
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
SDValue Srdi =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
Neg, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
if (IsSext)
return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
getI32Imm(-1, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Srdi,
getI32Imm(1, dl)), 0);
}
// Produces a sign/zero extended result of comparing whether a 64-bit value is
// less than or equal to zero.
SDValue PPCDAGToDAGISel::getSETLE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext) {
SDValue Addi =
SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
getI64Imm(~0ULL, dl)), 0);
SDValue Or =
SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
Addi, LHS), 0);
if (IsSext)
return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Or,
getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
Or, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
}
// Produces a sign/zero extended result of comparing whether a 32-bit value is
// greater than or equal to zero.
SDValue PPCDAGToDAGISel::getSETGE0I32InGPR(SDValue LHS, SDLoc dl, bool IsSext) {
SDValue Not =
SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, LHS, LHS), 0);
if (IsSext)
return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, Not,
getI32Imm(31, dl)), 0);
SDValue ShiftOps[] =
{ Not, getI32Imm(1, dl), getI32Imm(31, dl), getI32Imm(31, dl) };
return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
ShiftOps), 0);
}
// Produces a sign/zero extended result of comparing whether a 64-bit value is
// greater than or equal to zero.
SDValue PPCDAGToDAGISel::getSETGE0I64InGPR(SDValue LHS, SDLoc dl, bool IsSext) {
SDValue Not =
SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, LHS, LHS), 0);
if (IsSext)
return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Not,
getI64Imm(31, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Not,
getI64Imm(1, dl), getI64Imm(63, dl)),
0);
}
static void swapAndReset(SDValue &LHS, SDValue &RHS, bool &IsRHSZero,
bool &IsRHSOne, bool &IsRHSNegOne) {
std::swap(LHS, RHS);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isNullValue();
IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
IsRHSNegOne = RHSConst && RHSConst->isAllOnesValue();
}
/// Produces a zero-extended result of comparing two 32-bit values according to
/// the passed condition code.
SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0;
bool IsRHSOne = RHSValue == 1;
bool IsRHSNegOne = RHSValue == -1LL;
switch (CC) {
default: llvm_unreachable("Unknown condition!");
case ISD::SETEQ: {
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
getI32Imm(31, dl) };
return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
ShiftOps), 0);
}
case ISD::SETNE: {
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] = { Clz, getI32Imm(27, dl), getI32Imm(5, dl),
getI32Imm(31, dl) };
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
getI32Imm(1, dl)), 0);
}
case ISD::SETGE: {
if(IsRHSZero)
return getSETGE0I32InGPR(LHS, dl, false);
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
SDValue SubOrNeg = IsRHSZero ?
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0) :
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, SubOrNeg,
getI64Imm(1, dl), getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,
MVT::i32, Shift, getI32Imm(1, dl)), 0);
}
case ISD::SETGT: {
if (IsRHSNegOne)
return getSETGE0I32InGPR(LHS, dl, false);
if (IsRHSZero) {
SDValue Neg =
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
Neg, getI32Imm(1, dl), getI32Imm(63, dl)), 0);
}
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLT: {
// Handle SETLT 1 (which is equivalent to SETLE 0)
if (IsRHSOne)
return getSETLE0I32InGPR(LHS, dl, false);
if (IsRHSZero) {
SDValue ShiftOps[] = { LHS, getI32Imm(1, dl), getI32Imm(31, dl),
getI32Imm(31, dl) };
return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
ShiftOps), 0);
}
SDValue SUBFNode =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
SUBFNode, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
}
case ISD::SETUGE:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULE: {
SDValue Subtract =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
SDValue SrdiNode =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
Subtract, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, SrdiNode,
getI32Imm(1, dl)), 0);
}
case ISD::SETUGT:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULT: {
// FIXME: This is converted upstream to a shift/subtract sequence that
// does excessive zero extension/truncation for i8 and i16.
SDValue Subtract =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
Subtract, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
}
}
}
/// Produces a sign-extended result of comparing two 32-bit values according to
/// the passed condition code.
SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0;
bool IsRHSOne = RHSValue == 1;
bool IsRHSNegOne = RHSValue == -1LL;
switch (CC) {
default: llvm_unreachable("Unknown condition!");
case ISD::SETEQ: {
SDValue CountInput = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Cntlzw =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0);
SDValue LSHROps[] =
{ Cntlzw, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) };
SDValue Srwi =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, LSHROps), 0);
SDValue SHLOps[] = { Srwi, getI32Imm(63, dl), getI32Imm(0, dl) };
SDValue Sldi =
SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi,
getI32Imm(63, dl)), 0);
}
case ISD::SETNE: {
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0);
SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0);
SDValue ShiftOps[] =
{ Clz, getI32Imm(27, dl), getI32Imm(5, dl), getI32Imm(31, dl) };
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0);
SDValue Xori =
SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
getI32Imm(1, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
}
case ISD::SETGE: {
if(IsRHSZero)
return getSETGE0I32InGPR(LHS, dl, true);
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
if (IsRHSZero)
return getSETLE0I32InGPR(LHS, dl, true);
SDValue SUBFNode =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,
LHS, RHS), 0);
SDValue Srdi =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, MVT::Glue,
SUBFNode, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
getI32Imm(-1, dl)), 0);
}
case ISD::SETGT: {
if (IsRHSNegOne)
return getSETGE0I32InGPR(LHS, dl, true);
if (IsRHSZero) {
SDValue Neg =
SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Neg,
getI64Imm(63, dl)), 0);
}
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLT: {
if (IsRHSOne)
return getSETLE0I32InGPR(LHS, dl, true);
if (IsRHSZero)
return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, LHS,
getI32Imm(31, dl)), 0);
SDValue SUBFNode =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32,
SUBFNode, getI64Imm(63, dl)), 0);
}
case ISD::SETUGE:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULE: {
SDValue Subtract =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
SDValue Shift =
SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Subtract,
getI32Imm(1, dl), getI32Imm(63,dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Shift,
getI32Imm(-1, dl)), 0);
}
case ISD::SETUGT:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULT: {
SDValue Subtract =
SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, RHS, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32,
Subtract, getI64Imm(63, dl)), 0);
}
}
}
/// Produces a zero-extended result of comparing two 64-bit values according to
/// the passed condition code.
SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0;
bool IsRHSOne = RHSValue == 1;
bool IsRHSNegOne = RHSValue == -1LL;
switch (CC) {
default: llvm_unreachable("Unknown condition!");
case ISD::SETEQ: {
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
SDValue Clz =
SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz,
getI64Imm(58, dl), getI64Imm(63, dl)),
0);
}
case ISD::SETNE: {
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
SDValue AC =
SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
Xor, getI32Imm(~0U, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC,
Xor, AC.getValue(1)), 0);
}
case ISD::SETGE: {
if (IsRHSZero)
return getSETGE0I64InGPR(LHS, dl, false);
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
if (IsRHSZero)
return getSETLE0I64InGPR(LHS, dl, false);
SDValue ShiftL =
SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
getI64Imm(1, dl), getI64Imm(63, dl)), 0);
SDValue ShiftR =
SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
getI64Imm(63, dl)), 0);
SDValue SubtractCarry =
SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
LHS, RHS), 1);
return SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
ShiftR, ShiftL, SubtractCarry), 0);
}
case ISD::SETGT: {
if (IsRHSNegOne)
return getSETGE0I64InGPR(LHS, dl, false);
if (IsRHSZero) {
SDValue Addi =
SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
getI64Imm(~0ULL, dl)), 0);
SDValue Nor =
SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Addi, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Nor,
getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
}
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLT: {
if (IsRHSOne)
return getSETLE0I64InGPR(LHS, dl, false);
if (IsRHSZero)
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
SDValue SRADINode =
SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
LHS, getI64Imm(63, dl)), 0);
SDValue SRDINode =
SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
RHS, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
SDValue SUBFC8Carry =
SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
RHS, LHS), 1);
SDValue ADDE8Node =
SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
SRDINode, SRADINode, SUBFC8Carry), 0);
return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
ADDE8Node, getI64Imm(1, dl)), 0);
}
case ISD::SETUGE:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULE: {
SDValue SUBFC8Carry =
SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
LHS, RHS), 1);
SDValue SUBFE8Node =
SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue,
LHS, LHS, SUBFC8Carry), 0);
return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64,
SUBFE8Node, getI64Imm(1, dl)), 0);
}
case ISD::SETUGT:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULT: {
SDValue SubtractCarry =
SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
RHS, LHS), 1);
SDValue ExtSub =
SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
LHS, LHS, SubtractCarry), 0);
return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
ExtSub), 0);
}
}
}
/// Produces a sign-extended result of comparing two 64-bit values according to
/// the passed condition code.
SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0;
bool IsRHSOne = RHSValue == 1;
bool IsRHSNegOne = RHSValue == -1LL;
switch (CC) {
default: llvm_unreachable("Unknown condition!");
case ISD::SETEQ: {
SDValue AddInput = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
SDValue Addic =
SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
AddInput, getI32Imm(~0U, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic,
Addic, Addic.getValue(1)), 0);
}
case ISD::SETNE: {
SDValue Xor = IsRHSZero ? LHS :
SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
SDValue SC =
SDValue(CurDAG->getMachineNode(PPC::SUBFIC8, dl, MVT::i64, MVT::Glue,
Xor, getI32Imm(0, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC,
SC, SC.getValue(1)), 0);
}
case ISD::SETGE: {
if (IsRHSZero)
return getSETGE0I64InGPR(LHS, dl, true);
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLE: {
if (IsRHSZero)
return getSETLE0I64InGPR(LHS, dl, true);
SDValue ShiftR =
SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
getI64Imm(63, dl)), 0);
SDValue ShiftL =
SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
getI64Imm(1, dl), getI64Imm(63, dl)), 0);
SDValue SubtractCarry =
SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
LHS, RHS), 1);
SDValue Adde =
SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
ShiftR, ShiftL, SubtractCarry), 0);
return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0);
}
case ISD::SETGT: {
if (IsRHSNegOne)
return getSETGE0I64InGPR(LHS, dl, true);
if (IsRHSZero) {
SDValue Add =
SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
getI64Imm(-1, dl)), 0);
SDValue Nor =
SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Add, LHS), 0);
return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Nor,
getI64Imm(63, dl)), 0);
}
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
}
case ISD::SETLT: {
if (IsRHSOne)
return getSETLE0I64InGPR(LHS, dl, true);
if (IsRHSZero) {
llvm_unreachable("Should be transformed upstream!");
return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, LHS,
getI64Imm(63, dl)), 0);
}
SDValue SRADINode =
SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64,
LHS, getI64Imm(63, dl)), 0);
SDValue SRDINode =
SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
RHS, getI64Imm(1, dl),
getI64Imm(63, dl)), 0);
SDValue SUBFC8Carry =
SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
RHS, LHS), 1);
SDValue ADDE8Node =
SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64,
SRDINode, SRADINode, SUBFC8Carry), 0);
SDValue XORI8Node =
SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64,
ADDE8Node, getI64Imm(1, dl)), 0);
return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64,
XORI8Node), 0);
}
case ISD::SETUGE:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULE: {
SDValue SubtractCarry =
SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
LHS, RHS), 1);
SDValue ExtSub =
SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue, LHS,
LHS, SubtractCarry), 0);
return SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64,
ExtSub, ExtSub), 0);
}
case ISD::SETUGT:
swapAndReset(LHS, RHS, IsRHSZero, IsRHSOne, IsRHSNegOne);
LLVM_FALLTHROUGH;
case ISD::SETULT: {
SDValue SubCarry =
SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
RHS, LHS), 1);
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64,
LHS, LHS, SubCarry), 0);
}
}
}
/// Returns an equivalent of a SETCC node but with the result the same width as
/// the inputs. This can nalso be used for SELECT_CC if either the true or false
/// values is a power of two while the other is zero.
SDValue PPCDAGToDAGISel::getSETCCInGPR(SDValue Compare, bool IsSext,
bool InvertCC) {
assert((Compare.getOpcode() == ISD::SETCC ||
Compare.getOpcode() == ISD::SELECT_CC) &&
"An ISD::SETCC node required here.");
SDValue LHS = Compare.getOperand(0);
SDValue RHS = Compare.getOperand(1);
bool IsSelectCC = Compare.getOpcode() == ISD::SELECT_CC;
ISD::CondCode CC =
cast<CondCodeSDNode>(Compare.getOperand(IsSelectCC ? 4 : 2))->get();
EVT InputVT = LHS.getValueType();
if (InputVT != MVT::i32 && InputVT != MVT::i64)
return SDValue();
SDLoc dl(Compare);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
bool Inputs32Bit = InputVT == MVT::i32;
int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
if (InvertCC)
CC = ISD::getSetCCInverse(CC, true);
if (ISD::isSignedIntSetCC(CC) && Inputs32Bit) {
LHS = signExtendInputIfNeeded(LHS);
RHS = signExtendInputIfNeeded(RHS);
} else if (Inputs32Bit) {
LHS = zeroExtendInputIfNeeded(LHS);
RHS = zeroExtendInputIfNeeded(RHS);
}
if (Inputs32Bit && IsSext)
return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
else if (Inputs32Bit)
return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
else if (IsSext)
return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
}
/// If this node is a sign/zero extension of an integer comparison,
/// it can usually be computed in GPR's rather than using comparison
/// instructions and ISEL.
bool PPCDAGToDAGISel::tryEXTEND(SDNode *N) {
if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
return false;
assert((N->getOpcode() == ISD::ZERO_EXTEND ||
N->getOpcode() == ISD::SIGN_EXTEND) &&
"Expecting a zero/sign extend node!");
if (N->getOperand(0).getOpcode() != ISD::SETCC)
return false;
SDLoc dl(N);
SDValue WideRes = getSETCCInGPR(N->getOperand(0),
N->getOpcode() == ISD::SIGN_EXTEND);
bool Inputs32Bit = N->getOperand(0).getOperand(0).getValueType() == MVT::i32;
bool Output32Bit = N->getValueType(0) == MVT::i32;
if (!WideRes)
return false;
if (N->getOpcode() == ISD::SIGN_EXTEND)
NumSextSetcc++;
else
NumZextSetcc++;
SDValue ConvOp = addExtOrTrunc(WideRes, Inputs32Bit, Output32Bit);
ReplaceNode(N, ConvOp.getNode());
return true;
}
// Handle select (setcc), pwrOf2, 0.
bool PPCDAGToDAGISel::trySELECT(SDNode *N) {
if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
return false;
if (N->getOperand(0).getOpcode() != ISD::SETCC)
return false;
SDValue TrueVal = N->getOperand(1);
SDValue FalseVal = N->getOperand(2);
ConstantSDNode *TrueConst = dyn_cast<ConstantSDNode>(TrueVal);
ConstantSDNode *FalseConst = dyn_cast<ConstantSDNode>(FalseVal);
if (!TrueConst || !FalseConst || !isPowerOf2_64(TrueConst->getSExtValue()) ||
!FalseConst->isNullValue())
return false;
// Get the result of the comparison in a GPR.
SDValue SCCInGPR = getSETCCInGPR(N->getOperand(0), false);
if (!SCCInGPR)
return false;
SDLoc dl(N);
EVT InputVT = SCCInGPR.getValueType();
EVT OutputVT = N->getValueType(0);
bool Input32Bit = InputVT == MVT::i32;
bool Output32Bit = OutputVT == MVT::i32;
SDValue ConvOp = addExtOrTrunc(SCCInGPR, Input32Bit, Output32Bit);
// Shift the result of the comparison as required.
if (Output32Bit) {
uint32_t ShAmt = Log2_32(TrueConst->getSExtValue());
SDValue Ops[] = { ConvOp, getI32Imm(ShAmt, dl), getI32Imm(0, dl),
getI32Imm(31 - ShAmt, dl) };
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} else {
uint64_t ShAmt = Log2_64(TrueConst->getSExtValue());
CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, ConvOp,
getI64Imm(ShAmt, dl), getI64Imm(63 - ShAmt, dl));
}
NumSelectSetcc++;
return true;
}
// Is this a comparison operator (i.e. returns 0 if the values are equal,
// -1 if the first value is less and 1 if the first value is greater)?
static bool isComparisonOp(SDNode *N) {
if (N->getOpcode() != ISD::SELECT_CC)
return false;
SDValue DefFalse = N->getOperand(3);
SDValue MyLHS = N->getOperand(0);
SDValue MyRHS = N->getOperand(1);
ISD::CondCode MyCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
ConstantSDNode *MyTrueConst = dyn_cast<ConstantSDNode>(N->getOperand(2));
if (!MyTrueConst)
return false;
// The false value may be a zero/sign extended result of a setcc.
if (DefFalse.getOpcode() == ISD::ZERO_EXTEND ||
DefFalse.getOpcode() == ISD::SIGN_EXTEND) {
if (DefFalse.getOperand(0).getOpcode() != ISD::SETCC)
return false;
SDValue SetCC = DefFalse.getOperand(0);
if (SetCC.getOperand(0) != MyLHS || SetCC.getOperand(1) != MyRHS)
return false;
ISD::CondCode DefCC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
if (MyTrueConst->getSExtValue() == 1 && MyCC == ISD::SETUGT &&
DefFalse.getOpcode() == ISD::SIGN_EXTEND &&
(DefCC == ISD::SETNE || DefCC == ISD::SETULT))
return true;
if (MyTrueConst->isAllOnesValue() && MyCC == ISD::SETULT &&
DefFalse.getOpcode() == ISD::ZERO_EXTEND &&
DefCC == ISD::SETNE)
return true;
return false;
}
if (DefFalse.getOpcode() != ISD::SELECT_CC)
return false;
SDValue DefLHS = DefFalse.getOperand(0);
SDValue DefRHS = DefFalse.getOperand(1);
if (MyLHS != DefLHS || MyRHS != DefRHS)
return false;
ConstantSDNode *DefTrueConst =
dyn_cast<ConstantSDNode>(DefFalse.getOperand(2));
ConstantSDNode *DefFalseConst =
dyn_cast<ConstantSDNode>(DefFalse.getOperand(3));
ISD::CondCode DefCC = cast<CondCodeSDNode>(DefFalse.getOperand(4))->get();
if (!DefTrueConst || !DefFalseConst || !MyTrueConst)
return false;
if (MyTrueConst->isNullValue() && MyCC == ISD::SETEQ &&
DefTrueConst->isAllOnesValue() && DefFalseConst->getSExtValue() == 1 &&
DefCC == ISD::SETULT)
return true;
if (MyTrueConst->isNullValue() && MyCC == ISD::SETEQ &&
DefTrueConst->getSExtValue() == 1 && DefFalseConst->isAllOnesValue() &&
DefCC == ISD::SETUGT)
return true;
return false;
}
// Handle select_cc %a, %b, pwrOf2, 0
// and select_cc %a, %b, 0, pwrOf2
bool PPCDAGToDAGISel::trySELECT_CC(SDNode *N) {
if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
return false;
SDValue TrueVal = N->getOperand(2);
SDValue FalseVal = N->getOperand(3);
ConstantSDNode *TrueConst = dyn_cast<ConstantSDNode>(TrueVal);
ConstantSDNode *FalseConst = dyn_cast<ConstantSDNode>(FalseVal);
EVT InputVT = N->getOperand(0).getValueType();
EVT OutputVT = TrueVal.getValueType();
SDLoc dl(N);
// Can only do this if comparing and returning integers.
if ((InputVT != MVT::i32 && InputVT != MVT::i64) ||
(OutputVT != MVT::i32 && OutputVT != MVT::i64))
return false;
bool Input32Bit = InputVT == MVT::i32;
bool Output32Bit = OutputVT == MVT::i32;
// Comparison operators will typically be in the DAG as SELECT_CC nodes.
if (isComparisonOp(N)) {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue Subtract =
SDValue(CurDAG->getMachineNode(Input32Bit ? PPC::SUBF : PPC::SUBF8, dl,
InputVT, RHS, LHS), 0);
SDValue SubC =
SDValue(CurDAG->getMachineNode(Input32Bit ? PPC::SUBFC : PPC::SUBFC8, dl,
InputVT, MVT::Glue, LHS, RHS), 1);
SDValue SubExt1 =
SDValue(CurDAG->getMachineNode(Input32Bit ? PPC::SUBFE : PPC::SUBFE8, dl,
InputVT, MVT::Glue, RHS, LHS, SubC), 0);
SDValue SubExt2 =
SDValue(CurDAG->getMachineNode(Input32Bit ? PPC::SUBFE : PPC::SUBFE8, dl,
InputVT, SubExt1, Subtract,
SubExt1.getValue(1)), 0);
SDValue ConvOp = addExtOrTrunc(SubExt2, Input32Bit, Output32Bit);
ReplaceNode(N, ConvOp.getNode());
NumComparisonOps++;
return true;
}
if (!TrueConst || !FalseConst)
return false;
SDValue SCCInGPR;
uint64_t ShAmt = 0;
// Is this select_cc %a, %b, 0, pwrOf2
if (TrueConst->isNullValue() &&
isPowerOf2_64(FalseConst->getSExtValue())) {
SCCInGPR = getSETCCInGPR(SDValue(N, 0), false, true);
if (!SCCInGPR)
return false;
NumSelectCCPow2False++;
ShAmt = Log2_64(FalseConst->getSExtValue());
} else if (FalseConst->isNullValue() &&
isPowerOf2_64(TrueConst->getSExtValue())) {
// Is this select_cc %a, %b, pwrOf2, 0
SCCInGPR = getSETCCInGPR(SDValue(N, 0), false);
if (!SCCInGPR)
return false;
NumSelectCCPow2True++;
ShAmt = Log2_64(TrueConst->getSExtValue());
} else
return false;
SDValue ConvOp = addExtOrTrunc(SCCInGPR, Input32Bit, Output32Bit);
if (ShAmt && Output32Bit) {
SDValue Ops[] = { ConvOp, getI32Imm(ShAmt, dl), getI32Imm(0, dl),
getI32Imm(31 - ShAmt, dl) };
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
} else if (ShAmt) {
CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, ConvOp,
getI64Imm(ShAmt, dl), getI64Imm(63 - ShAmt, dl));
} else
ReplaceNode(N, ConvOp.getNode());
return true;
}
// Handle a 32-bit value in a 64-bit register and vice-versa.
SDValue PPCDAGToDAGISel::addExtOrTrunc(SDValue NatWidthRes, bool From32Bit,
bool To32Bit) {
SDLoc dl(NatWidthRes);
SDValue ConvOp = NatWidthRes;
if (From32Bit && !To32Bit) {
SDValue ImDef(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, MVT::i64), 0);
SDValue SubRegIdx =
CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
ConvOp = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, MVT::i64,
ImDef, NatWidthRes, SubRegIdx), 0);
} else if (!From32Bit && To32Bit) {
SDValue SubRegIdx =
CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32);
ConvOp = SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32,
NatWidthRes, SubRegIdx), 0);
}
return ConvOp;
}
bool PPCDAGToDAGISel::trySETCC(SDNode *N) { bool PPCDAGToDAGISel::trySETCC(SDNode *N) {
SDLoc dl(N); SDLoc dl(N);
unsigned Imm; unsigned Imm;
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
EVT PtrVT = EVT PtrVT =
CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout()); CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
bool isPPC64 = (PtrVT == MVT::i64); bool isPPC64 = (PtrVT == MVT::i64);
▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Linesvoid PPCDAGToDAGISel::Select(SDNode *N) {
case ISD::Constant: case ISD::Constant:
if (N->getValueType(0) == MVT::i64) { if (N->getValueType(0) == MVT::i64) {
ReplaceNode(N, getInt64(CurDAG, N)); ReplaceNode(N, getInt64(CurDAG, N));
return; return;
} }
break; break;
case ISD::ZERO_EXTEND:
case ISD::SIGN_EXTEND:
if (tryEXTEND(N))
return;
break;
case ISD::SETCC: case ISD::SETCC:
if (trySETCC(N)) if (trySETCC(N))
return; return;
break; break;
case ISD::SELECT:
if (trySELECT(N))
return;
break;
case PPCISD::GlobalBaseReg: case PPCISD::GlobalBaseReg:
ReplaceNode(N, getGlobalBaseReg()); ReplaceNode(N, getGlobalBaseReg());
return; return;
case ISD::FrameIndex: case ISD::FrameIndex:
selectFrameIndex(N, N); selectFrameIndex(N, N);
return; return;
▲ Show 20 Lines • Show All 321 Lines • ▼ Show 20 Lines SDValue SRIdxVal =
CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ? CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
PPC::sub_eq : PPC::sub_gt, dl, MVT::i32); PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, CR0Reg, CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, CR0Reg,
SRIdxVal, SDValue(AndI.getNode(), 1) /* glue */); SRIdxVal, SDValue(AndI.getNode(), 1) /* glue */);
return; return;
} }
case ISD::SELECT_CC: { case ISD::SELECT_CC: {
if (trySELECT_CC(N))
return;
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
EVT PtrVT = EVT PtrVT =
CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout()); CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
bool isPPC64 = (PtrVT == MVT::i64); bool isPPC64 = (PtrVT == MVT::i64);
// If this is a select of i1 operands, we'll pattern match it. // If this is a select of i1 operands, we'll pattern match it.
if (PPCSubTarget->useCRBits() && if (PPCSubTarget->useCRBits() &&
N->getOperand(0).getValueType() == MVT::i1) N->getOperand(0).getValueType() == MVT::i1)
▲ Show 20 Lines • Show All 1,703 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCInstr64Bit.td

Show First 20 Lines • Show All 628 Lines • ▼ Show 20 Lines
defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
"extsw", "$rA, $rS", IIC_IntSimple, "extsw", "$rA, $rS", IIC_IntSimple,
[(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
"extsw", "$rA, $rS", IIC_IntSimple, "extsw", "$rA, $rS", IIC_IntSimple,
[(set i64:$rA, (sext i32:$rS))]>, isPPC64; [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
let isCodeGenOnly = 1 in
def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS),
"extsw $rA, $rS", IIC_IntSimple,
[]>, isPPC64;
defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
"sradi", "$rA, $rS, $SH", IIC_IntRotateDI, "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
[(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
// For fast-isel:
let isCodeGenOnly = 1 in
def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH),
"sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64;
defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
"cntlzd", "$rA, $rS", IIC_IntGeneral, "cntlzd", "$rA, $rS", IIC_IntGeneral,
[(set i64:$rA, (ctlz i64:$rS))]>; [(set i64:$rA, (ctlz i64:$rS))]>;
defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS),
"cnttzd", "$rA, $rS", IIC_IntGeneral, "cnttzd", "$rA, $rS", IIC_IntGeneral,
[(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>;
def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
"popcntd $rA, $rS", IIC_IntGeneral, "popcntd $rA, $rS", IIC_IntGeneral,
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Linesdefm RLDCR : MDSForm_1r<30, 9,
[]>, isPPC64; []>, isPPC64;
defm RLDICL : MDForm_1r<30, 0, defm RLDICL : MDForm_1r<30, 0,
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
"rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
// For fast-isel: // For fast-isel:
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def RLDICL_32_64 : MDForm_1<30, 0, def RLDICL_32_64 : MDForm_1<30, 0,
(outs g8rc:$rA), (outs g8rc:$rA),
(ins gprc:$rS, u6imm:$SH, u6imm:$MBE), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
"rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
// End fast-isel. // End fast-isel.
let isCodeGenOnly = 1 in
def RLDICL_32 : MDForm_1<30, 0,
(outs gprc:$rA),
(ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
"rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64;
defm RLDICR : MDForm_1r<30, 1, defm RLDICR : MDForm_1r<30, 1,
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
"rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
let isCodeGenOnly = 1 in
def RLDICR_32 : MDForm_1<30, 1,
(outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
"rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64;
defm RLDIC : MDForm_1r<30, 2, defm RLDIC : MDForm_1r<30, 2,
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
"rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
(ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
▲ Show 20 Lines • Show All 568 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCInstrInfo.cpp

Show First 20 Lines • Show All 248 Lines • ▼ Show 20 Lines
// Detect 32 -> 64-bit extensions where we may reuse the low sub-register. // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg, unsigned &SrcReg, unsigned &DstReg,
unsigned &SubIdx) const { unsigned &SubIdx) const {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
default: return false; default: return false;
case PPC::EXTSW: case PPC::EXTSW:
case PPC::EXTSW_32:
case PPC::EXTSW_32_64: case PPC::EXTSW_32_64:
SrcReg = MI.getOperand(1).getReg(); SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg(); DstReg = MI.getOperand(0).getReg();
SubIdx = PPC::sub_32; SubIdx = PPC::sub_32;
return true; return true;
} }
} }
▲ Show 20 Lines • Show All 1,669 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCMIPeephole.cpp

Show All 21 Lines
#include "PPCInstrInfo.h" #include "PPCInstrInfo.h"
#include "PPC.h" #include "PPC.h"
#include "PPCInstrBuilder.h" #include "PPCInstrBuilder.h"
#include "PPCTargetMachine.h" #include "PPCTargetMachine.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/ADT/Statistic.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "ppc-mi-peepholes" #define DEBUG_TYPE "ppc-mi-peepholes"
STATISTIC(SignExtensionsRemoved,
"Number of EXTSW instructions removed.");
namespace llvm { namespace llvm {
void initializePPCMIPeepholePass(PassRegistry&); void initializePPCMIPeepholePass(PassRegistry&);
} }
namespace { namespace {
struct PPCMIPeephole : public MachineFunctionPass { struct PPCMIPeephole : public MachineFunctionPass {
▲ Show 20 Lines • Show All 289 Lines • ▼ Show 20 Lines for (MachineInstr &MI : MBB) {
removeFRSPIfPossible(P1); removeFRSPIfPossible(P1);
removeFRSPIfPossible(P2); removeFRSPIfPossible(P2);
break; break;
} }
removeFRSPIfPossible(P1); removeFRSPIfPossible(P1);
} }
break; break;
} }
case PPC::EXTSW:
case PPC::EXTSW_32:
case PPC::EXTSW_32_64: {
unsigned NarrowReg = MI.getOperand(1).getReg();
if (!TargetRegisterInfo::isVirtualRegister(NarrowReg))
break;
MachineInstr *DefMI = MRI->getVRegDef(NarrowReg);
if (!MRI->hasOneNonDBGUse(DefMI->getOperand(0).getReg()))
break;
// If we've used a zero-extending load that we will sign-extend,
// just do a sign-extending load.
if (DefMI->getOpcode() == PPC::LWZ) {
unsigned Opc =
(MI.getOpcode() == PPC::EXTSW ||
MI.getOpcode() == PPC::EXTSW_32_64) ? PPC::LWA : PPC::LWA_32;
DEBUG(dbgs() << "Removing redundant sign extension:\n");
DEBUG(MI.dump());
DEBUG(dbgs() << "As it was fed by:\n");
DEBUG(DefMI->dump());
DefMI->setDesc(TII->get(Opc));
DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
ToErase = &MI;
Simplified = true;
SignExtensionsRemoved++;
}
break;
}
} }
} }
// If the last instruction was marked for elimination, // If the last instruction was marked for elimination,
// remove it now. // remove it now.
if (ToErase) { if (ToErase) {
ToErase->eraseFromParent(); ToErase->eraseFromParent();
ToErase = nullptr; ToErase = nullptr;
} }
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/comparisonOps32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
@ga = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @compOp1(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp1:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%cmp1 = icmp ult i32 %a, %b
%. = select i1 %cmp1, i32 -1, i32 1
%retval.0 = select i1 %cmp, i32 0, i32 %.
ret i32 %retval.0
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @compOp2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%cmp1 = icmp ugt i32 %a, %b
%. = select i1 %cmp1, i32 1, i32 -1
%retval.0 = select i1 %cmp, i32 0, i32 %.
ret i32 %retval.0
}
; Function Attrs: norecurse nounwind readnone
; FIXME: the extsw is unnecessary but is in the DAG as well.
define signext i32 @compOp3(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%not.cmp1 = icmp ne i32 %a, %b
%. = sext i1 %not.cmp1 to i32
%retval.0 = select i1 %cmp, i32 1, i32 %.
ret i32 %retval.0
}
; Function Attrs: norecurse nounwind readnone
; FIXME: the extsw is unnecessary but is in the DAG as well.
define signext i32 @compOp4(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp4:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%cmp1 = icmp ult i32 %a, %b
%. = sext i1 %cmp1 to i32
%retval.0 = select i1 %cmp, i32 1, i32 %.
ret i32 %retval.0
}
; Function Attrs: norecurse nounwind readnone
; FIXME: the extsw is unnecessary but is in the DAG as well.
define signext i32 @compOp5(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp5:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%not.cmp1 = icmp ne i32 %a, %b
%. = zext i1 %not.cmp1 to i32
%retval.0 = select i1 %cmp, i32 -1, i32 %.
ret i32 %retval.0
}
; Function Attrs: norecurse nounwind readnone
; FIXME: this is still done with compares, we may fix that in the future
define signext i32 @compOp6(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp6:
entry:
%cmp = icmp ult i32 %a, %b
%cmp1 = icmp ugt i32 %a, %b
%. = zext i1 %cmp1 to i32
%retval.0 = select i1 %cmp, i32 -1, i32 %.
ret i32 %retval.0
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @compOp7(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp7:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%cmp1 = icmp ult i32 %a, %b
%cond = select i1 %cmp1, i32 -1, i32 1
%cond2 = select i1 %cmp, i32 0, i32 %cond
ret i32 %cond2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @compOp8(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp8:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%cmp1 = icmp ugt i32 %a, %b
%cond = select i1 %cmp1, i32 1, i32 -1
%cond2 = select i1 %cmp, i32 0, i32 %cond
ret i32 %cond2
}
; Function Attrs: norecurse nounwind readnone
; FIXME: the extsw is unnecessary but is in the DAG as well.
define signext i32 @compOp9(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp9:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%not.cmp1 = icmp ne i32 %a, %b
%cond = zext i1 %not.cmp1 to i32
%cond2 = select i1 %cmp, i32 -1, i32 %cond
ret i32 %cond2
}
; Function Attrs: norecurse nounwind readnone
; FIXME: this is still done with compares, we may fix that in the future
define signext i32 @compOp10(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp10:
entry:
%cmp = icmp ult i32 %a, %b
%cmp1 = icmp ugt i32 %a, %b
%cond = zext i1 %cmp1 to i32
%cond2 = select i1 %cmp, i32 -1, i32 %cond
ret i32 %cond2
}
; Function Attrs: norecurse nounwind readnone
; FIXME: the extsw is unnecessary but is in the DAG as well.
define signext i32 @compOp11(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp11:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%not.cmp1 = icmp ne i32 %a, %b
%cond = sext i1 %not.cmp1 to i32
%cond2 = select i1 %cmp, i32 1, i32 %cond
ret i32 %cond2
}
; Function Attrs: norecurse nounwind readnone
; FIXME: the extsw is unnecessary but is in the DAG as well.
define signext i32 @compOp12(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: compOp12:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: subf r5, r4, r3
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r5
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%cmp1 = icmp ult i32 %a, %b
%cond = sext i1 %cmp1 to i32
%cond2 = select i1 %cmp, i32 1, i32 %cond
ret i32 %cond2
}
; Function Attrs: norecurse nounwind
define void @store1(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store1:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp eq i32 %a, %b
%cmp1.i = icmp ult i32 %a, %b
%..i = select i1 %cmp1.i, i32 -1, i32 1
%retval.0.i = select i1 %cmp.i, i32 0, i32 %..i
store i32 %retval.0.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @store2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp eq i32 %a, %b
%cmp1.i = icmp ugt i32 %a, %b
%..i = select i1 %cmp1.i, i32 1, i32 -1
%retval.0.i = select i1 %cmp.i, i32 0, i32 %..i
store i32 %retval.0.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @store3(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ugt i32 %a, %b
%not.cmp1.i = icmp ne i32 %a, %b
%..i = sext i1 %not.cmp1.i to i32
%retval.0.i = select i1 %cmp.i, i32 1, i32 %..i
store i32 %retval.0.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @store4(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store4:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ugt i32 %a, %b
%cmp1.i = icmp ult i32 %a, %b
%..i = sext i1 %cmp1.i to i32
%retval.0.i = select i1 %cmp.i, i32 1, i32 %..i
store i32 %retval.0.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @store5(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store5:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ult i32 %a, %b
%not.cmp1.i = icmp ne i32 %a, %b
%..i = zext i1 %not.cmp1.i to i32
%retval.0.i = select i1 %cmp.i, i32 -1, i32 %..i
store i32 %retval.0.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
; FIXME: this is still done with compares, we may fix that in the future
define void @store6(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store6:
entry:
%cmp.i = icmp ult i32 %a, %b
%cmp1.i = icmp ugt i32 %a, %b
%..i = zext i1 %cmp1.i to i32
%retval.0.i = select i1 %cmp.i, i32 -1, i32 %..i
store i32 %retval.0.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @store7(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store7:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp eq i32 %a, %b
%cmp1.i = icmp ult i32 %a, %b
%cond.i = select i1 %cmp1.i, i32 -1, i32 1
%cond2.i = select i1 %cmp.i, i32 0, i32 %cond.i
store i32 %cond2.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @store8(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store8:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp eq i32 %a, %b
%cmp1.i = icmp ugt i32 %a, %b
%cond.i = select i1 %cmp1.i, i32 1, i32 -1
%cond2.i = select i1 %cmp.i, i32 0, i32 %cond.i
store i32 %cond2.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @store9(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store9:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ult i32 %a, %b
%not.cmp1.i = icmp ne i32 %a, %b
%cond.i = zext i1 %not.cmp1.i to i32
%cond2.i = select i1 %cmp.i, i32 -1, i32 %cond.i
store i32 %cond2.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
; FIXME: this is still done with compares, we may fix that in the future
define void @store10(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store10:
entry:
%cmp.i = icmp ult i32 %a, %b
%cmp1.i = icmp ugt i32 %a, %b
%cond.i = zext i1 %cmp1.i to i32
%cond2.i = select i1 %cmp.i, i32 -1, i32 %cond.i
store i32 %cond2.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @store11(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store11:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ugt i32 %a, %b
%not.cmp1.i = icmp ne i32 %a, %b
%cond.i = sext i1 %not.cmp1.i to i32
%cond2.i = select i1 %cmp.i, i32 1, i32 %cond.i
store i32 %cond2.i, i32* @ga, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @store12(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: store12:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: subf r6, r4, r3
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r6
; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ugt i32 %a, %b
%cmp1.i = icmp ult i32 %a, %b
%cond.i = sext i1 %cmp1.i to i32
%cond2.i = select i1 %cmp.i, i32 1, i32 %cond.i
store i32 %cond2.i, i32* @ga, align 4
ret void
}

test/CodeGen/PowerPC/comparisonOps64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
@ga = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @compOp1(i64 %a, i64 %b) {
; CHECK-LABEL: compOp1:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%cmp1 = icmp ult i64 %a, %b
%. = select i1 %cmp1, i64 -1, i64 1
%retval.0 = select i1 %cmp, i64 0, i64 %.
ret i64 %retval.0
}
; Function Attrs: norecurse nounwind readnone
define i64 @compOp2(i64 %a, i64 %b) {
; CHECK-LABEL: compOp2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%cmp1 = icmp ugt i64 %a, %b
%. = select i1 %cmp1, i64 1, i64 -1
%retval.0 = select i1 %cmp, i64 0, i64 %.
ret i64 %retval.0
}
; Function Attrs: norecurse nounwind readnone
define i64 @compOp3(i64 %a, i64 %b) {
; CHECK-LABEL: compOp3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%not.cmp1 = icmp ne i64 %a, %b
%. = sext i1 %not.cmp1 to i64
%retval.0 = select i1 %cmp, i64 1, i64 %.
ret i64 %retval.0
}
; Function Attrs: norecurse nounwind readnone
define i64 @compOp4(i64 %a, i64 %b) {
; CHECK-LABEL: compOp4:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%cmp1 = icmp ult i64 %a, %b
%. = sext i1 %cmp1 to i64
%retval.0 = select i1 %cmp, i64 1, i64 %.
ret i64 %retval.0
}
; Function Attrs: norecurse nounwind readnone
define i64 @compOp5(i64 %a, i64 %b) {
; CHECK-LABEL: compOp5:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i64 %a, %b
%not.cmp1 = icmp ne i64 %a, %b
%. = zext i1 %not.cmp1 to i64
%retval.0 = select i1 %cmp, i64 -1, i64 %.
ret i64 %retval.0
}
; Function Attrs: norecurse nounwind readnone
; FIXME: this is still done with compares, we may fix that in the future
define i64 @compOp6(i64 %a, i64 %b) {
; CHECK-LABEL: compOp6:
entry:
%cmp = icmp ult i64 %a, %b
%cmp1 = icmp ugt i64 %a, %b
%. = zext i1 %cmp1 to i64
%retval.0 = select i1 %cmp, i64 -1, i64 %.
ret i64 %retval.0
}
; Function Attrs: norecurse nounwind readnone
define i64 @compOp7(i64 %a, i64 %b) {
; CHECK-LABEL: compOp7:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%cmp1 = icmp ult i64 %a, %b
%phitmp = select i1 %cmp1, i64 -1, i64 1
%cond2 = select i1 %cmp, i64 0, i64 %phitmp
ret i64 %cond2
}
; Function Attrs: norecurse nounwind readnone
define i64 @compOp8(i64 %a, i64 %b) {
; CHECK-LABEL: compOp8:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%cmp1 = icmp ugt i64 %a, %b
%phitmp = select i1 %cmp1, i64 1, i64 -1
%cond2 = select i1 %cmp, i64 0, i64 %phitmp
ret i64 %cond2
}
; Function Attrs: norecurse nounwind readnone
define i64 @compOp9(i64 %a, i64 %b) {
; CHECK-LABEL: compOp9:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i64 %a, %b
%not.cmp1 = icmp ne i64 %a, %b
%phitmp = zext i1 %not.cmp1 to i64
%cond2 = select i1 %cmp, i64 -1, i64 %phitmp
ret i64 %cond2
}
; Function Attrs: norecurse nounwind readnone
; FIXME: this is still done with compares, we may fix that in the future
define i64 @compOp10(i64 %a, i64 %b) {
; CHECK-LABEL: compOp10:
entry:
%cmp = icmp ult i64 %a, %b
%cmp1 = icmp ugt i64 %a, %b
%phitmp = zext i1 %cmp1 to i64
%cond2 = select i1 %cmp, i64 -1, i64 %phitmp
ret i64 %cond2
}
; Function Attrs: norecurse nounwind readnone
define i64 @compOp11(i64 %a, i64 %b) {
; CHECK-LABEL: compOp11:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%not.cmp1 = icmp ne i64 %a, %b
%phitmp = sext i1 %not.cmp1 to i64
%cond2 = select i1 %cmp, i64 1, i64 %phitmp
ret i64 %cond2
}
; Function Attrs: norecurse nounwind readnone
define i64 @compOp12(i64 %a, i64 %b) {
; CHECK-LABEL: compOp12:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r5, r3, r4
; CHECK-NEXT: sub r5, r3, r4
; CHECK-NEXT: subfe r12, r4, r3
; CHECK-NEXT: subfe r3, r12, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%cmp1 = icmp ult i64 %a, %b
%phitmp = sext i1 %cmp1 to i64
%cond2 = select i1 %cmp, i64 1, i64 %phitmp
ret i64 %cond2
}
; Function Attrs: norecurse nounwind
define void @store1(i64 %a, i64 %b) {
; CHECK-LABEL: store1:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp eq i64 %a, %b
%cmp1.i = icmp ult i64 %a, %b
%..i = select i1 %cmp1.i, i64 -1, i64 1
%retval.0.i = select i1 %cmp.i, i64 0, i64 %..i
store i64 %retval.0.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @store2(i64 %a, i64 %b) {
; CHECK-LABEL: store2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp eq i64 %a, %b
%cmp1.i = icmp ugt i64 %a, %b
%..i = select i1 %cmp1.i, i64 1, i64 -1
%retval.0.i = select i1 %cmp.i, i64 0, i64 %..i
store i64 %retval.0.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @store3(i64 %a, i64 %b) {
; CHECK-LABEL: store3:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ugt i64 %a, %b
%not.cmp1.i = icmp ne i64 %a, %b
%..i = sext i1 %not.cmp1.i to i64
%retval.0.i = select i1 %cmp.i, i64 1, i64 %..i
store i64 %retval.0.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @store4(i64 %a, i64 %b) {
; CHECK-LABEL: store4:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ugt i64 %a, %b
%cmp1.i = icmp ult i64 %a, %b
%..i = sext i1 %cmp1.i to i64
%retval.0.i = select i1 %cmp.i, i64 1, i64 %..i
store i64 %retval.0.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @store5(i64 %a, i64 %b) {
; CHECK-LABEL: store5:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ult i64 %a, %b
%not.cmp1.i = icmp ne i64 %a, %b
%..i = zext i1 %not.cmp1.i to i64
%retval.0.i = select i1 %cmp.i, i64 -1, i64 %..i
store i64 %retval.0.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
; FIXME: this is still done with compares, we may fix that in the future
define void @store6(i64 %a, i64 %b) {
; CHECK-LABEL: store6:
entry:
%cmp.i = icmp ult i64 %a, %b
%cmp1.i = icmp ugt i64 %a, %b
%..i = zext i1 %cmp1.i to i64
%retval.0.i = select i1 %cmp.i, i64 -1, i64 %..i
store i64 %retval.0.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @store7(i64 %a, i64 %b) {
; CHECK-LABEL: store7:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp eq i64 %a, %b
%cmp1.i = icmp ult i64 %a, %b
%phitmp.i = select i1 %cmp1.i, i64 -1, i64 1
%cond2.i = select i1 %cmp.i, i64 0, i64 %phitmp.i
store i64 %cond2.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @store8(i64 %a, i64 %b) {
; CHECK-LABEL: store8:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp eq i64 %a, %b
%cmp1.i = icmp ugt i64 %a, %b
%phitmp.i = select i1 %cmp1.i, i64 1, i64 -1
%cond2.i = select i1 %cmp.i, i64 0, i64 %phitmp.i
store i64 %cond2.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @store9(i64 %a, i64 %b) {
; CHECK-LABEL: store9:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ult i64 %a, %b
%not.cmp1.i = icmp ne i64 %a, %b
%phitmp.i = zext i1 %not.cmp1.i to i64
%cond2.i = select i1 %cmp.i, i64 -1, i64 %phitmp.i
store i64 %cond2.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
; FIXME: this is still done with compares, we may fix that in the future
define void @store10(i64 %a, i64 %b) {
; CHECK-LABEL: store10:
entry:
%cmp.i = icmp ult i64 %a, %b
%cmp1.i = icmp ugt i64 %a, %b
%phitmp.i = zext i1 %cmp1.i to i64
%cond2.i = select i1 %cmp.i, i64 -1, i64 %phitmp.i
store i64 %cond2.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @store11(i64 %a, i64 %b) {
; CHECK-LABEL: store11:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ugt i64 %a, %b
%not.cmp1.i = icmp ne i64 %a, %b
%phitmp.i = sext i1 %not.cmp1.i to i64
%cond2.i = select i1 %cmp.i, i64 1, i64 %phitmp.i
store i64 %cond2.i, i64* @ga, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @store12(i64 %a, i64 %b) {
; CHECK-LABEL: store12:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r6, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: sub r6, r3, r4
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: subfe r3, r3, r6
; CHECK-NEXT: std r3, 0(r5)
; CHECK-NEXT: blr
entry:
%cmp.i = icmp ugt i64 %a, %b
%cmp1.i = icmp ult i64 %a, %b
%phitmp.i = sext i1 %cmp1.i to i64
%cond2.i = select i1 %cmp.i, i64 1, i64 %phitmp.i
store i64 %cond2.i, i64* @ga, align 8
ret void
}

test/CodeGen/PowerPC/expand-isel.ll

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Linesif.end:
%conv3 = zext i1 %cmp to i32 %conv3 = zext i1 %cmp to i32
br label %cleanup br label %cleanup
cleanup: cleanup:
%retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ] %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ]
ret i32 %retval.0 ret i32 %retval.0
; CHECK-LABEL: @testComplexISEL ; CHECK-LABEL: @testComplexISEL
; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]] ; CHECK-DAG: [[LI:r[0-9]+]], 1
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-DAG: cmplwi [[LD:r[0-9]+]], 0
; CHECK-NEXT: [[TRUE]] ; CHECK: beq cr0, .LBB[[IFEND:[0-9_]+]]
; CHECK-NEXT: addi r3, r12, 0 ; CHECK: clrldi r3, [[LI]], 32
; CHECK-NEXT: [[SUCCESSOR]] ; CHECK-NEXT: blr
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK: .LBB[[IFEND]]:
; CHECK-NEXT: blr ; CHECK: xor [[XOR:r[0-9]+]]
; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
; CHECK: clrldi r3, [[SH]], 32
} }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}

test/CodeGen/PowerPC/i1-ext-fold.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define signext i32 @foo(i32 signext %a, i32 signext %b) #0 { define signext i32 @foo(i32 signext %a, i32 signext %b) #0 {
entry: entry:
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 4 %shl = shl nuw nsw i32 %conv, 4
ret i32 %shl ret i32 %shl
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
; CHECK-NO-ISEL-LABEL: @foo ; CHECK-NO-ISEL-LABEL: @foo
; CHECK-DAG: cmpw ; CHECK-DAG: subf [[REG1:[0-9]+]], 4, 3
; CHECK-DAG: li [[REG1:[0-9]+]], 0 ; CHECK-DAG: rldicl [[REG2:[0-9]+]], [[REG1]], 1, 63
; CHECK-DAG: li [[REG2:[0-9]+]], 16 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 4
; CHECK: isel 3, [[REG2]], [[REG1]],
; CHECK: blr ; CHECK: blr
; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 5, 0
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
; CHECK-NO-ISEL-NEXT: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define signext i32 @foo2(i32 signext %a, i32 signext %b) #0 { define signext i32 @foo2(i32 signext %a, i32 signext %b) #0 {
entry: entry:
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 4 %shl = shl nuw nsw i32 %conv, 4
Show All 19 Lines
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define signext i32 @foo3(i32 signext %a, i32 signext %b) #0 { define signext i32 @foo3(i32 signext %a, i32 signext %b) #0 {
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 4 %shl = shl nuw nsw i32 %conv, 4
ret i32 %shl ret i32 %shl
; CHECK-LABEL: @foo3 ; CHECK-ALL-LABEL: @foo3
; CHECK-NO-ISEL-LABEL: @foo3 ; CHECK-ALL: subf [[SUB:[0-9]+]], 3, 4
; CHECK-DAG: cmpw ; CHECK-ALL: rldicl [[SH:[0-9]+]], [[SUB]], 33, 63
; CHECK-DAG: li [[REG1:[0-9]+]], 16 ; CHECK-ALL: xori [[FLIP:[0-9]+]], [[SH]], 1
; CHECK: isel 3, 0, [[REG1]], ; CHECK-ALL: sldi 3, [[FLIP]], 4
; CHECK: blr ; CHECK-ALL: blr
; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 5, 0
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
; CHECK-NO-ISEL-NEXT: blr
} }
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

test/CodeGen/PowerPC/optcmp.ll

Show First 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
store i64 %shl, i64* %c, align 8 store i64 %shl, i64* %c, align 8
%cmp = icmp sgt i64 %shl, 0 %cmp = icmp sgt i64 %shl, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
; CHECK: @foo2l ; CHECK: @foo2l
; CHECK: sld. 4, 3, 4 ; CHECK: sld 4, 3, 4
; CHECK: std 4, 0(5) ; CHECK-NEXT: addi 3, 4, -1
; CHECK-NEXT: std 4, 0(5)
; CHECK-NEXT: nor 3, 3, 4
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: blr
} }
define double @food(double %a, double %b, double* nocapture %c) #0 { define double @food(double %a, double %b, double* nocapture %c) #0 {
entry: entry:
%sub = fsub double %a, %b %sub = fsub double %a, %b
store double %sub, double* %c, align 8 store double %sub, double* %c, align 8
%cmp = fcmp ogt double %a, %b %cmp = fcmp ogt double %a, %b
%cond = select i1 %cmp, double %a, double %b %cond = select i1 %cmp, double %a, double %b
Show All 35 Lines

test/CodeGen/PowerPC/ppc-crbits-onoff.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define signext i32 @crbitsoff(i32 signext %v1, i32 signext %v2) #0 { define signext i32 @crbitsoff(i32 signext %v1, i32 signext %v2) #0 {
entry: entry:
%tobool = icmp ne i32 %v1, 0 %tobool = icmp ne i32 %v1, 0
%lnot = icmp eq i32 %v2, 0 %lnot = icmp eq i32 %v2, 0
%and3 = and i1 %tobool, %lnot %and3 = and i1 %tobool, %lnot
%and = zext i1 %and3 to i32 %and = zext i1 %and3 to i32
ret i32 %and ret i32 %and
; CHECK-LABEL: @crbitsoff ; CHECK-ALL-LABEL: @crbitsoff
; CHECK-NO-ISEL-LABEL: @crbitsoff ; CHECK-ALL-DAG: cntlzw [[CNTv1:[0-9]+]], 3
; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0 ; CHECK-ALL-DAG: cntlzw [[CNTv2:[0-9]+]], 4
; CHECK-DAG: li [[REG2:[0-9]+]], 1 ; CHECK-ALL-DAG: srwi [[SH:[0-9]+]], [[CNTv1]], 5
; CHECK-DAG: cntlzw [[REG3:[0-9]+]], ; CHECK-ALL-DAG: xori [[FLIP:[0-9]+]], [[SH]], 1
; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]] ; CHECK-ALL-DAG: rlwinm [[SH2:[0-9]+]], [[CNTv2]], 27, 5, 31
; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]] ; CHECK-ALL: and 3, [[FLIP]], [[SH2]]
; CHECK-NO-ISEL: ori 4, 5, 0 ; CHECK-ALL: blr
; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 4, 0, 0
; CHECK: and 3, [[REG4]], [[REG3]]
; CHECK: blr
} }
define signext i32 @crbitson(i32 signext %v1, i32 signext %v2) #1 { define signext i32 @crbitson(i32 signext %v1, i32 signext %v2) #1 {
entry: entry:
%tobool = icmp ne i32 %v1, 0 %tobool = icmp ne i32 %v1, 0
%lnot = icmp eq i32 %v2, 0 %lnot = icmp eq i32 %v2, 0
%and3 = and i1 %tobool, %lnot %and3 = and i1 %tobool, %lnot
%and = zext i1 %and3 to i32 %and = zext i1 %and3 to i32
Show All 21 Lines

test/CodeGen/PowerPC/testComparesi32geu.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @fn1(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: fn1:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: li r4, 2
; CHECK-NEXT: clrlwi r3, r3, 24
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 1
; CHECK-NEXT: blr
entry:
%a.off = add i8 %a, -1
%switch = icmp ult i8 %a.off, 2
%. = select i1 %switch, i8 0, i8 2
ret i8 %.
}
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @fn2(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: fn2:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: li r4, 3
; CHECK-NEXT: clrlwi r3, r3, 24
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 1
; CHECK-NEXT: blr
entry:
%a.off = add i8 %a, -1
%switch = icmp ule i8 %a.off, 2
%. = select i1 %switch, i8 0, i8 2
ret i8 %.
}

test/CodeGen/PowerPC/testComparesi32gtu.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
%struct.tree_common = type { i8, [3 x i8] }
declare signext i32 @fn2(...) local_unnamed_addr #1
; Function Attrs: nounwind
define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
; CHECK-LABEL: testCompare1:
; CHECK: # BB#0: # %entry
; CHECK: lbz r3, 0(r3)
; CHECK-DAG: clrlwi r3, r3, 31
; CHECK-DAG: rldicl r3, r3, 0, 32
; CHECK: lbz r4, 0(r4)
; CHECK-DAG: clrlwi r4, r4, 31
; CHECK-DAG: rldicl r4, r4, 0, 32
; CHECK: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
entry:
%bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
%bf.clear = and i8 %bf.load, 1
%0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
%bf.load1 = load i8, i8* %0, align 4
%bf.clear2 = and i8 %bf.load1, 1
%cmp = icmp ugt i8 %bf.clear, %bf.clear2
%conv = zext i1 %cmp to i32
%call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
ret i32 undef
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2:
; CHECK: # BB#0: # %entry
; CHECK-DAG: rlwinm r3, r3, 0, 31, 31
; CHECK-DAG: rlwinm r4, r4, 0, 31, 31
; CHECK-DAG: rldicl r3, r3, 0, 32
; CHECK-DAG: rldicl r4, r4, 0, 32
; CHECK: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%and = and i32 %a, 1
%and1 = and i32 %b, 1
%cmp = icmp ugt i32 %and, %and1
%conv = zext i1 %cmp to i32
ret i32 %conv
}

test/CodeGen/PowerPC/testComparesi32leu.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%0 = and i8 %a, 1
%1 = and i8 %b, 1
%cmp = icmp ule i8 %0, %1
%conv3 = zext i1 %cmp to i32
ret i32 %conv3
}

test/CodeGen/PowerPC/testComparesi32ltu.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
%struct.tree_common = type { i8, [3 x i8] }
declare signext i32 @fn2(...) local_unnamed_addr #1
; Function Attrs: nounwind
define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
; CHECK-LABEL: testCompare1:
; CHECK: # BB#0: # %entry
; CHECK: lbz r3, 0(r3)
; CHECK-DAG: clrlwi r3, r3, 31
; CHECK-DAG: rldicl r3, r3, 0, 32
; CHECK: lbz r4, 0(r4)
; CHECK-DAG: clrlwi r4, r4, 31
; CHECK-DAG: rldicl r4, r4, 0, 32
; CHECK: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
entry:
%bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
%bf.clear = and i8 %bf.load, 1
%0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %arg1, i64 0, i32 0
%bf.load1 = load i8, i8* %0, align 4
%bf.clear2 = and i8 %bf.load1, 1
%cmp = icmp ult i8 %bf.clear, %bf.clear2
%conv = zext i1 %cmp to i32
%call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
ret i32 undef
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2:
; CHECK: # BB#0: # %entry
; CHECK-DAG: rlwinm r3, r3, 0, 31, 31
; CHECK-DAG: rlwinm r4, r4, 0, 31, 31
; CHECK-DAG: rldicl r3, r3, 0, 32
; CHECK-DAG: rldicl r4, r4, 0, 32
; CHECK: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%and = and i32 %a, 1
%and1 = and i32 %b, 1
%cmp = icmp ult i32 %and, %and1
%conv = zext i1 %cmp to i32
ret i32 %conv
}

test/CodeGen/PowerPC/testComparesieqsc.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsc.c'
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc_z(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ieqsc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_ieqsc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesieqsi.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsi.c'
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsi_z(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ieqsi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_ieqsi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesieqsll.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqsll.c'
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsll_z(i64 %a) {
; CHECK-LABEL: test_ieqsll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqsll_sext_z(i64 %a) {
; CHECK-LABEL: test_ieqsll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_ieqsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ieqsll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsll_z_store(i64 %a) {
; CHECK-LABEL: test_ieqsll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ieqsll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesieqss.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqss.c'
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss_z(i16 signext %a) {
; CHECK-LABEL: test_ieqss_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_ieqss_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_ieqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesiequc.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequc.c'
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc_z(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesiequi.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequi.c'
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi_z(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequi_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequi_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesiequll.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequll.c'
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll_z(i64 %a) {
; CHECK-LABEL: test_iequll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll_sext_z(i64 %a) {
; CHECK-LABEL: test_iequll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_iequll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequll_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesiequs.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequs.c'
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs_z(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesigesc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_igesc_z(i8 signext %a) {
; CHECK-LABEL: test_igesc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, -1
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_igesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_igesc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, -1
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_igesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_igesc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rlwinm r3, r3, 25, 31, 31
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, -1
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_igesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_igesc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: srwi r3, r3, 7
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, -1
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesigesi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_igesi_z(i32 signext %a) {
; CHECK-LABEL: test_igesi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, -1
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_igesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_igesi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, -1
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_igesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_igesi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, -1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_igesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_igesi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, -1
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesigesll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_igesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_igesll_z(i64 %a) {
; CHECK-LABEL: test_igesll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_igesll_sext_z(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi r6, r3, 63
; CHECK: subfc r3, r4, r3
; CHECK: rldicl r3, r4, 1, 63
; CHECK: adde r3, r6, r3
; CHECK: std r3
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_igesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_igesll_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_igesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: std r3,
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesigess.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_igess_z(i16 signext %a) {
; CHECK-LABEL: test_igess_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, -1
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_igess_sext_z(i16 signext %a) {
; CHECK-LABEL: test_igess_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, -1
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_igess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_igess_z_store(i16 signext %a) {
; CHECK-LABEL: test_igess_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rlwinm r3, r3, 17, 31, 31
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, -1
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_igess_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_igess_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: srwi r3, r3, 15
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, -1
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesigeuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp uge i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
; CHECK-LABEL: test_igeuc:
; CHECK: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp uge i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_igeuc_sext
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_z(i8 zeroext %a) {
entry:
%cmp = icmp uge i8 %a, 0
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
; CHECK-LABEL: @test_igeuc_z
; CHECK: li r3, 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
entry:
%cmp = icmp uge i8 %a, 0
%conv2 = sext i1 %cmp to i32
ret i32 %conv2
; CHECK-LABEL: @test_igeuc_sext_z
; CHECK: li r3, -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK_LABEL: test_igeuc_store:
; CHECK: clrldi r3, r3, 32
; CHECK: clrldi r4, r4, 32
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK-TBD-LABEL: @test_igeuc_sext_store
; CHECK-TBD: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-TBD: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-TBD: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-TBD: stb [[REG3]]
; CHECK-TBD: blr
}
; Function Attrs : norecurse nounwind
define void @test_igeuc_z_store(i8 zeroext %a) {
entry:
%cmp = icmp uge i8 %a, 0
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK-LABEL: @test_igeuc_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: stb [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeuc_sext_z_store(i8 zeroext %a) {
entry:
%cmp = icmp uge i8 %a, 0
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK-LABEL: @test_igeuc_sext_z_store
; CHECK: li [[REG1:r[0-9]+]], 255
; CHECK: stb [[REG1]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesigeui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
; CHECK-LABEL: test_igeui:
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_igeui_sext
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_z(i32 zeroext %a) {
entry:
%cmp = icmp uge i32 %a, 0
%sub = zext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_igeui_z
; CHECK: li r3, 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_sext_z(i32 zeroext %a) {
entry:
%cmp = icmp uge i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_igeui_sext_z
; CHECK: li r3, -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob
ret void
; CHECK_LABEL: test_igeuc_store:
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: @test_igeui_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: stw [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeui_z_store(i32 zeroext %a) {
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = zext i1 %cmp to i32
store i32 %conv1, i32* @glob
ret void
; CHECK-LABEL: @test_igeui_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: stw [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeui_sext_z_store(i32 zeroext %a) {
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = sext i1 %cmp to i32
store i32 %conv1, i32* @glob
ret void
; CHECK-LABEL: @test_igeui_sext_z_store
; CHECK: li [[REG1:r[0-9]+]], -1
; CHECK: stw [[REG1]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesigeull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
; CHECK-LABEL: test_igeull:
; CHECK: subfc {{r[0-9]+}}, r4, r3
; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
; CHECK-NEXT: addi r3, [[REG1]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_igeull_sext
; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not r3, [[REG2]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_z(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%sub = zext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_igeull_z
; CHECK: li r3, 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_sext_z(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_igeull_sext_z
; CHECK: li r3, -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeull_store(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: test_igeull_store:
; CHECK: subfc {{r[0-9]+}}, r4, r3
; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeull_sext_store(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_igeull_sext_store
; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
; CHECK: std [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeull_z_store(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_igeull_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: std [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeull_sext_z_store(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_igeull_sext_z_store
; CHECK: li [[REG1:r[0-9]+]], -1
; CHECK: std [[REG1]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesigeus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
; CHECK-LABEL: test_igeus:
; CHECK: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_igeus_sext
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_z(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
; CHECK-LABEL: @test_igeus_z
; CHECK: li r3, 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_sext_z(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
; CHECK-LABEL: @test_igeus_sext_z
; CHECK: li r3, 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK_LABEL: test_igeus_store:
; CHECK: clrldi r3, r3, 32
; CHECK: clrldi r4, r4, 32
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK-LABEL: @test_igeus_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: sth [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeus_z_store(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK-LABEL: @test_igeus_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: sth [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeus_sext_z_store(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK-LABEL: @test_igeus_sext_z_store
; CHECK: lis [[REG1:r[0-9]+]], 0
; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
; CHECK: sth [[REG2]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesigtsc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; FIXME
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsc_z(i8 signext %a) {
; CHECK-LABEL: test_igtsc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_igtsc_sext_z:
; CHECK: neg [[REG2:r[0-9]+]], r3
; CHECK-NEXT: sradi r3, [[REG2]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp sgt i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; FIXME
; Function Attrs: norecurse nounwind
define void @test_igtsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_igtsc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_igtsc_sext_z_store:
; CHECK: neg [[REG2:r[0-9]+]], r3
; CHECK: sradi {{r[0-9]+}}, [[REG2]], 63
entry:
%cmp = icmp sgt i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesigtsi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; FIXME
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsi_z(i32 signext %a) {
; CHECK-LABEL: test_igtsi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_igtsi_sext_z:
; CHECK: neg [[REG2:r[0-9]+]], r3
; CHECK-NEXT: sradi r3, [[REG2]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; FIXME
; Function Attrs: norecurse nounwind
define void @test_igtsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_igtsi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_igtsi_sext_z_store:
; CHECK: neg [[REG:r[0-9]+]], r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesigtsll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: xori r3, [[REG4]], 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK-NEXT: neg r3, [[REG5]]
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; FIXME
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll_z(i64 %a) {
; CHECK-LABEL: test_igtsll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: nor r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll_sext_z(i64 %a) {
; CHECK-LABEL: test_igtsll_sext_z:
; CHECK: addi [[REG1:r[0-9]+]], r3, -1
; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3
; CHECK-NEXT: sradi r3, [[REG2]], 63
entry:
%cmp = icmp sgt i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_igtsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK-NOT: neg
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; FIXME
; Function Attrs: norecurse nounwind
define void @test_igtsll_z_store(i64 %a) {
; CHECK-LABEL: test_igtsll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igtsll_sext_z_store:
; CHECK: addi [[REG1:r[0-9]+]], r3, -1
; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3
; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63
entry:
%cmp = icmp sgt i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesigtss.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG1]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; FIXME
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtss_z(i16 signext %a) {
; CHECK-LABEL: test_igtss_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_igtss_sext_z:
; CHECK: # BB#0: # %entry
; CHECK: neg [[REG2:r[0-9]+]], r3
; CHECK-NEXT: sradi r3, [[REG2]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_igtss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 1, 63
entry:
%cmp = icmp sgt i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; FIXME
; Function Attrs: norecurse nounwind
define void @test_igtss_z_store(i16 signext %a) {
; CHECK-LABEL: test_igtss_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_igtss_sext_z_store:
; CHECK: neg [[REG2:r[0-9]+]], r3
; CHECK: sradi {{r[0-9]+}}, [[REG2]], 63
entry:
%cmp = icmp sgt i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesigtuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_igtuc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_igtuc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc_store:
; CHECK: # BB#0: # %entry
; CHECK: clrldi r4, r4, 32
; CHECK: clrldi r3, r3, 32
; CHECK: sub [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_igtuc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_igtuc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesigtui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui_z(i32 zeroext %a) {
; CHECK-LABEL: test_igtui_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_igtui_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui_store:
; CHECK: # BB#0: # %entry
; CHECK-NOT: clrldi r3, r3, 32
; CHECK: sub [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NOT: clrldi r3, r3, 32
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ugt i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_igtui_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_igtui_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesigtull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtull(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtull:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NEXT: neg r3, [[REG2]]
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtull_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: subfe r3, [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtull_z(i64 %a) {
; CHECK-LABEL: test_igtull_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtull_sext_z(i64 %a) {
; CHECK-LABEL: test_igtull_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_igtull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtull_store:
; CHECK: # BB#0: # %entry
; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NEXT: neg {{r[0-9]+}}, [[REG2]]
; CHECK: blr
entry:
%cmp = icmp ugt i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtull_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NOT: neg
; CHECK: blr
entry:
%cmp = icmp ugt i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtull_z_store(i64 %a) {
; CHECK-LABEL: test_igtull_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igtull_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesigtus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus_z(i16 zeroext %a) {
; CHECK-LABEL: test_igtus_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_igtus_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus_store:
; CHECK: # BB#0: # %entry
; CHECK: clrldi r4, r4, 32
; CHECK: clrldi r3, r3, 32
; CHECK: sub [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
; CHECK: blr
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
; CHECK: blr
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_igtus_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_igtus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_igtus_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesilesc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ilesc_z(i8 signext %a) {
; CHECK-LABEL: test_ilesc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 1
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_ilesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_ilesc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 1
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_ilesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_ilesc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 1
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
define void @test_ilesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_ilesc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 1
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesilesi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ilesi_z(i32 signext %a) {
; CHECK-LABEL: test_ilesi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 1
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ilesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_ilesi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 1
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_ilesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_ilesi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_ilesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_ilesi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 1
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesilesll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_ilesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r12, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r12, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ilesll_z(i64 %a) {
; CHECK-LABEL: test_ilesll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ilesll_sext_z(i64 %a) {
; CHECK-LABEL: test_ilesll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi r6, r4, 63
; CHECK: subfc r4, r3, r4
; CHECK: rldicl r3, r3, 1, 63
; CHECK: adde r3, r6, r3
; CHECK: std r3,
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_ilesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi r6, r4, 63
; CHECK-DAG: rldicl r3, r3, 1, 63
; CHECK-DAG: subfc r4, r3, r4
; CHECK: adde r3, r6, r3
; CHECK: neg r3, r3
; CHECK: std r3,
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_ilesll_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_ilesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesiless.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_iless_z(i16 signext %a) {
; CHECK-LABEL: test_iless_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 1
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_iless_sext_z(i16 signext %a) {
; CHECK-LABEL: test_iless_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 1
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_iless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_iless_z_store(i16 signext %a) {
; CHECK-LABEL: test_iless_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 1
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
define void @test_iless_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_iless_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 1
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesileuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp ule i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
; CHECK-LABEL: test_ileuc:
; CHECK: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp ule i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_ileuc_sext
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_z(i8 zeroext %a) {
entry:
%cmp = icmp eq i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
; CHECK-LABEL: test_ileuc_z:
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi r3, [[REG1]], 5
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
entry:
%cmp = icmp ule i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_ileuc_sext_z
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK-LABEL: test_ileuc_store:
; CHECK: clrldi r4, r4, 32
; CHECK: clrldi r3, r3, 32
; CHECK: sub [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK-LABEL: @test_ileuc_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: stb [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileuc_z_store(i8 zeroext %a) {
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob
ret void
; CHECK-LABEL: test_ileuc_z_store:
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileuc_sext_z_store(i8 zeroext %a) {
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob
ret void
; CHECK-LABEL: @test_ileuc_sext_z_store
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK: stb [[REG4]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesileui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp ule i32 %a, %b
%sub = zext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: test_ileui:
; CHECK: sub [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_ileui_sext
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_z(i32 zeroext %a) {
entry:
%cmp = icmp eq i32 %a, 0
%sub = zext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: test_ileui_z:
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi r3, [[REG1]], 5
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_sext_z(i32 zeroext %a) {
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_ileui_sext_z
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK-NEXT: sradi r3, [[REG3]], 63
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp ule i32 %a, %b
%sub = zext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: test_ileui_store:
; CHECK: sub [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: @test_ileui_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: stw [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileui_z_store(i32 zeroext %a) {
entry:
%cmp = icmp eq i32 %a, 0
%sub = zext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: test_ileui_z_store:
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileui_sext_z_store(i32 zeroext %a) {
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: @test_ileui_sext_z_store
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK: stw [[REG4]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesileull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull(i64 %a, i64 %b) {
entry:
%cmp = icmp ule i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
; CHECK-LABEL: test_ileull:
; CHECK: subfc {{r[0-9]+}}, r3, r4
; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
; CHECK-NEXT: addi r3, [[REG1]], 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
entry:
%cmp = icmp ule i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_ileull_sext
; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not r3, [[REG2]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_z(i64 %a) {
entry:
%cmp = icmp ule i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
; CHECK-LABEL: test_ileull_z
; CHECK: cntlzd [[REG1:r[0-9]+]], r3
; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_sext_z(i64 %a) {
entry:
%cmp = icmp ule i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_ileull_sext_z
; CHECK: addic [[REG1:r[0-9]+]], r3, -1
; CHECK: subfe r3, [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileull_store(i64 %a, i64 %b) {
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: test_ileull_store:
; CHECK: subfc {{r[0-9]+}}, r3, r4
; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileull_sext_store(i64 %a, i64 %b) {
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_ileull_sext_store
; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
; CHECK: std [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileull_z_store(i64 %a) {
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: test_ileull_z_store:
; CHECK: cntlzd [[REG1:r[0-9]+]], r3
; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileull_sext_z_store(i64 %a) {
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_ileull_sext_z_store
; CHECK: addic [[REG1:r[0-9]+]], r3, -1
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: std [[REG2]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesileus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp ule i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
; CHECK-LABEL: test_ileus:
; CHECK: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp ule i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_ileus_sext
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_z(i16 zeroext %a) {
entry:
%cmp = icmp ule i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
; CHECK-LABEL: test_ileus_z:
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi r3, [[REG1]], 5
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_sext_z(i16 zeroext %a) {
entry:
%cmp = icmp ule i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
; CHECK-LABEL: @test_ileus_sext_z
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK-LABEL: test_ileus_store:
; CHECK: clrldi r4, r4, 32
; CHECK: clrldi r3, r3, 32
; CHECK: sub [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK-LABEL: @test_ileus_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: sth [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileus_z_store(i16 zeroext %a) {
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob
ret void
; CHECK-LABEL: test_ileus_z_store:
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileus_sext_z_store(i16 zeroext %a) {
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob
ret void
; CHECK-LABEL: @test_ileus_sext_z_store
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK: sth [[REG4]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesiltsc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_iltsc_sext_z:
; CHECK: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_iltsc_sext_z_store:
; CHECK: srwi {{r[0-9]+}}, r3, 7
entry:
%cmp = icmp slt i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesiltsi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_iltsi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_iltsi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_iltsi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_iltsi_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_iltsi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp slt i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_iltsi_sext_z_store:
; CHECK: srawi {{r[0-9]+}}, r3, 31
; CHECK: blr
entry:
%cmp = icmp slt i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesiltsll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: xori r3, [[REG4]], 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK-NEXT: neg r3, [[REG5]]
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsll_sext_z(i64 %a) {
; CHECK-LABEL: test_iltsll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_iltsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK-NOT: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_iltsll_sext_z_store:
; CHECK: sradi r3, r3, 63
entry:
%cmp = icmp slt i64 %a, 0
%conv2 = sext i1 %cmp to i64
store i64 %conv2, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesiltss.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iltss:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iltss_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_iltss_sext_z:
; CHECK: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind
define void @test_iltss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iltss_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp slt i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iltss_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp slt i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_iltss_sext_z_store:
; CHECK: srwi {{r[0-9]+}}, r3, 15
entry:
%cmp = icmp slt i16 %a, 0
%sub = sext i1 %cmp to i16
store i16 %sub, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesiltuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iltuc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iltuc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_iltuc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i32 0
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_iltuc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i32 0
}
; Function Attrs: norecurse nounwind
define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iltuc_store:
; CHECK: # BB#0: # %entry
; CHECK: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK: sub [[REG:r[2-9]+]], r3, r4
; CHECK-NEXT: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iltuc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iltuc_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: stb [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i8 0, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iltuc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: stb [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i8 0, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesiltui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iltui:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iltui_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltui_z(i32 zeroext %a) {
; CHECK-LABEL: test_iltui_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i32 0
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_iltui_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i32 0
}
; Function Attrs: norecurse nounwind
define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iltui_store:
; CHECK: # BB#0: # %entry
; CHECK: sub [[REG:r[2-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iltui_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ult i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iltui_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: stw [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i32 0, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iltui_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: stw [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i32 0, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesiltull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltull(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltull:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc [[REG:r[1-9]+]], r4, r3
; CHECK-NEXT: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NEXT: neg r3, [[REG2]]
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltull_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: subfe r3, [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltull_z(i64 %a) {
; CHECK-LABEL: test_iltull_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i32 0
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltull_sext_z(i64 %a) {
; CHECK-LABEL: test_iltull_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i32 0
}
; Function Attrs: norecurse nounwind
define void @test_iltull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltull_store:
; CHECK: # BB#0: # %entry
; CHECK: subfc [[REG:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NEXT: neg {{r[0-9]+}}, [[REG2]]
entry:
%cmp = icmp ult i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltull_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subfc [[REG:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NOT: neg
entry:
%cmp = icmp ult i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltull_z_store(i64 %a) {
; CHECK-LABEL: test_iltull_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: std [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i64 0, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_iltull_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: std [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i64 0, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesiltus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iltus:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iltus_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltus_z(i16 zeroext %a) {
; CHECK-LABEL: test_iltus_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i32 0
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_iltus_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i32 0
}
; Function Attrs: norecurse nounwind
define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iltus_store:
; CHECK: # BB#0: # %entry
; CHECK: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK: sub [[REG:r[2-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iltus_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iltus_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: sth [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i16 0, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_iltus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iltus_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: sth [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i16 0, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesinesc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_inesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_inesc_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_inesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_inesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_store:
; CHECK: # BB#0: # %entry
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_inesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_inesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_z_store:
; CHECK: # BB#0: # %entry
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
define void @test_inesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_inesc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesinesi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_inesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_inesi_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_inesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_inesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_inesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_inesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_inesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_inesi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesinesll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_inesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_inesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_inesll_z(i64 %a) {
; CHECK-LABEL: test_inesll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_inesll_sext_z(i64 %a) {
; CHECK-LABEL: test_inesll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_inesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_inesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_inesll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_inesll_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_inesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_inesll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesiness.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_iness(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_iness_z(i16 signext %a) {
; CHECK-LABEL: test_iness_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_iness_sext_z(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_iness_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_store:
; CHECK: # BB#0: # %entry
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_iness_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iness_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_iness_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_z_store:
; CHECK: # BB#0: # %entry
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
define void @test_iness_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_iness_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesineuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ineuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ineuc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_ineuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
define void @test_ineuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ineuc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesineui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ineui_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ineui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ineui_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_ineui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_ineui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ineui_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesineull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define signext i32 @test_ineull(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ineull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ineull_z(i64 %a) {
; CHECK-LABEL: test_ineull_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define signext i32 @test_ineull_sext_z(i64 %a) {
; CHECK-LABEL: test_ineull_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ineull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_ineull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ineull_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_ineull_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_ineull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ineull_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesineus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
}
define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define signext i32 @test_ineus_z(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
}
define signext i32 @test_ineus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
}
define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ineus_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_ineus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
define void @test_ineus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ineus_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testCompareslleqsc.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c'
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsc_z(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind
define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lleqsc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_lleqsc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testCompareslleqsi.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsi_z(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lleqsi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_lleqsi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testCompareslleqsll.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll_z(i64 %a) {
; CHECK-LABEL: test_lleqsll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll_sext_z(i64 %a) {
; CHECK-LABEL: test_lleqsll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_lleqsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsll_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testCompareslleqss.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss_z(i16 signext %a) {
; CHECK-LABEL: test_lleqss_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_lleqss_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind
define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_lleqss_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_lleqss_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesllequc.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequc_z(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind
define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llequc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llequc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesllequi.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequi_z(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequi_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llequi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequi_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequi_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llequi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllequll.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequll_z(i64 %a) {
; CHECK-LABEL: test_llequll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequll_sext_z(i64 %a) {
; CHECK-LABEL: test_llequll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_llequll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llequll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequll_z_store(i64 %a) {
; CHECK-LABEL: test_llequll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llequll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesllequs.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequs_z(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llequs_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind
define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llequs_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llequs_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: sldi r3, r3, 63
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesllgesc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgesc_z(i8 signext %a) {
; CHECK-LABEL: test_llgesc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, -1
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_llgesc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, -1
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_llgesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_llgesc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rlwinm r3, r3, 25, 31, 31
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, -1
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_llgesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_llgesc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: srwi r3, r3, 7
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, -1
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesllgesi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llgesi_z(i32 signext %a) {
; CHECK-LABEL: test_llgesi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, -1
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llgesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_llgesi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, -1
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_llgesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_llgesi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, -1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_llgesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_llgesi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, -1
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllgesll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llgesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llgesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llgesll_z(i64 %a) {
; CHECK-LABEL: test_llgesll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llgesll_sext_z(i64 %a) {
; CHECK-LABEL: test_llgesll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llgesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi r6, r3, 63
; CHECK: subfc r3, r4, r3
; CHECK: rldicl r3, r4, 1, 63
; CHECK: adde r3, r6, r3
; CHECK: std r3,
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llgesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: rldicl r3, r4, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llgesll_z_store(i64 %a) {
; CHECK-LABEL: test_llgesll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llgesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llgesll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, -1
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesllgess.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llgess(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgess_z(i16 signext %a) {
; CHECK-LABEL: test_llgess_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, -1
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llgess_sext_z(i16 signext %a) {
; CHECK-LABEL: test_llgess_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, -1
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define void @test_llgess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llgess_z_store(i16 signext %a) {
; CHECK-LABEL: test_llgess_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rlwinm r3, r3, 17, 31, 31
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, -1
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llgess_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_llgess_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: srwi r3, r3, 15
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, -1
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesllgeuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: test_llgeuc:
; CHECK: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub [[REG1:r[0-9]+]], r3, r4
jtonyUnsubmitted
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I noticed that in some test cases we use generic registers (like here [[REG1]] ), and in some other test cases, we use the specific register (like r4,r5), I know this is caused by this patch are created by multiple people. But I think maybe it is worthwhile to use one format for all ? ( I personally prefer the auto generated one, but I am OK with both, as long as they are consistent)

jtony: I noticed that in some test cases we use generic registers (like here [[REG1]] ), and in some…
jtonyUnsubmitted
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I maybe not be clear enough, What I mean here is some test cases use generic names [[REG1:r[0-9]+]] (like this file testComparesllgeuc.ll), while the others just use whatever generated, like the setcc eqtest/CodeGen/PowerPC/testComparesieqsc.ll, there is no [[REG:r[0-9]+]] at all.

jtony: I maybe not be clear enough, What I mean here is some test cases use generic names [[REG1:r[0…
sfertileUnsubmitted
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When writing these tests we want to use a specific register for the places where the abi dictates what register must be used, and variables for all other registers. For example in the next test (@test_llgeuc_sext):

subf [[REG1:r[0-9]+]], r4, r3 --> %a must be in register r3, and %b must be in register r4. The subf instruction isn't constrained to putting the result into a specific register so we shouldn't make any assumptions about which register it goes into as long as that result is used as the second operand of the rldicl instruction.

sfertile: When writing these tests we want to use a specific register for the places where the abi…
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc_sext(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: @test_llgeuc_sext
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc_z(i8 zeroext %a) {
entry:
%cmp = icmp uge i8 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeuc_z
; CHECK: li r3, 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc_sext_z(i8 zeroext %a) {
entry:
%cmp = icmp uge i8 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeuc_sext_z
; CHECK: li r3, -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK_LABEL: test_llgeuc_store:
; CHECK: clrldi r3, r3, 32
; CHECK: clrldi r4, r4, 32
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK-LABEL: @test_llgeuc_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: stb [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeuc_z_store(i8 zeroext %a) {
entry:
%cmp = icmp uge i8 %a, 0
%conv1 = zext i1 %cmp to i8
store i8 %conv1, i8* @glob
ret void
; CHECK-LABEL: @test_llgeuc_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: stb [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeuc_sext_z_store(i8 zeroext %a) {
entry:
%cmp = icmp uge i8 %a, 0
%conv1 = sext i1 %cmp to i8
store i8 %conv1, i8* @glob
ret void
; CHECK-LABEL: @test_llgeuc_sext_z_store
; CHECK: li [[REG1:r[0-9]+]], 255
; CHECK: stb [[REG1]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesllgeui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp uge i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: test_llgeui:
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp uge i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeui_sext
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_z(i32 zeroext %a) {
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeui_z
; CHECK: li r3, 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_sext_z(i32 zeroext %a) {
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeui_sext_z
; CHECK: li r3, -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob
ret void
; CHECK_LABEL: test_igeuc_store:
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: @test_llgeui_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: stw [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_z_store(i32 zeroext %a) {
entry:
%cmp = icmp uge i32 %a, 0
%sub = zext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: @test_llgeui_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: stw [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_sext_z_store(i32 zeroext %a) {
entry:
%cmp = icmp uge i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: @test_llgeui_sext_z_store
; CHECK: li [[REG1:r[0-9]+]], -1
; CHECK: stw [[REG1]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesllgeull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: test_llgeull:
; CHECK: subfc {{r[0-9]+}}, r4, r3
; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
; CHECK-NEXT: addi r3, [[REG1]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_sext(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeull_sext
; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_z(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeull_z
; CHECK: li r3, 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_sext_z(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeull_sext_z
; CHECK: li r3, -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_store(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: test_llgeull_store:
; CHECK: subfc {{r[0-9]+}}, r4, r3
; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_sext_store(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_llgeull_sext_store
; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
; CHECK: std [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_z_store(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_llgeull_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: std [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_sext_z_store(i64 %a) {
entry:
store i64 -1, i64* @glob
ret void
; CHECK-LABEL: @test_llgeull_sext_z_store
; CHECK: li [[REG1:r[0-9]+]], -1
; CHECK: std [[REG1]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesllgeus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: test_llgeus:
; CHECK: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: @test_llgeus_sext
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_z(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeus_z
; CHECK: li r3, 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_sext_z(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeus_sext_z
; CHECK: li r3, -1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK_LABEL: test_llgeus_store:
; CHECK: clrldi r3, r3, 32
; CHECK: clrldi r4, r4, 32
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK-LABEL: @test_llgeus_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: sth [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_z_store(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = zext i1 %cmp to i16
store i16 %conv1, i16* @glob
ret void
; CHECK-LABEL: @test_llgeus_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: sth [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_sext_z_store(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = sext i1 %cmp to i16
store i16 %conv1, i16* @glob
ret void
; CHECK-LABEL: @test_llgeus_sext_z_store
; CHECK: lis [[REG1:r[0-9]+]], 0
; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
; CHECK: sth [[REG2]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesllgtsc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgtsc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG1]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgtsc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; FIXME
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsc_z(i8 signext %a) {
; CHECK-LABEL: test_llgtsc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_llgtsc_sext_z:
; CHECK: neg [[REG:r[0-9]+]], r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind
define void @test_llgtsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgtsc_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 1, 63
entry:
%cmp = icmp sgt i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgtsc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; FIXME
; Function Attrs: norecurse nounwind
define void @test_llgtsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_llgtsc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_llgtsc_sext_z_store:
; CHECK: neg [[REG:r[0-9]+]], r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesllgtsi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgtsi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG1]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgtsi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; FIXME
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsi_z(i32 signext %a) {
; CHECK-LABEL: test_llgtsi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_llgtsi_sext_z:
; CHECK: neg [[REG:r[0-9]+]], r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_llgtsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgtsi_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 1, 63
entry:
%cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgtsi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; FIXME
; Function Attrs: norecurse nounwind
define void @test_llgtsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_llgtsi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_llgtsi_sext_z_store:
; CHECK: neg [[REG:r[0-9]+]], r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllgtsll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: xori r3, [[REG4]], 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK-NEXT: neg r3, [[REG5]]
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; FIXME
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll_z(i64 %a) {
; CHECK-LABEL: test_llgtsll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: nor r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll_sext_z(i64 %a) {
; CHECK-LABEL: test_llgtsll_sext_z:
; CHECK: addi [[REG1:r[0-9]+]], r3, -1
; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3
; CHECK-NEXT: sradi r3, [[REG2]], 63
entry:
%cmp = icmp sgt i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_llgtsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK-NOT: neg
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; FIXME
; Function Attrs: norecurse nounwind
define void @test_llgtsll_z_store(i64 %a) {
; CHECK-LABEL: test_llgtsll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llgtsll_sext_z_store:
; CHECK: addi [[REG1:r[0-9]+]], r3, -1
; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3
; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63
entry:
%cmp = icmp sgt i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesllgtss.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgtss:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG1]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgtss_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; FIXME
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtss_z(i16 signext %a) {
; CHECK-LABEL: test_llgtss_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_llgtss_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg [[REG:r[0-9]+]], r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind
define void @test_llgtss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgtss_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 1, 63
entry:
%cmp = icmp sgt i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgtss_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; FIXME
; Function Attrs: norecurse nounwind
define void @test_llgtss_z_store(i16 signext %a) {
; CHECK-LABEL: test_llgtss_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_llgtss_sext_z_store:
; CHECK: neg [[REG:r[0-9]+]], r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp sgt i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesllgtuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_llgtuc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_llgtuc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind
define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc_store:
; CHECK: # BB#0: # %entry
; CHECK: clrldi r4, r4, 32
; CHECK: clrldi r3, r3, 32
; CHECK: sub [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llgtuc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llgtuc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesllgtui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui:
; CHECK: # BB#0: # %entry
; CHECK-NOT: clrldi
; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
entry:
%cmp = icmp ugt i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui_z(i32 zeroext %a) {
; CHECK-LABEL: test_llgtui_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_llgtui_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui_store:
; CHECK: # BB#0: # %entry
; CHECK-NOT: clrldi
; CHECK: sub [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ugt i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llgtui_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llgtui_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllgtull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtull:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NEXT: neg r3, [[REG2]]
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtull_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: subfe r3, [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtull_z(i64 %a) {
; CHECK-LABEL: test_llgtull_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtull_sext_z(i64 %a) {
; CHECK-LABEL: test_llgtull_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_llgtull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtull_store:
; CHECK: # BB#0: # %entry
; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NEXT: neg {{r[0-9]+}}, [[REG2]]
entry:
%cmp = icmp ugt i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtull_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NOT: neg
entry:
%cmp = icmp ugt i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtull_z_store(i64 %a) {
; CHECK-LABEL: test_llgtull_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llgtull_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesllgtus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtus_z(i16 zeroext %a) {
; CHECK-LABEL: test_llgtus_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_llgtus_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
; Function Attrs: norecurse nounwind
define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus_store:
; CHECK: # BB#0: # %entry
; CHECK: clrldi r4, r4, 32
; CHECK: clrldi r3, r3, 32
; CHECK: sub [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llgtus_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llgtus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llgtus_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testCompareslllesc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_lllesc_z(i8 signext %a) {
; CHECK-LABEL: test_lllesc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 1
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
define i64 @test_lllesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_lllesc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 1
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_lllesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_lllesc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 1
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
define void @test_lllesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_lllesc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 1
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testCompareslllesi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_lllesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_lllesi_z(i32 signext %a) {
; CHECK-LABEL: test_lllesi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 1
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_lllesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_lllesi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 1
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_lllesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_lllesi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_lllesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_lllesi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 1
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testCompareslllesll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r12, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r12, r3, r4
; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll_z(i64 %a) {
; CHECK-LABEL: test_lllesll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll_sext_z(i64 %a) {
; CHECK-LABEL: test_lllesll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_lllesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi r6, r4, 63
; CHECK: subfc r4, r3, r4
; CHECK: rldicl r3, r3, 1, 63
; CHECK: adde r3, r6, r3
; CHECK: std r3,
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lllesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi r6, r4, 63
; CHECK-DAG: rldicl r3, r3, 1, 63
; CHECK-DAG: subfc r4, r3, r4
; CHECK: adde r3, r6, r3
; CHECK: neg r3, r3
; CHECK: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lllesll_z_store(i64 %a) {
; CHECK-LABEL: test_lllesll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lllesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_lllesll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 1
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesllless.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llless(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llless_z(i16 signext %a) {
; CHECK-LABEL: test_llless_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 1
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
define i64 @test_llless_sext_z(i16 signext %a) {
; CHECK-LABEL: test_llless_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 1
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
define void @test_llless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llless_z_store(i16 signext %a) {
; CHECK-LABEL: test_llless_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 1
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
define void @test_llless_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_llless_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 1
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesllleuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: test_llleuc:
; CHECK: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc_sext(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: @test_llleuc_sext
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc_z(i8 zeroext %a) {
entry:
%cmp = icmp ule i8 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
; CHECK-LABEL: test_llleuc_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc_sext_z(i8 zeroext %a) {
entry:
%cmp = icmp ule i8 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
; CHECK-LABEL: @test_llleuc_sext_z
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK-LABEL: test_llleuc_store:
; CHECK: clrldi r4, r4, 32
; CHECK: clrldi r3, r3, 32
; CHECK: sub [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK-LABEL: @test_llleuc_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: stb [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleuc_z_store(i8 zeroext %a) {
entry:
%cmp = icmp ule i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob
ret void
; CHECK-LABEL: test_llleuc_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi {{r[0-9]}}, r3, 5
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleuc_sext_z_store(i8 zeroext %a) {
entry:
%cmp = icmp ule i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob
ret void
; CHECK-LABEL: @test_llleuc_sext_z_store
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK: stb [[REG4]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesllleui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp ule i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: test_llleui:
; CHECK: sub [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui_sext(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp ule i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llleui_sext
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui_z(i32 zeroext %a) {
entry:
%cmp = icmp ule i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: test_llleui_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui_sext_z(i32 zeroext %a) {
entry:
%cmp = icmp ule i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llleui_sext_z
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK-NEXT: sradi r3, [[REG3]], 63
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp ule i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob
ret void
; CHECK-LABEL: test_llleui_store:
; CHECK: sub [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) {
entry:
%cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: @test_llleui_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: stw [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleui_z_store(i32 zeroext %a) {
entry:
%cmp = icmp ule i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob
ret void
; CHECK-LABEL: test_llleui_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleui_sext_z_store(i32 zeroext %a) {
entry:
%cmp = icmp ule i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
; CHECK-LABEL: @test_llleui_sext_z_store
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK: stw [[REG4]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesllleull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull(i64 %a, i64 %b) {
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: test_llleull:
; CHECK: subfc {{r[0-9]+}}, r3, r4
; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
; CHECK-NEXT: addi r3, [[REG1]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull_sext(i64 %a, i64 %b) {
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llleull_sext
; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull_z(i64 %a) {
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: test_llleull_z
; CHECK: cntlzd [[REG1:r[0-9]+]], r3
; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull_sext_z(i64 %a) {
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llleull_sext_z
; CHECK: addic [[REG1:r[0-9]+]], r3, -1
; CHECK: subfe r3, [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleull_store(i64 %a, i64 %b) {
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: test_llleull_store:
; CHECK: subfc {{r[0-9]+}}, r3, r4
; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
; CHECK: addi r3, [[REG1]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleull_sext_store(i64 %a, i64 %b) {
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_llleull_sext_store
; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
; CHECK: std [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleull_z_store(i64 %a) {
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: test_llleull_z_store:
; CHECK: cntlzd [[REG1:r[0-9]+]], r3
; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleull_sext_z_store(i64 %a) {
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_llleull_sext_z_store
; CHECK: addic [[REG1:r[0-9]+]], r3, -1
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: std [[REG2]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesllleus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: test_llleus:
; CHECK: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub [[REG1:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus_sext(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: @test_llleus_sext
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus_z(i16 zeroext %a) {
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
; CHECK-LABEL: test_llleus_z:
; CHECK: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus_sext_z(i16 zeroext %a) {
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
; CHECK-LABEL: @test_llleus_sext_z
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK-NEXT: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK-NEXT: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK-LABEL: test_llleus_store:
; CHECK: clrldi r4, r4, 32
; CHECK: clrldi r3, r3, 32
; CHECK: sub [[REG1:r[0-9]+]], r4, r3
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK-LABEL: @test_llleus_sext_store
; CHECK: subf [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: sth [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleus_z_store(i16 zeroext %a) {
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob
ret void
; CHECK-LABEL: test_llleus_z_store:
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleus_sext_z_store(i16 zeroext %a) {
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob
ret void
; CHECK-LABEL: @test_llleus_sext_z_store
; CHECK: cntlzw [[REG1:r[0-9]+]], r3
; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
; CHECK: sldi [[REG3:r[0-9]+]], [[REG2]], 63
; CHECK: sradi [[REG4:r[0-9]+]], [[REG3]], 63
; CHECK: sth [[REG4]]
; CHECK: blr
}

test/CodeGen/PowerPC/testComparesllltsc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llltsc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llltsc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_llltsc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 0
%sub = sext i1 %cmp to i64
ret i64 %sub
}
; Function Attrs: norecurse nounwind
define void @test_llltsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llltsc_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llltsc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_llltsc_sext_z_store:
; CHECK: srwi {{r[0-9]+}}, r3, 7
; CHECK: blr
entry:
%cmp = icmp slt i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesllltsi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llltsi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llltsi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_llltsi_sext_z:
; CHECK: srawi r3, r3, 31
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_llltsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llltsi_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llltsi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp slt i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_llltsi_sext_z_store:
; CHECK: srawi r3, r3, 31
; CHECK: blr
entry:
%cmp = icmp slt i32 %a, 0
%conv1 = sext i1 %cmp to i32
store i32 %conv1, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllltsll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: xori r3, [[REG4]], 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK-NEXT: neg r3, [[REG5]]
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll_sext_z(i64 %a) {
; CHECK-LABEL: test_llltsll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 0
%sub = sext i1 %cmp to i64
ret i64 %sub
}
; Function Attrs: norecurse nounwind
define void @test_llltsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK-NOT: neg
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
; CHECK: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llltsll_sext_z_store:
; CHECK: sradi r3, r3, 63
entry:
%cmp = icmp slt i64 %a, 0
%sub = sext i1 %cmp to i64
store i64 %sub, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesllltss.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llltss:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llltss_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_llltss_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: srawi r3, r3, 31
entry:
%cmp = icmp slt i16 %a, 0
%sub = sext i1 %cmp to i64
ret i64 %sub
}
; Function Attrs: norecurse nounwind
define void @test_llltss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llltss_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp slt i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llltss_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp slt i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_llltss_sext_z_store:
; CHECK: srwi r3, r3, 15
; CHECK: blr
entry:
%cmp = icmp slt i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesllltuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_llltuc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i64 0
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_llltuc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i64 0
}
; Function Attrs: norecurse nounwind
define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc_store:
; CHECK: # BB#0: # %entry
; CHECK: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK: sub [[REG:r[2-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llltuc_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: stb [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i8 0, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llltuc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: stb [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i8 0, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesllltui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui:
; CHECK: # BB#0: # %entry
; CHECK-NOT: clrldi
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltui_z(i32 zeroext %a) {
; CHECK-LABEL: test_llltui_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i64 0
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_llltui_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i64 0
}
; Function Attrs: norecurse nounwind
define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui_store:
; CHECK: # BB#0: # %entry
; CHECK-NOT: clrldi
; CHECK: sub [[REG:r[2-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NOT: clrldi
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ult i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llltui_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: stw [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i32 0, i32* @glob, align 4
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llltui_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: stw [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i32 0, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllltull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltull:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc [[REG:r[1-9]+]], r4, r3
; CHECK-NEXT: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NEXT: neg r3, [[REG2]]
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltull_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: subfe r3, [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltull_z(i64 %a) {
; CHECK-LABEL: test_llltull_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i64 0
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltull_sext_z(i64 %a) {
; CHECK-LABEL: test_llltull_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i64 0
}
; Function Attrs: norecurse nounwind
define void @test_llltull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltull_store:
; CHECK: # BB#0: # %entry
; CHECK: subfc [[REG:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NEXT: neg {{r[0-9]+}}, [[REG2]]
entry:
%cmp = icmp ult i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltull_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subfc [[REG:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], [[REG3:r[0-9]+]], [[REG3]]
; CHECK-NOT: neg
entry:
%cmp = icmp ult i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltull_z_store(i64 %a) {
; CHECK-LABEL: test_llltull_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: std [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i64 0, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llltull_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: std [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i64 0, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesllltus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llltus:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llltus_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf [[REG:r[0-9]+]], r4, r3
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltus_z(i16 zeroext %a) {
; CHECK-LABEL: test_llltus_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i64 0
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_llltus_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: blr
entry:
ret i64 0
}
; Function Attrs: norecurse nounwind
define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llltus_store:
; CHECK: # BB#0: # %entry
; CHECK: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK: sub [[REG:r[2-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llltus_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: subf [[REG:r[0-9]+]], r4, r3
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llltus_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: sth [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i16 0, i16* @glob, align 2
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llltus_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: li [[REG:r[0-9]+]], 0
; CHECK: sth [[REG]], 0(r3)
; CHECK-NEXT: blr
entry:
store i16 0, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesllnesc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_llnesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llnesc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llnesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llnesc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llnesc_z(i8 signext %a) {
; CHECK-LABEL: test_llnesc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
define i64 @test_llnesc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_llnesc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
define void @test_llnesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llnesc_store:
; CHECK: # BB#0: # %entry
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_llnesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llnesc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_llnesc_z_store(i8 signext %a) {
; CHECK-LABEL: test_llnesc_z_store:
; CHECK: # BB#0: # %entry
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
define void @test_llnesc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_llnesc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesllnesi.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_llnesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llnesi:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llnesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llnesi_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llnesi_z(i32 signext %a) {
; CHECK-LABEL: test_llnesi_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llnesi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_llnesi_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llnesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llnesi_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_llnesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llnesi_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_llnesi_z_store(i32 signext %a) {
; CHECK-LABEL: test_llnesi_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_llnesi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_llnesi_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllnesll.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llnesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llnesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llnesll_z(i64 %a) {
; CHECK-LABEL: test_llnesll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llnesll_sext_z(i64 %a) {
; CHECK-LABEL: test_llnesll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llnesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llnesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llnesll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llnesll_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llnesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llnesll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesllness.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llness(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llness:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llness_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llness_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r4, r4, 0, 32
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llness_z(i16 signext %a) {
; CHECK-LABEL: test_llness_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
define i64 @test_llness_sext_z(i16 signext %a) {
; CHECK-LABEL: test_llness_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 0, 32
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
define void @test_llness_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llness_store:
; CHECK: # BB#0: # %entry
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llness_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llness_sext_store:
; CHECK: # BB#0: # %entry
; CHECK: xor r3, r3, r4
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llness_z_store(i16 signext %a) {
; CHECK-LABEL: test_llness_z_store:
; CHECK: # BB#0: # %entry
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
define void @test_llness_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_llness_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK: cntlzw r3, r3
; CHECK: srwi r3, r3, 5
; CHECK: xori r3, r3, 1
; CHECK: neg r3, r3
; CHECK: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testComparesllneuc.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i8 0, align 1
define i64 @test_llneuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llneuc:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llneuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llneuc_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llneuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_llneuc_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
define i64 @test_llneuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_llneuc_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
define void @test_llneuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llneuc_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_llneuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llneuc_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
define void @test_llneuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llneuc_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}
define void @test_llneuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llneuc_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1
ret void
}

test/CodeGen/PowerPC/testComparesllneui.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i32 0, align 4
define i64 @test_llneui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llneui:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llneui_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneui_z(i32 zeroext %a) {
; CHECK-LABEL: test_llneui_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_llneui_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llneui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llneui_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_llneui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llneui_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}
define void @test_llneui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llneui_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4
ret void
}
define void @test_llneui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llneui_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4
ret void
}

test/CodeGen/PowerPC/testComparesllneull.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i64 0, align 8
define i64 @test_llneull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneull_z(i64 %a) {
; CHECK-LABEL: test_llneull_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
define i64 @test_llneull_sext_z(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
define void @test_llneull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llneull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llneull_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llneull_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
define void @test_llneull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llneull_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: subfic r3, r3, 0
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}

test/CodeGen/PowerPC/testComparesllneus.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
@glob = common local_unnamed_addr global i16 0, align 2
define i64 @test_llneus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llneus:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llneus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llneus_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
define i64 @test_llneus_z(i16 zeroext %a) {
; CHECK-LABEL: test_llneus_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
}
define i64 @test_llneus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_llneus_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
}
define void @test_llneus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llneus_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llneus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llneus_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2
ret void
}
define void @test_llneus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llneus_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}
define void @test_llneus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_llneus_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2
ret void
}

test/CodeGen/PowerPC/testSelectSetCCEQ.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i64 @set_flagi64_z(i64 %a, i64 %flags) {
; CHECK-LABEL: set_flagi64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32_z(i32 %a, i32 %flags) {
; CHECK-LABEL: set_flagi32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
; CHECK-LABEL: set_flagi64i32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64_z(i32 %a, i64 %flags) {
; CHECK-LABEL: set_flagi32i64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}

test/CodeGen/PowerPC/testSelectSetCCGE.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: rldicl r7, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r7
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 signext %a, i32 signext %b, i32 %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: rldicl r7, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r7
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 signext %a, i32 signext %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i64 @set_flagi64_z(i64 %a, i64 %flags) {
; CHECK-LABEL: set_flagi64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: li r5, 8
; CHECK-NEXT: rldicl r3, r3, 4, 60
; CHECK-NEXT: andc r3, r5, r3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32_z(i32 signext %a, i32 %flags) {
; CHECK-LABEL: set_flagi32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: srwi r3, r3, 28
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: rlwinm r3, r3, 0, 28, 28
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
; CHECK-LABEL: set_flagi64i32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i64 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64_z(i32 signext %a, i64 %flags) {
; CHECK-LABEL: set_flagi32i64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: nor r3, r3, r3
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sge i32 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}

test/CodeGen/PowerPC/testSelectSetCCGT.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: rldicl r7, r3, 1, 63
; CHECK-NEXT: subfc r12, r3, r4
; CHECK-NEXT: adde r3, r7, r6
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 signext %a, i32 signext %b, i32 %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: rldicl r7, r3, 1, 63
; CHECK-NEXT: subfc r12, r3, r4
; CHECK-NEXT: adde r3, r7, r6
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 signext %a, i32 signext %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i64 @set_flagi64_z(i64 %a, i64 %flags) {
; CHECK-LABEL: set_flagi64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: nor r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32_z(i32 signext %a, i32 %flags) {
; CHECK-LABEL: set_flagi32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
; CHECK-LABEL: set_flagi64i32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: nor r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64_z(i32 signext %a, i64 %flags) {
; CHECK-LABEL: set_flagi32i64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}

test/CodeGen/PowerPC/testSelectSetCCLE.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: rldicl r7, r3, 1, 63
; CHECK-NEXT: subfc r12, r3, r4
; CHECK-NEXT: adde r3, r6, r7
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 signext %a, i32 signext %b, i32 %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: rldicl r7, r3, 1, 63
; CHECK-NEXT: subfc r12, r3, r4
; CHECK-NEXT: adde r3, r6, r7
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 signext %a, i32 signext %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i64 @set_flagi64_z(i64 %a, i64 %flags) {
; CHECK-LABEL: set_flagi64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32_z(i32 signext %a, i32 %flags) {
; CHECK-LABEL: set_flagi32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
; CHECK-LABEL: set_flagi64i32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: or r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i64 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64_z(i32 signext %a, i64 %flags) {
; CHECK-LABEL: set_flagi32i64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp sle i32 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}

test/CodeGen/PowerPC/testSelectSetCCLT.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: rldicl r7, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r7, r6
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 signext %a, i32 signext %b, i32 zeroext %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 zeroext %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
; CHECK-NEXT: rldicl r7, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r7, r6
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 signext %a, i32 signext %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subf r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i64 @set_flagi64_z(i64 %a, i64 %flags) {
; CHECK-LABEL: set_flagi64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rotldi r3, r3, 1
; CHECK-NEXT: rldic r3, r3, 3, 60
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32_z(i32 signext %a, i32 %flags) {
; CHECK-LABEL: set_flagi32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rlwinm r3, r3, 4, 28, 28
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
; CHECK-LABEL: set_flagi64i32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64_z(i32 signext %a, i64 %flags) {
; CHECK-LABEL: set_flagi32i64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: srwi r3, r3, 31
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}

test/CodeGen/PowerPC/testSelectSetCCNE.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r4, r3, -1
; CHECK-NEXT: subfe r3, r4, r3
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i64 @set_flagi64_z(i64 %a, i64 %flags) {
; CHECK-LABEL: set_flagi64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32_z(i32 %a, i32 %flags) {
; CHECK-LABEL: set_flagi32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
; CHECK-LABEL: set_flagi64i32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i64 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64_z(i32 %a, i64 %flags) {
; CHECK-LABEL: set_flagi32i64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}

test/CodeGen/PowerPC/testSelectSetCCUGE.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: li r6, 8
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 4, 60
; CHECK-NEXT: andc r3, r6, r3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i64 @set_flagi64_z(i64 %a, i64 %flags) {
; CHECK-LABEL: set_flagi64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: ori r3, r4, 8
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32_z(i32 %a, i32 %flags) {
; CHECK-LABEL: set_flagi32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: ori r3, r4, 8
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
; CHECK-LABEL: set_flagi64i32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: ori r3, r4, 8
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64_z(i32 %a, i64 %flags) {
; CHECK-LABEL: set_flagi32i64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: ori r3, r4, 8
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}

test/CodeGen/PowerPC/testSelectSetCCUGT.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rotldi r3, r3, 1
; CHECK-NEXT: rldic r3, r3, 3, 60
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i64 @set_flagi64_z(i64 %a, i64 %flags) {
; CHECK-LABEL: set_flagi64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32_z(i32 %a, i32 %flags) {
; CHECK-LABEL: set_flagi32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32_z(i64 %a, i32 %flags) {
; CHECK-LABEL: set_flagi64i32_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r5, r3, -1
; CHECK-NEXT: subfe r3, r5, r3
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i64 %a, 0
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64_z(i32 %a, i64 %flags) {
; CHECK-LABEL: set_flagi32i64_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, 0
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}

test/CodeGen/PowerPC/testSelectSetCCULE.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r4, r3, r4
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: li r6, 8
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 4, 60
; CHECK-NEXT: andc r3, r6, r3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}

test/CodeGen/PowerPC/testSelectSetCCULT.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define i64 @set_flagi64(i64 %a, i64 %b, i64 %flags) {
; CHECK-LABEL: set_flagi64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sldi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i64 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}
define i32 @set_flagi32(i32 %a, i32 %b, i32 %flags) {
; CHECK-LABEL: set_flagi32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i32 @set_flagi64i32(i64 %a, i64 %b, i32 %flags) {
; CHECK-LABEL: set_flagi64i32:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: subfc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: slwi r3, r3, 3
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i64 %a, %b
%conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 3
%or = or i32 %shl, %flags
ret i32 %or
}
define i64 @set_flagi32i64(i32 %a, i32 %b, i64 %flags) {
; CHECK-LABEL: set_flagi32i64:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rotldi r3, r3, 1
; CHECK-NEXT: rldic r3, r3, 3, 60
; CHECK-NEXT: or r3, r3, r5
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i64
%shl = shl nuw nsw i64 %conv, 3
%or = or i64 %shl, %flags
ret i64 %or
}