GlobalISel: Translate ConstantAggregateZero vectors

[volkan]

Use G_MERGE_VALUES to represent vectors.

[qcolombet]

LGTM

lib/CodeGen/GlobalISel/IRTranslator.cpp

984

I would just return false.
The caller should check the fallback/abort status.

I know surrounding code does that, but we should fix that as well. I'll have a try.

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

1206

Add a non-power-of-2 test case

[volkan]

• Added a non-power-of-2 test.
• Removed GlobalISelAbortEnabled check.

[qcolombet]

lib/CodeGen/GlobalISel/IRTranslator.cpp

984

That's r297535

lib/CodeGen/GlobalISel/IRTranslator.cpp

bool IRTranslator::translate(const Constant &C, unsigned Reg) {
   else if (auto CF = dyn_cast<ConstantFP>(&C))
     EntryBuilder.buildFConstant(Reg, *CF);
   else if (isa<UndefValue>(C))
     EntryBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(Reg);
   else if (isa<ConstantPointerNull>(C))
     EntryBuilder.buildConstant(Reg, 0);
   else if (auto GV = dyn_cast<GlobalValue>(&C))
     EntryBuilder.buildGlobalValue(Reg, GV);
-  else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
+  else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
+    if (!CAZ->getType()->isVectorTy()) {
+      if (!TPC->isGlobalISelAbortEnabled())
+        return false;
+      llvm_unreachable("unhandled constant aggregate zero");
+    }
+    std::vector<unsigned> Ops;
+    std::vector<uint64_t> Indices;
+    for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
+      Constant &Elt = *CAZ->getElementValue(i);
+      Ops.push_back(getOrCreateVReg(Elt));
+      Indices.push_back(i * CAZ->getType()->getScalarSizeInBits());
+    }
+    EntryBuilder.buildSequence(Reg, Ops, Indices);
+  } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
     switch(CE->getOpcode()) {
 #define HANDLE_INST(NUM, OPCODE, CLASS)                         \
       case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
 #include "llvm/IR/Instruction.def"
     default:
       if (!TPC->isGlobalISelAbortEnabled())
         return false;
       llvm_unreachable("unknown opcode");

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store singlethread monotonic 1 into %ir.addr)
   %v1 = load atomic i8, i8* %addr acquire, align 1
   store atomic i8 %v1, i8* %addr release, align 1
 
   %v2 = load atomic i8, i8* %addr singlethread seq_cst, align 1
   store atomic i8 %v2, i8* %addr singlethread monotonic, align 1
 
   ret void
 }
+
+define <2 x i32> @test_constant_agg_zero_vector() {
+; CHECK-LABEL: name: test_constant_agg_zero_vector
+; CHECK: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
+; CHECK: [[RES:%[0-9]+]](<2 x s32>) = G_SEQUENCE [[ZERO]](s32), 0, [[ZERO]](s32), 32
+; CHECK: %d0 = COPY [[RES]](<2 x s32>)
+entry:
+  ret <2 x i32> zeroinitializer
+}