[AArch64][TableGen] Skip tied result operands for InstAlias

[huntergr]

Summary

This patch checks the number of operands in the resulting
instruction instead of just the alias, then skips over
tied operands when generating the printing method.

This allows us to generate the preferred assembly syntax
for the AArch64 'ins' instruction, which should always be
displayed as 'mov' according to the ARMARM.

Several unit tests have changed as a result, but only to
reflect the preferred disassembly.

Some other InstAlias patterns (movk/bic/orr) needed a
slight adjustment to stop them becoming the default
and breaking other unit tests.

[rengolin]

Hi Graham,

I think you got your patch backwards...

cheers,
--renato

[rengolin]

Hi Graham,

This looks ok to me, but I'm not confident to approve a TableGen back-end patch that could potentially change the behaviour in other targets.

I'm adding other people that touched the code / table files recently, and I'm hoping that other targets developers got the mail via the commits list and will chime in if necessary.

cheers,
--renato

lib/Target/AArch64/AArch64InstrInfo.td

454–456

If I read Target.td correctly, this completely disables the printing in all cases, not just the one you're testing.

4398–4402

I'm not sure why this was disabled, probably due to a similar conflict in the past.

The original patch that introduced this by Tim explains nothing, so I'll assume this is ok.

[huntergr]

In D29219#658698, @rengolin wrote:

Hi Graham,

This looks ok to me, but I'm not confident to approve a TableGen back-end patch that could potentially change the behaviour in other targets.

I'm adding other people that touched the code / table files recently, and I'm hoping that other targets developers got the mail via the commits list and will chime in if necessary.

cheers,
--renato

Thanks for looking over it.

lib/Target/AArch64/AArch64InstrInfo.td

454–456

That's my understanding as well. In this case, imm0_65535 printed in hex, whereas the unit tests are in decimal. The alternative is to change the tests to expect hex.

[rengolin]

lib/Target/AArch64/AArch64InstrInfo.td

454–456

No, decimals are fine.

It may be that the other encodings are also just for the assembler, not code generation, so would be better to have the explicit 0.

But I don't think this is worth doing in this patch. It would be better for someone to look at that later with more extensive testing, to make sure nothing is lost in translation.

[huntergr]

Ping.

For clarity wrt. the movk/bic/orr pattern changes, they never triggered when printing asm before because the base patterns in AArch64InstrFormats.td (BaseInsertImmediate and BaseSIMDModifiedImmVectorTied) both contain tied register constraints. Since they now print with this change, I've adjusted the priority where needed to avoid breaking the existing unit tests, and just change ins to mov.

[rengolin]

In D29219#667592, @huntergr wrote:

Ping.

Hi Graham,

I was waiting from other comments, especially regarding the tied operand logic for other targets, which I'm not familiar with. I'm surprised this didn't trigger anything else in any other target. Are you building and testing all targets?

For clarity wrt. the movk/bic/orr pattern changes, they never triggered when printing asm before because the base patterns in AArch64InstrFormats.td (BaseInsertImmediate and BaseSIMDModifiedImmVectorTied) both contain tied register constraints. Since they now print with this change, I've adjusted the priority where needed to avoid breaking the existing unit tests, and just change ins to mov.

I suspected as much. It looks good from the AArch64 point of view. We can give it a few more days, and if no one objects, I'll approve and we try our luck on the buildbots. :)

cheers,
--renato

[huntergr]

In D29219#667645, @rengolin wrote:

In D29219#667592, @huntergr wrote:

Ping.

Hi Graham,

I was waiting from other comments, especially regarding the tied operand logic for other targets, which I'm not familiar with. I'm surprised this didn't trigger anything else in any other target. Are you building and testing all targets?

I've run make check-all for all targets, no failures; I was a little surprised that no changes were required on other targets as well (with both debug and release builds), but I don't know how many other architectures have significant differences between representations of the same instruction.

For clarity wrt. the movk/bic/orr pattern changes, they never triggered when printing asm before because the base patterns in AArch64InstrFormats.td (BaseInsertImmediate and BaseSIMDModifiedImmVectorTied) both contain tied register constraints. Since they now print with this change, I've adjusted the priority where needed to avoid breaking the existing unit tests, and just change ins to mov.

I suspected as much. It looks good from the AArch64 point of view. We can give it a few more days, and if no one objects, I'll approve and we try our luck on the buildbots. :)

cheers,
--renato

[rengolin]

In D29219#667646, @huntergr wrote:

I've run make check-all for all targets, no failures; I was a little surprised that no changes were required on other targets as well (with both debug and release builds), but I don't know how many other architectures have significant differences between representations of the same instruction.

Ha, right, this was introduced by Tim specifically for AArch64 in commit r208880, and he moved the x86 usage of this code away, so it should only affect the AArch64 back-end.

I'm setting to accepted now, but wait a day to commit, so that we give a bit more time for people to review.

cheers,
--renato

[MatzeB]

Hi,

the "Clang Stage 2: cmake, R -g Asan+Ubsan" buildbot on greendragon is failing as of build
#3583. Full log at http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_build/3583/consoleFull#-1431883905a1ca8a51-895e-46c6-af87-ce24fa4cd561

Given the backtrace this seems like the most likely commit in the change list. Could you please take a look.

Thanks,

Matthias

FAILED: lib/Target/AArch64/AArch64GenAsmWriter.inc.tmp

cd /Users/buildslave/jenkins/sharedspace/clang-stage2-cmake-RgSan@2/clang-build/lib/Target/AArch64 && /Users/buildslave/jenkins/sharedspace/clang-stage2-cmake-RgSan@2/clang-build/bin/llvm-tblgen -gen-asm-writer -I /Users/buildslave/jenkins/sharedspace/clang-stage2-cmake-RgSan@2/llvm/lib/Target/AArch64 -I /Users/buildslave/jenkins/sharedspace/clang-stage2-cmake-RgSan@2/llvm/include -I /Users/buildslave/jenkins/sharedspace/clang-stage2-cmake-RgSan@2/llvm/lib/Target /Users/buildslave/jenkins/sharedspace/clang-stage2-cmake-RgSan@2/llvm/lib/Target/AArch64/AArch64.td -o /Users/buildslave/jenkins/sharedspace/clang-stage2-cmake-RgSan@2/clang-build/lib/Target/AArch64/AArch64GenAsmWriter.inc.tmp

309==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x615000f8a4e4 at pc 0x00010916bae6 bp 0x7fff56b25fb0 sp 0x7fff56b25fa8

READ of size 4 at 0x615000f8a4e4 thread T0

#0 0x10916bae5 in (anonymous namespace)::AsmWriterEmitter::EmitPrintAliasInstruction(llvm::raw_ostream&) AsmWriterEmitter.cpp:835
#1 0x1091514fa in llvm::EmitAsmWriter(llvm::RecordKeeper&, llvm::raw_ostream&) AsmWriterEmitter.cpp:1125
#2 0x1094b145d in (anonymous namespace)::LLVMTableGenMain(llvm::raw_ostream&, llvm::RecordKeeper&) TableGen.cpp:124
#3 0x10956b99e in llvm::TableGenMain(char*, bool (*)(llvm::raw_ostream&, llvm::RecordKeeper&)) Main.cpp:109
#4 0x1094b0d30 in main TableGen.cpp:205
#5 0x7fff95d095ac in start (libdyld.dylib:x86_64+0x35ac)

0x615000f8a4e4 is located 28 bytes to the left of 504-byte region [0x615000f8a500,0x615000f8a6f8)
allocated by thread T0 here:

#0 0x109c0ee1b in wrap__Znwm (libclang_rt.asan_osx_dynamic.dylib:x86_64+0x62e1b)
#1 0x10922e41a in std::__1::__split_buffer<llvm::CGIOperandList::OperandInfo, std::__1::allocator<llvm::CGIOperandList::OperandInfo>&>::__split_buffer(unsigned long, unsigned long, std::__1::allocator<llvm::CGIOperandList::OperandInfo>&) new:215
#2 0x10921e655 in std::__1::vector<llvm::CGIOperandList::OperandInfo, std::__1::allocator<llvm::CGIOperandList::OperandInfo> >::reserve(unsigned long) __split_buffer:310
#3 0x10921ad71 in llvm::CGIOperandList::CGIOperandList(llvm::Record*) CodeGenInstruction.cpp:53
#4 0x10922205e in llvm::CodeGenInstruction::CodeGenInstruction(llvm::Record*) CodeGenInstruction.cpp:28
#5 0x1092ffda0 in llvm::CodeGenTarget::ReadInstructions() const STLExtras.h:846
#6 0x1093002ee in llvm::CodeGenTarget::ComputeInstrsByEnum() const CodeGenTarget.h:150
#7 0x10910fd6f in llvm::CodeGenTarget::getInstructionsByEnumValue() const CodeGenTarget.h:166
#8 0x1091506df in llvm::EmitAsmWriter(llvm::RecordKeeper&, llvm::raw_ostream&) AsmWriterEmitter.cpp:1113
#9 0x1094b145d in (anonymous namespace)::LLVMTableGenMain(llvm::raw_ostream&, llvm::RecordKeeper&) TableGen.cpp:124
#10 0x10956b99e in llvm::TableGenMain(char*, bool (*)(llvm::raw_ostream&, llvm::RecordKeeper&)) Main.cpp:109
#11 0x1094b0d30 in main TableGen.cpp:205
#12 0x7fff95d095ac in start (libdyld.dylib:x86_64+0x35ac)

SUMMARY: AddressSanitizer: heap-buffer-overflow AsmWriterEmitter.cpp:835 in (anonymous namespace)::AsmWriterEmitter::EmitPrintAliasInstruction(llvm::raw_ostream&)
Shadow bytes around the buggy address:

0x1c2a001f1440: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x1c2a001f1450: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x1c2a001f1460: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x1c2a001f1470: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x1c2a001f1480: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa

>0x1c2a001f1490: fa fa fa fa fa fa fa fa fa fa fa fa[fa]fa fa fa

0x1c2a001f14a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x1c2a001f14b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x1c2a001f14c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x1c2a001f14d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa
0x1c2a001f14e0: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa

Shadow byte legend (one shadow byte represents 8 application bytes):

Addressable:           00
Partially addressable: 01 02 03 04 05 06 07 
Heap left redzone:       fa
Freed heap region:       fd
Stack left redzone:      f1
Stack mid redzone:       f2
Stack right redzone:     f3
Stack after return:      f5
Stack use after scope:   f8
Global redzone:          f9
Global init order:       f6
Poisoned by user:        f7
Container overflow:      fc
Array cookie:            ac
Intra object redzone:    bb
ASan internal:           fe
Left alloca redzone:     ca
Right alloca redzone:    cb

309==ABORTING

lib/Target/AArch64/AArch64InstrInfo.td

 //===----------------------------------------------------------------------===//
 
 defm MOVK : InsertImmediate<0b11, "movk">;
 defm MOVN : MoveImmediate<0b00, "movn">;
 
 let PostEncoderMethod = "fixMOVZ" in
 defm MOVZ : MoveImmediate<0b10, "movz">;
 
 // First group of aliases covers an implicit "lsl #0".
-def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0), 0>;
-def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0), 0>;
+def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
+def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
 
 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
 
 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
 
-def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48), 0>;
-def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32), 0>;
-def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16), 0>;
-def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0), 0>;
+def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
+def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
+def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
+def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
 
 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
 
 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
 
-def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16), 0>;
-def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0), 0>;
+def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
+def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
 
 // Final group of aliases covers true "mov $Rd, $imm" cases.
 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
                           int width, int shift> {
   def _asmoperand : AsmOperandClass {
     let Name = basename # width # "_lsl" # shift # "MovAlias";
     let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
                                # shift # ">";

 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
 // AdvSIMD ORR
 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
 
 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd,  imm0_255:$imm, 0)>;
 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd,  imm0_255:$imm, 0)>;
 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
 
-def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd,  imm0_255:$imm, 0)>;
-def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
-def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd,  imm0_255:$imm, 0)>;
-def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
+def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd,  imm0_255:$imm, 0), 0>;
+def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
+def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd,  imm0_255:$imm, 0), 0>;
+def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
 
 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd,  imm0_255:$imm, 0)>;
 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd,  imm0_255:$imm, 0)>;
 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
 
-def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd,  imm0_255:$imm, 0)>;
-def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
-def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd,  imm0_255:$imm, 0)>;
-def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
+def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd,  imm0_255:$imm, 0), 0>;
+def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
+def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd,  imm0_255:$imm, 0), 0>;
+def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
 
 // AdvSIMD FMOV
 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8,
                                               "fmov", ".2d",
                        [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1111, V64,  fpimm8,
                                               "fmov", ".2s",
                        [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;

test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll

 ; banks copies that cannot be coalesced.
 ; CHECK-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]
 ; With advanced copy optimization, we end up with just one copy
 ; to insert the computed high part into the V register. 
 ; CHECK-OPT-NOT: fmov
 ; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
 ; CHECK-NOOPT: fmov d0, [[COPY_REG3]]
 ; CHECK-OPT-NOT: fmov
-; CHECK: mov.d v0[1], [[COPY_REG2]]
+; CHECK: ins.d v0[1], [[COPY_REG2]]
 ; CHECK-NEXT: ret
 ;
 ; GENERIC-LABEL: bar:
 ; GENERIC: add  v[[REG:[0-9]+]].2d, v0.2d, v1.2d
 ; GENERIC: add  d[[REG3:[0-9]+]], d[[REG]], d1
 ; GENERIC: sub  d[[REG2:[0-9]+]], d[[REG]], d1
 ; GENERIC-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]
 ; GENERIC-OPT-NOT: fmov
 ; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
 ; GENERIC-NOOPT: fmov d0, [[COPY_REG3]]
 ; GENERIC-OPT-NOT: fmov
-; GENERIC: mov v0.d[1], [[COPY_REG2]]
+; GENERIC: ins v0.d[1], [[COPY_REG2]]
 ; GENERIC-NEXT: ret
   %add = add <2 x i64> %a, %b
   %vgetq_lane = extractelement <2 x i64> %add, i32 0
   %vgetq_lane2 = extractelement <2 x i64> %b, i32 0
   %add3 = add i64 %vgetq_lane, %vgetq_lane2
   %sub = sub i64 %vgetq_lane, %vgetq_lane2
   %vecinit = insertelement <2 x i64> undef, i64 %add3, i32 0
   %vecinit8 = insertelement <2 x i64> %vecinit, i64 %sub, i32 1

test/CodeGen/AArch64/arm64-build-vector.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
 ; Check that building up a vector w/ only one non-zero lane initializes
 ; intelligently.
 define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
 ; CHECK-LABEL: one_lane:
 ; CHECK: dup.16b v[[REG:[0-9]+]], wzr
-; CHECK-NEXT: mov.b v[[REG]][0], w1
+; CHECK-NEXT: ins.b v[[REG]][0], w1
 ; v and q are aliases, and str is preferred against st.16b when possible
 ; rdar://11246289
 ; CHECK: str q[[REG]], [x0]
 ; CHECK: ret
   %conv = trunc i32 %skip0 to i8
   %vset_lane = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv, i32 0
   %tmp = bitcast i32* %out_int to <4 x i32>*
   %tmp1 = bitcast <16 x i8> %vset_lane to <4 x i32>
   store <4 x i32> %tmp1, <4 x i32>* %tmp, align 16
   ret void
 }
 
 ; Check that building a vector from floats doesn't insert an unnecessary
 ; copy for lane zero.
 define <4 x float>  @foo(float %a, float %b, float %c, float %d) nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK-NOT: ins.s v0[0], v0[0]
-; CHECK: mov.s v0[1], v1[0]
-; CHECK: mov.s v0[2], v2[0]
-; CHECK: mov.s v0[3], v3[0]
+; CHECK: ins.s v0[1], v1[0]
+; CHECK: ins.s v0[2], v2[0]
+; CHECK: ins.s v0[3], v3[0]
 ; CHECK: ret
   %1 = insertelement <4 x float> undef, float %a, i32 0
   %2 = insertelement <4 x float> %1, float %b, i32 1
   %3 = insertelement <4 x float> %2, float %c, i32 2
   %4 = insertelement <4 x float> %3, float %d, i32 3
   ret <4 x float> %4
 }
 

test/CodeGen/AArch64/arm64-dup.ll

 entry:
   %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
   ret <2 x double> %0
 }
 
 define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone  {
 ; CHECK-LABEL: f:
 ; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: mov.s v0[1], w1
+; CHECK-NEXT: ins.s v0[1], w1
 ; CHECK-NEXT: ret
   %vecinit = insertelement <2 x i32> undef, i32 %a, i32 0
   %vecinit1 = insertelement <2 x i32> %vecinit, i32 %b, i32 1
   ret <2 x i32> %vecinit1
 }
 
 define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone  {
 ; CHECK-LABEL: g:
 ; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: mov.s v0[1], w1
-; CHECK-NEXT: mov.s v0[2], w1
-; CHECK-NEXT: mov.s v0[3], w0
+; CHECK-NEXT: ins.s v0[1], w1
+; CHECK-NEXT: ins.s v0[2], w1
+; CHECK-NEXT: ins.s v0[3], w0
 ; CHECK-NEXT: ret
   %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
   %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
   %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
   %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %a, i32 3
   ret <4 x i32> %vecinit3
 }
 
 define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone  {
 ; CHECK-LABEL: h:
 ; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: mov.d v0[1], x1
+; CHECK-NEXT: ins.d v0[1], x1
 ; CHECK-NEXT: ret
   %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
   %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
   ret <2 x i64> %vecinit1
 }
 
 ; We used to spot this as a BUILD_VECTOR implementable by dup, but assume that
 ; the single value needed was of the same type as the vector. This is false if

test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll

 
 ; Check for dependencies between the vector and the scalar load.
 define <4 x float> @test_v4f32_post_reg_ld1lane_dep_vec_on_load(float* %bar, float** %ptr, i64 %inc, <4 x float>* %dep_ptr_1, <4 x float>* %dep_ptr_2, <4 x float> %vec) {
 ; CHECK-LABEL: test_v4f32_post_reg_ld1lane_dep_vec_on_load:
 ; CHECK: BB#0:
 ; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0]
 ; CHECK-NEXT: str q0, [x3]
 ; CHECK-NEXT: ldr q0, [x4]
-; CHECK-NEXT: mov.s v0[1], v[[LD]][0]
+; CHECK-NEXT: ins.s v0[1], v[[LD]][0]
 ; CHECK-NEXT: add [[POST:x[0-9]]], x0, x2, lsl #2
 ; CHECK-NEXT: str [[POST]], [x1]
 ; CHECK-NEXT: ret
   %tmp1 = load float, float* %bar
   store <4 x float> %vec, <4 x float>* %dep_ptr_1, align 16
   %A = load <4 x float>, <4 x float>* %dep_ptr_2, align 16
   %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1
   %tmp3 = getelementptr float, float* %bar, i64 %inc

test/CodeGen/AArch64/arm64-neon-copy.ll

 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
 
 
 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
 ; CHECK-LABEL: ins16bw:
-; CHECK: mov {{v[0-9]+}}.b[15], {{w[0-9]+}}
+; CHECK: ins {{v[0-9]+}}.b[15], {{w[0-9]+}}
   %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 15
   ret <16 x i8> %tmp3
 }
 
 define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {
 ; CHECK-LABEL: ins8hw:
-; CHECK: mov {{v[0-9]+}}.h[6], {{w[0-9]+}}
+; CHECK: ins {{v[0-9]+}}.h[6], {{w[0-9]+}}
   %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 6
   ret <8 x i16> %tmp3
 }
 
 define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {
 ; CHECK-LABEL: ins4sw:
-; CHECK: mov {{v[0-9]+}}.s[2], {{w[0-9]+}}
+; CHECK: ins {{v[0-9]+}}.s[2], {{w[0-9]+}}
   %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 2
   ret <4 x i32> %tmp3
 }
 
 define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {
 ; CHECK-LABEL: ins2dw:
-; CHECK: mov {{v[0-9]+}}.d[1], {{x[0-9]+}}
+; CHECK: ins {{v[0-9]+}}.d[1], {{x[0-9]+}}
   %tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 1
   ret <2 x i64> %tmp3
 }
 
 define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {
 ; CHECK-LABEL: ins8bw:
-; CHECK: mov {{v[0-9]+}}.b[5], {{w[0-9]+}}
+; CHECK: ins {{v[0-9]+}}.b[5], {{w[0-9]+}}
   %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 5
   ret <8 x i8> %tmp3
 }
 
 define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {
 ; CHECK-LABEL: ins4hw:
-; CHECK: mov {{v[0-9]+}}.h[3], {{w[0-9]+}}
+; CHECK: ins {{v[0-9]+}}.h[3], {{w[0-9]+}}
   %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 3
   ret <4 x i16> %tmp3
 }
 
 define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {
 ; CHECK-LABEL: ins2sw:
-; CHECK: mov {{v[0-9]+}}.s[1], {{w[0-9]+}}
+; CHECK: ins {{v[0-9]+}}.s[1], {{w[0-9]+}}
   %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
   ret <2 x i32> %tmp3
 }
 
 define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {
 ; CHECK-LABEL: ins16b16:
-; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
+; CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
   %tmp3 = extractelement <16 x i8> %tmp1, i32 2
   %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
   ret <16 x i8> %tmp4
 }
 
 define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {
 ; CHECK-LABEL: ins8h8:
-; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
+; CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <8 x i16> %tmp1, i32 2
   %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
   ret <8 x i16> %tmp4
 }
 
 define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {
 ; CHECK-LABEL: ins4s4:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
   %tmp3 = extractelement <4 x i32> %tmp1, i32 2
   %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
 ; CHECK-LABEL: ins2d2:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <2 x i64> %tmp1, i32 0
   %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
   ret <2 x i64> %tmp4
 }
 
 define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
 ; CHECK-LABEL: ins4f4:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
   %tmp3 = extractelement <4 x float> %tmp1, i32 2
   %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
   ret <4 x float> %tmp4
 }
 
 define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
 ; CHECK-LABEL: ins2df2:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <2 x double> %tmp1, i32 0
   %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
   ret <2 x double> %tmp4
 }
 
 define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
 ; CHECK-LABEL: ins8b16:
-; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
+; CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
   %tmp3 = extractelement <8 x i8> %tmp1, i32 2
   %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
   ret <16 x i8> %tmp4
 }
 
 define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
 ; CHECK-LABEL: ins4h8:
-; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
+; CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <4 x i16> %tmp1, i32 2
   %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
   ret <8 x i16> %tmp4
 }
 
 define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
 ; CHECK-LABEL: ins2s4:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
+; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
   %tmp3 = extractelement <2 x i32> %tmp1, i32 1
   %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
 ; CHECK-LABEL: ins1d2:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <1 x i64> %tmp1, i32 0
   %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
   ret <2 x i64> %tmp4
 }
 
 define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
 ; CHECK-LABEL: ins2f4:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
+; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
   %tmp3 = extractelement <2 x float> %tmp1, i32 1
   %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
   ret <4 x float> %tmp4
 }
 
 define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
 ; CHECK-LABEL: ins1f2:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <1 x double> %tmp1, i32 0
   %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
   ret <2 x double> %tmp4
 }
 
 define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
 ; CHECK-LABEL: ins16b8:
-; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
+; CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
   %tmp3 = extractelement <16 x i8> %tmp1, i32 2
   %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
   ret <8 x i8> %tmp4
 }
 
 define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
 ; CHECK-LABEL: ins8h4:
-; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
+; CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <8 x i16> %tmp1, i32 2
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
   ret <4 x i16> %tmp4
 }
 
 define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
 ; CHECK-LABEL: ins4s2:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
   %tmp3 = extractelement <4 x i32> %tmp1, i32 2
   %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
   ret <2 x i32> %tmp4
 }
 
 define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
 ; CHECK-LABEL: ins2d1:
-; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <2 x i64> %tmp1, i32 0
   %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
   ret <1 x i64> %tmp4
 }
 
 define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
 ; CHECK-LABEL: ins4f2:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
   %tmp3 = extractelement <4 x float> %tmp1, i32 2
   %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
   ret <2 x float> %tmp4
 }
 
 define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
 ; CHECK-LABEL: ins2f1:
 ; CHECK: mov {{d[0-9]+}}, {{v[0-9]+}}.d[1]
   %tmp3 = extractelement <2 x double> %tmp1, i32 1
   %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
   ret <1 x double> %tmp4
 }
 
 define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
 ; CHECK-LABEL: ins8b8:
-; CHECK: mov {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
+; CHECK: ins {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
   %tmp3 = extractelement <8 x i8> %tmp1, i32 2
   %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4
   ret <8 x i8> %tmp4
 }
 
 define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
 ; CHECK-LABEL: ins4h4:
-; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
+; CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <4 x i16> %tmp1, i32 2
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
   ret <4 x i16> %tmp4
 }
 
 define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
 ; CHECK-LABEL: ins2s2:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
+; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
   %tmp3 = extractelement <2 x i32> %tmp1, i32 0
   %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
   ret <2 x i32> %tmp4
 }
 
 define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
 ; CHECK-LABEL: ins1d1:
-; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <1 x i64> %tmp1, i32 0
   %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
   ret <1 x i64> %tmp4
 }
 
 define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
 ; CHECK-LABEL: ins2f2:
-; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
+; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
   %tmp3 = extractelement <2 x float> %tmp1, i32 0
   %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
   ret <2 x float> %tmp4
 }
 
 define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
 ; CHECK-LABEL: ins1df1:
 ; CHECK-NOT: ins {{v[0-9]+}}

 ; CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.s[1]
   %tmp3 = extractelement <2 x i32> %tmp1, i32 1
   %tmp4 = sext i32 %tmp3 to i64
   ret i64 %tmp4
 }
 
 define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {
 ; CHECK-LABEL: test_vcopy_lane_s8:
-; CHECK: mov  {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]
+; CHECK: ins  {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]
   %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 11, i32 6, i32 7>
   ret <8 x i8> %vset_lane
 }
 
 define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) {
 ; CHECK-LABEL: test_vcopyq_laneq_s8:
-; CHECK: mov  {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]
+; CHECK: ins  {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]
   %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 22, i32 15>
   ret <16 x i8> %vset_lane
 }
 
 define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {
 ; CHECK-LABEL: test_vcopy_lane_swap_s8:
-; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]
+; CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]
   %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
   ret <8 x i8> %vset_lane
 }
 
 define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {
 ; CHECK-LABEL: test_vcopyq_laneq_swap_s8:
-; CHECK: mov {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]
+; CHECK: ins {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]
   %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vset_lane
 }
 
 define <8 x i8> @test_vdup_n_u8(i8 %v1) #0 {
 ; CHECK-LABEL: test_vdup_n_u8:
 ; CHECK: dup {{v[0-9]+}}.8b, {{w[0-9]+}}
   %vecinit.i = insertelement <8 x i8> undef, i8 %v1, i32 0
; CHECK: ret
   ret <8 x i8> %vecinit14
 }
 
 ; CHECK-LABEL: test_extracts_inserts_varidx_extract:
 ; CHECK: str q0
 ; CHECK-DAG: and [[MASKED_IDX:x[0-9]+]], x0, #0x7
 ; CHECK: bfi [[PTR:x[0-9]+]], [[MASKED_IDX]], #1, #3
 ; CHECK-DAG: ld1 { v[[R:[0-9]+]].h }[0], {{\[}}[[PTR]]{{\]}}
-; CHECK-DAG: mov v[[R]].h[1], v0.h[1]
-; CHECK-DAG: mov v[[R]].h[2], v0.h[2]
-; CHECK-DAG: mov v[[R]].h[3], v0.h[3]
+; CHECK-DAG: ins v[[R]].h[1], v0.h[1]
+; CHECK-DAG: ins v[[R]].h[2], v0.h[2]
+; CHECK-DAG: ins v[[R]].h[3], v0.h[3]
 define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) {
   %tmp = extractelement <8 x i16> %x, i32 %idx
   %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0
   %tmp3 = extractelement <8 x i16> %x, i32 1
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1
   %tmp5 = extractelement <8 x i16> %x, i32 2
   %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2
   %tmp7 = extractelement <8 x i16> %x, i32 3
   %tmp8 = insertelement <4 x i16> %tmp6, i16 %tmp7, i32 3
   ret <4 x i16> %tmp8
 }
 
 ; CHECK-LABEL: test_extracts_inserts_varidx_insert:
 ; CHECK: and [[MASKED_IDX:x[0-9]+]], x0, #0x3
 ; CHECK: bfi x9, [[MASKED_IDX]], #1, #2
 ; CHECK: st1 { v0.h }[0], [x9]
 ; CHECK-DAG: ldr d[[R:[0-9]+]]
-; CHECK-DAG: mov v[[R]].h[1], v0.h[1]
-; CHECK-DAG: mov v[[R]].h[2], v0.h[2]
-; CHECK-DAG: mov v[[R]].h[3], v0.h[3]
+; CHECK-DAG: ins v[[R]].h[1], v0.h[1]
+; CHECK-DAG: ins v[[R]].h[2], v0.h[2]
+; CHECK-DAG: ins v[[R]].h[3], v0.h[3]
 define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {
   %tmp = extractelement <8 x i16> %x, i32 0
   %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx
   %tmp3 = extractelement <8 x i16> %x, i32 1
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1
   %tmp5 = extractelement <8 x i16> %x, i32 2
   %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2
   %tmp7 = extractelement <8 x i16> %x, i32 3
entry:
   %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %0, i32 1
   ret <2 x i32> %vecinit1.i
 }
 
 define <2 x i32> @test_concat_diff_v1i32_v1i32(i32 %a, i32 %b) {
 ; CHECK-LABEL: test_concat_diff_v1i32_v1i32:
 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
-; CHECK: mov {{v[0-9]+}}.s[1], w{{[0-9]+}}
+; CHECK: ins {{v[0-9]+}}.s[1], w{{[0-9]+}}
 entry:
   %c = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %a)
   %d = insertelement <2 x i32> undef, i32 %c, i32 0
   %e = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %b)
   %f = insertelement <2 x i32> undef, i32 %e, i32 0
   %h = shufflevector <2 x i32> %d, <2 x i32> %f, <2 x i32> <i32 0, i32 2>
   ret <2 x i32> %h
 }
 
 define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
   ret <16 x i8> %vecinit30
 }
 
 define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <8 x i8> %x, i32 0
   %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
   %vecext1 = extractelement <8 x i8> %x, i32 1
   %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
   %vecext3 = extractelement <8 x i8> %x, i32 2
   %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
   %vecext5 = extractelement <8 x i8> %x, i32 3
   %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 3
   %vecext7 = extractelement <8 x i8> %x, i32 4
   %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 4
   %vecext9 = extractelement <8 x i8> %x, i32 5
   %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 5
   %vecext11 = extractelement <8 x i8> %x, i32 6
   %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 6
   %vecext13 = extractelement <8 x i8> %x, i32 7
   %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 7
   %vecinit30 = shufflevector <16 x i8> %vecinit14, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
   ret <16 x i8> %vecinit30
 }
 
 define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <16 x i8> %x, i32 0
   %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
   %vecext1 = extractelement <16 x i8> %x, i32 1
   %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
   %vecext3 = extractelement <16 x i8> %x, i32 2
   %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
   %vecext5 = extractelement <16 x i8> %x, i32 3
entry:
   %vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 14
   %vecext29 = extractelement <8 x i8> %y, i32 7
   %vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 15
   ret <16 x i8> %vecinit30
 }
 
 define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <8 x i8> %x, i32 0
   %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
   %vecext1 = extractelement <8 x i8> %x, i32 1
   %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
   %vecext3 = extractelement <8 x i8> %x, i32 2
   %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
   %vecext5 = extractelement <8 x i8> %x, i32 3
entry:
   %vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 14
   %vecext29 = extractelement <8 x i8> %y, i32 7
   %vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 15
   ret <16 x i8> %vecinit30
 }
 
 define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
   ret <8 x i16> %vecinit14
 }
 
 define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <4 x i16> %x, i32 0
   %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
   %vecext1 = extractelement <4 x i16> %x, i32 1
   %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
   %vecext3 = extractelement <4 x i16> %x, i32 2
   %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
   %vecext5 = extractelement <4 x i16> %x, i32 3
   %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
   %vecinit14 = shufflevector <8 x i16> %vecinit6, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
   ret <8 x i16> %vecinit14
 }
 
 define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <8 x i16> %x, i32 0
   %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
   %vecext1 = extractelement <8 x i16> %x, i32 1
   %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
   %vecext3 = extractelement <8 x i16> %x, i32 2
   %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
   %vecext5 = extractelement <8 x i16> %x, i32 3
   %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
   %vecext7 = extractelement <4 x i16> %y, i32 0
   %vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 4
   %vecext9 = extractelement <4 x i16> %y, i32 1
   %vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 5
   %vecext11 = extractelement <4 x i16> %y, i32 2
   %vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 6
   %vecext13 = extractelement <4 x i16> %y, i32 3
   %vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 7
   ret <8 x i16> %vecinit14
 }
 
 define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <4 x i16> %x, i32 0
   %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
   %vecext1 = extractelement <4 x i16> %x, i32 1
   %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
   %vecext3 = extractelement <4 x i16> %x, i32 2
   %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
   %vecext5 = extractelement <4 x i16> %x, i32 3
   %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
   %vecext7 = extractelement <4 x i16> %y, i32 0
   %vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 4
   %vecext9 = extractelement <4 x i16> %y, i32 1
   %vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 5
   %vecext11 = extractelement <4 x i16> %y, i32 2
   %vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 6
   %vecext13 = extractelement <4 x i16> %y, i32 3
   %vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 7
   ret <8 x i16> %vecinit14
 }
 
 define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <2 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
   %vecext1 = extractelement <2 x i32> %x, i32 1
   %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
   %vecinit6 = shufflevector <4 x i32> %vecinit2, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <4 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
   %vecext1 = extractelement <4 x i32> %x, i32 1
   %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
   %vecext3 = extractelement <2 x i32> %y, i32 0
   %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
   %vecext5 = extractelement <2 x i32> %y, i32 1
   %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %vecext5, i32 3
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @test_concat_v4i32_v2i32_v2i32(<2 x i32> %x, <2 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecinit6 = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %vecinit6
 }
 
 define <2 x i64> @test_concat_v2i64_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y) #0 {
 ; CHECK-LABEL: test_concat_v2i64_v2i64_v2i64:
 ; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
entry:
   %vecext = extractelement <1 x i64> %x, i32 0
   %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
   %vecinit2 = shufflevector <2 x i64> %vecinit, <2 x i64> %y, <2 x i32> <i32 0, i32 2>
   ret <2 x i64> %vecinit2
 }
 
 define <2 x i64> @test_concat_v2i64_v2i64_v1i64(<2 x i64> %x, <1 x i64> %y) #0 {
 ; CHECK-LABEL: test_concat_v2i64_v2i64_v1i64:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <2 x i64> %x, i32 0
   %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
   %vecext1 = extractelement <1 x i64> %y, i32 0
   %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
   ret <2 x i64> %vecinit2
 }
 
 define <2 x i64> @test_concat_v2i64_v1i64_v1i64(<1 x i64> %x, <1 x i64> %y) #0 {
 ; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:
-; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <1 x i64> %x, i32 0
   %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
   %vecext1 = extractelement <1 x i64> %y, i32 0
   %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
   ret <2 x i64> %vecinit2
 }
 

test/CodeGen/AArch64/arm64-smaxv.ll

 entry:
   %vmaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a1)
   ret i32 %vmaxv.i
 }
 
 define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxv_s8_used_by_laneop:
 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
   ret <8 x i8> %2
 }
 
 define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxv_s16_used_by_laneop:
 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
   ret <4 x i16> %2
 }
 
 define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxv_s32_used_by_laneop:
 ; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a2)
   %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
   ret <2 x i32> %1
 }
 
 define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop:
 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
   ret <16 x i8> %2
 }
 
 define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxvq_s16_used_by_laneop:
 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
   ret <8 x i16> %2
 }
 
 define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxvq_s32_used_by_laneop:
 ; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a2)
   %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
   ret <4 x i32> %1
 }
 
 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
 declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
 declare i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32>)
 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
 

test/CodeGen/AArch64/arm64-sminv.ll

 entry:
   %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a1)
   ret i32 %vminv.i
 }
 
 define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vminv_s8_used_by_laneop:
 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
   ret <8 x i8> %2
 }
 
 define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vminv_s16_used_by_laneop:
 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
   ret <4 x i16> %2
 }
 
 define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vminv_s32_used_by_laneop:
 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
   %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
   ret <2 x i32> %1
 }
 
 define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
   ret <16 x i8> %2
 }
 
 define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
   ret <8 x i16> %2
 }
 
 define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
 ; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
   %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
   ret <4 x i32> %1
 }
 
 declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
 declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
 declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
 declare i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32>)
 declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
 declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
 

test/CodeGen/AArch64/arm64-stp.ll

 ; Check that a non-splat store that is storing a vector created by 4
 ; insertelements that is not a splat vector does not get split.
 define void @nosplat_v4i32(i32 %v, i32 *%p) {
 entry:
 
 ; CHECK-LABEL: nosplat_v4i32:
 ; CHECK: str w0,
 ; CHECK: ldr q[[REG1:[0-9]+]],
-; CHECK-DAG: mov v[[REG1]].s[1], w0
-; CHECK-DAG: mov v[[REG1]].s[2], w0
-; CHECK-DAG: mov v[[REG1]].s[3], w0
+; CHECK-DAG: ins v[[REG1]].s[1], w0
+; CHECK-DAG: ins v[[REG1]].s[2], w0
+; CHECK-DAG: ins v[[REG1]].s[3], w0
 ; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8
 ; CHECK: stp d[[REG1]], d[[REG2]], [x1]
 ; CHECK: ret
 
   %p17 = insertelement <4 x i32> undef, i32 %v, i32 %v
   %p18 = insertelement <4 x i32> %p17, i32 %v, i32 1
   %p19 = insertelement <4 x i32> %p18, i32 %v, i32 2
   %p20 = insertelement <4 x i32> %p19, i32 %v, i32 3
   %p21 = bitcast i32* %p to <4 x i32>*
   store <4 x i32> %p20, <4 x i32>* %p21, align 4
   ret void
 }
 
 ; Check that a non-splat store that is storing a vector created by 4
 ; insertelements that is not a splat vector does not get split.
 define void @nosplat2_v4i32(i32 %v, i32 *%p, <4 x i32> %vin) {
 entry:
 
 ; CHECK-LABEL: nosplat2_v4i32:
-; CHECK: mov v[[REG1]].s[1], w0
-; CHECK-DAG: mov v[[REG1]].s[2], w0
-; CHECK-DAG: mov v[[REG1]].s[3], w0
+; CHECK: ins v[[REG1]].s[1], w0
+; CHECK-DAG: ins v[[REG1]].s[2], w0
+; CHECK-DAG: ins v[[REG1]].s[3], w0
 ; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8
 ; CHECK: stp d[[REG1]], d[[REG2]], [x1]
 ; CHECK: ret
 
   %p18 = insertelement <4 x i32> %vin, i32 %v, i32 1
   %p19 = insertelement <4 x i32> %p18, i32 %v, i32 2
   %p20 = insertelement <4 x i32> %p19, i32 %v, i32 3
   %p21 = bitcast i32* %p to <4 x i32>*

test/CodeGen/AArch64/arm64-umaxv.ll

 return:
   %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
   ret i32 %retval.0
 }
 
 define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxv_u8_used_by_laneop:
 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
   ret <8 x i8> %2
 }
 
 define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxv_u16_used_by_laneop:
 ; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
   ret <4 x i16> %2
 }
 
 define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxv_u32_used_by_laneop:
 ; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2)
   %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
   ret <2 x i32> %1
 }
 
 define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop:
 ; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
   ret <16 x i8> %2
 }
 
 define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxvq_u16_used_by_laneop:
 ; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
   ret <8 x i16> %2
 }
 
 define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxvq_u32_used_by_laneop:
 ; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2)
   %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
   ret <4 x i32> %1
 }
 
 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone
 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone
 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone
 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone
 declare i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32>) nounwind readnone
 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>) nounwind readnone

test/CodeGen/AArch64/arm64-uminv.ll

 return:
   %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
   ret i32 %retval.0
 }
 
 define <8 x i8> @test_vminv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vminv_u8_used_by_laneop:
 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
   ret <8 x i8> %2
 }
 
 define <4 x i16> @test_vminv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vminv_u16_used_by_laneop:
 ; CHECK: uminv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
   ret <4 x i16> %2
 }
 
 define <2 x i32> @test_vminv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vminv_u32_used_by_laneop:
 ; CHECK: uminp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32> %a2)
   %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
   ret <2 x i32> %1
 }
 
 define <16 x i8> @test_vminvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vminvq_u8_used_by_laneop:
 ; CHECK: uminv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
   ret <16 x i8> %2
 }
 
 define <8 x i16> @test_vminvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vminvq_u16_used_by_laneop:
 ; CHECK: uminv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
   ret <8 x i16> %2
 }
 
 define <4 x i32> @test_vminvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vminvq_u32_used_by_laneop:
 ; CHECK: uminv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a2)
   %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
   ret <4 x i32> %1
 }
 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) nounwind readnone
 declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>) nounwind readnone
 declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>) nounwind readnone
 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) nounwind readnone
 declare i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32>) nounwind readnone
 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>) nounwind readnone

test/CodeGen/AArch64/arm64-vaddv.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -mcpu=cyclone | FileCheck %s
 
 define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
 ; CHECK-LABEL: test_vaddv_s8:
 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a1)
   %0 = trunc i32 %vaddv.i to i8
   ret i8 %0
 }
 
 define <8 x i8> @test_vaddv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vaddv_s8_used_by_laneop:
 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
   ret <8 x i8> %2
 }
 
 define signext i16 @test_vaddv_s16(<4 x i16> %a1) {
 ; CHECK-LABEL: test_vaddv_s16:
 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a1)
   %0 = trunc i32 %vaddv.i to i16
   ret i16 %0
 }
 
 define <4 x i16> @test_vaddv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vaddv_s16_used_by_laneop:
 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
   ret <4 x i16> %2
 }
 
 define i32 @test_vaddv_s32(<2 x i32> %a1) {
 ; CHECK-LABEL: test_vaddv_s32:
 ; 2 x i32 is not supported by the ISA, thus, this is a special case
 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a1)
   ret i32 %vaddv.i
 }
 
 define <2 x i32> @test_vaddv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vaddv_s32_used_by_laneop:
 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a2)
   %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
   ret <2 x i32> %1
 }
 
 define i64 @test_vaddv_s64(<2 x i64> %a1) {
 ; CHECK-LABEL: test_vaddv_s64:
 ; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
 ; CHECK-NEXT: fmov x0, [[REGNUM]]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a1)
   ret i64 %vaddv.i
 }
 
 define <2 x i64> @test_vaddv_s64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
 ; CHECK-LABEL: test_vaddv_s64_used_by_laneop:
 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a2)
   %1 = insertelement <2 x i64> %a1, i64 %0, i64 1
   ret <2 x i64> %1
 }
 
 define zeroext i8 @test_vaddv_u8(<8 x i8> %a1) {
 ; CHECK-LABEL: test_vaddv_u8:
 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1)
   %0 = trunc i32 %vaddv.i to i8
   ret i8 %0
 }
 
 define <8 x i8> @test_vaddv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vaddv_u8_used_by_laneop:
 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
   ret <8 x i8> %2
 }
 
entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a1)
   %0 = trunc i32 %vaddv.i to i16
   ret i16 %0
 }
 
 define <4 x i16> @test_vaddv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vaddv_u16_used_by_laneop:
 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
   ret <4 x i16> %2
 }
 

 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a1)
   ret i32 %vaddv.i
 }
 
 define <2 x i32> @test_vaddv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vaddv_u32_used_by_laneop:
 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a2)
   %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
   ret <2 x i32> %1
 }
 
 define float @test_vaddv_f32(<2 x float> %a1) {

 entry:
   %vaddv.i = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a1)
   ret i64 %vaddv.i
 }
 
 define <2 x i64> @test_vaddv_u64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
 ; CHECK-LABEL: test_vaddv_u64_used_by_laneop:
 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a2)
   %1 = insertelement <2 x i64> %a1, i64 %0, i64 1
   ret <2 x i64> %1
 }
 
 define <1 x i64> @test_vaddv_u64_to_vec(<2 x i64> %a1) {
entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a1)
   %0 = trunc i32 %vaddv.i to i8
   ret i8 %0
 }
 
 define <16 x i8> @test_vaddvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vaddvq_s8_used_by_laneop:
 ; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
   ret <16 x i8> %2
 }
 
 define signext i16 @test_vaddvq_s16(<8 x i16> %a1) {
 ; CHECK-LABEL: test_vaddvq_s16:
 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a1)
   %0 = trunc i32 %vaddv.i to i16
   ret i16 %0
 }
 
 define <8 x i16> @test_vaddvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vaddvq_s16_used_by_laneop:
 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
   ret <8 x i16> %2
 }
 
 define i32 @test_vaddvq_s32(<4 x i32> %a1) {
 ; CHECK-LABEL: test_vaddvq_s32:
 ; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
 ; CHECK-NEXT: fmov w0, [[REGNUM]]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a1)
   ret i32 %vaddv.i
 }
 
 define <4 x i32> @test_vaddvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vaddvq_s32_used_by_laneop:
 ; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a2)
   %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
   ret <4 x i32> %1
 }
 
 define zeroext i8 @test_vaddvq_u8(<16 x i8> %a1) {
 ; CHECK-LABEL: test_vaddvq_u8:
 ; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0
 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a1)
   %0 = trunc i32 %vaddv.i to i8
   ret i8 %0
 }
 
 define <16 x i8> @test_vaddvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vaddvq_u8_used_by_laneop:
 ; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a2)
   %1 = trunc i32 %0 to i8
   %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
   ret <16 x i8> %2
 }
 
 define zeroext i16 @test_vaddvq_u16(<8 x i16> %a1) {
 ; CHECK-LABEL: test_vaddvq_u16:
 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a1)
   %0 = trunc i32 %vaddv.i to i16
   ret i16 %0
 }
 
 define <8 x i16> @test_vaddvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vaddvq_u16_used_by_laneop:
 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a2)
   %1 = trunc i32 %0 to i16
   %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
   ret <8 x i16> %2
 }
 
 define i32 @test_vaddvq_u32(<4 x i32> %a1) {
 ; CHECK-LABEL: test_vaddvq_u32:
 ; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
 ; CHECK-NEXT: fmov [[FMOVRES:w[0-9]+]], [[REGNUM]]
 ; CHECK-NEXT: ret
 entry:
   %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a1)
   ret i32 %vaddv.i
 }
 
 define <4 x i32> @test_vaddvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vaddvq_u32_used_by_laneop:
 ; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a2)
   %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
   ret <4 x i32> %1
 }
 
 declare i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32>)

test/CodeGen/AArch64/arm64-vcombine.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
 ; LowerCONCAT_VECTORS() was reversing the order of two parts.
 ; rdar://11558157
 ; rdar://11559553
 define <16 x i8> @test(<16 x i8> %q0, <16 x i8> %q1, i8* nocapture %dest) nounwind {
 entry:
 ; CHECK-LABEL: test:
-; CHECK: mov.d v0[1], v1[0]
+; CHECK: ins.d v0[1], v1[0]
   %0 = bitcast <16 x i8> %q0 to <2 x i64>
   %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> zeroinitializer
   %1 = bitcast <16 x i8> %q1 to <2 x i64>
   %shuffle.i4 = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer
   %shuffle.i3 = shufflevector <1 x i64> %shuffle.i, <1 x i64> %shuffle.i4, <2 x i32> <i32 0, i32 1>
   %2 = bitcast <2 x i64> %shuffle.i3 to <16 x i8>
   ret <16 x i8> %2
 }

test/CodeGen/AArch64/arm64-vector-insertion.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -mcpu=generic -aarch64-neon-syntax=apple | FileCheck %s
 
 define void @test0f(float* nocapture %x, float %a) #0 {
 entry:
   %0 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %a, i32 0
   %1 = bitcast float* %x to <4 x float>*
   store <4 x float> %0, <4 x float>* %1, align 16
   ret void
 
   ; CHECK-LABEL: test0f
   ; CHECK: movi.2d v[[TEMP:[0-9]+]], #0000000000000000
-  ; CHECK: mov.s v[[TEMP]][0], v{{[0-9]+}}[0]
+  ; CHECK: ins.s v[[TEMP]][0], v{{[0-9]+}}[0]
   ; CHECK: str q[[TEMP]], [x0]
   ; CHECK: ret
 
 
 }
 
 
 define void @test1f(float* nocapture %x, float %a) #0 {
 entry:
   %0 = insertelement <4 x float> <float undef, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, float %a, i32 0
   %1 = bitcast float* %x to <4 x float>*
   store <4 x float> %0, <4 x float>* %1, align 16
   ret void
 
   ; CHECK-LABEL: test1f
   ; CHECK: fmov  s[[TEMP:[0-9]+]], #1.0000000
   ; CHECK: dup.4s  v[[TEMP2:[0-9]+]], v[[TEMP]][0]
-  ; CHECK: mov.s v[[TEMP2]][0], v0[0]
+  ; CHECK: ins.s v[[TEMP2]][0], v0[0]
   ; CHECK: str q[[TEMP2]], [x0]
   ; CHECK: ret
 }

test/CodeGen/AArch64/bitreverse.ll

 ; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s
 
 ; These tests just check that the plumbing is in place for @llvm.bitreverse.
 
 declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
 
 define <2 x i16> @f(<2 x i16> %a) {
 ; CHECK-LABEL: f:
 ; CHECK: fmov [[REG1:w[0-9]+]], s0
 ; CHECK-DAG: rbit [[REG2:w[0-9]+]], [[REG1]]
 ; CHECK-DAG: fmov s0, [[REG2]]
 ; CHECK-DAG: mov [[REG3:w[0-9]+]], v0.s[1]
 ; CHECK-DAG: rbit [[REG4:w[0-9]+]], [[REG3]]
-; CHECK-DAG: mov v0.s[1], [[REG4]]
+; CHECK-DAG: ins v0.s[1], [[REG4]]
 ; CHECK-DAG: ushr v0.2s, v0.2s, #16
   %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
   ret <2 x i16> %b
 }
 
 declare i8 @llvm.bitreverse.i8(i8) readnone
 
 define i8 @g(i8 %a) {

test/CodeGen/AArch64/concat_vector-scalar-combine.ll

; CHECK-NEXT: ret
   %0 = bitcast i32 %x to <2 x i16>
   %1 = shufflevector <2 x i16> %0, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 0, i32 1, i32 0, i32 1>
   ret <8 x i16> %1
 }
 
 define <8 x i8> @test_concat_scalars_2x_v2i8_to_v8i8(i32 %x, i32 %y) #0 {
 entry:
 ; CHECK-LABEL: test_concat_scalars_2x_v2i8_to_v8i8:
-; CHECK-NEXT: mov.h v0[0], w0
-; CHECK-NEXT: mov.h v0[1], w1
-; CHECK-NEXT: mov.h v0[3], w1
+; CHECK-NEXT: ins.h v0[0], w0
+; CHECK-NEXT: ins.h v0[1], w1
+; CHECK-NEXT: ins.h v0[3], w1
 ; CHECK-NEXT: ret
   %tx = trunc i32 %x to i16
   %ty = trunc i32 %y to i16
   %bx = bitcast i16 %tx to <2 x i8>
   %by = bitcast i16 %ty to <2 x i8>
   %r = shufflevector <2 x i8> %bx, <2 x i8> %by, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 2, i32 3>
   ret <8 x i8> %r
 }
 
 define <8 x i8> @test_concat_scalars_2x_v4i8_to_v8i8_dup(i32 %x, i32 %y) #0 {
 entry:
 ; CHECK-LABEL: test_concat_scalars_2x_v4i8_to_v8i8_dup:
 ; CHECK-NEXT: fmov s0, w1
-; CHECK-NEXT: mov.s v0[1], w0
+; CHECK-NEXT: ins.s v0[1], w0
 ; CHECK-NEXT: ret
   %bx = bitcast i32 %x to <4 x i8>
   %by = bitcast i32 %y to <4 x i8>
   %r = shufflevector <4 x i8> %bx, <4 x i8> %by, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
   ret <8 x i8> %r
 }
 
 define <8 x i16> @test_concat_scalars_2x_v2i16_to_v8i16_dup(i32 %x, i32 %y) #0 {
 entry:
 ; CHECK-LABEL: test_concat_scalars_2x_v2i16_to_v8i16_dup:
 ; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: mov.s v0[1], w1
-; CHECK-NEXT: mov.s v0[2], w1
-; CHECK-NEXT: mov.s v0[3], w0
+; CHECK-NEXT: ins.s v0[1], w1
+; CHECK-NEXT: ins.s v0[2], w1
+; CHECK-NEXT: ins.s v0[3], w0
 ; CHECK-NEXT: ret
   %bx = bitcast i32 %x to <2 x i16>
   %by = bitcast i32 %y to <2 x i16>
   %r = shufflevector <2 x i16> %bx, <2 x i16> %by, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1>
   ret <8 x i16> %r
 }
 
 ; Also make sure we minimize bitcasts.
 
 ; This is a pretty artificial testcase: make sure we bitcast to floating-point
 ; if any of the scalars is floating-point.
 define <8 x i8> @test_concat_scalars_mixed_2x_v2i8_to_v8i8(float %dummy, i32 %x, half %y) #0 {
 entry:
 ; CHECK-LABEL: test_concat_scalars_mixed_2x_v2i8_to_v8i8:
 ; CHECK-NEXT: fmov s[[X:[0-9]+]], w0
-; CHECK-NEXT: mov.h v0[0], v[[X]][0]
-; CHECK-NEXT: mov.h v0[1], v1[0]
-; CHECK-NEXT: mov.h v0[2], v[[X]][0]
-; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ins.h v0[0], v[[X]][0]
+; CHECK-NEXT: ins.h v0[1], v1[0]
+; CHECK-NEXT: ins.h v0[2], v[[X]][0]
+; CHECK-NEXT: ins.h v0[3], v1[0]
 ; CHECK-NEXT: ret
   %t = trunc i32 %x to i16
   %0 = bitcast i16 %t to <2 x i8>
   %y0 = bitcast half %y to <2 x i8>
   %1 = shufflevector <2 x i8> %0, <2 x i8> %y0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
   ret <8 x i8> %1
 }
 
 define <2 x float> @test_concat_scalars_fp_2x_v2i8_to_v8i8(float %dummy, half %x, half %y) #0 {
 entry:
 ; CHECK-LABEL: test_concat_scalars_fp_2x_v2i8_to_v8i8:
-; CHECK-NEXT: mov.h v0[0], v1[0]
-; CHECK-NEXT: mov.h v0[1], v2[0]
-; CHECK-NEXT: mov.h v0[2], v1[0]
-; CHECK-NEXT: mov.h v0[3], v2[0]
+; CHECK-NEXT: ins.h v0[0], v1[0]
+; CHECK-NEXT: ins.h v0[1], v2[0]
+; CHECK-NEXT: ins.h v0[2], v1[0]
+; CHECK-NEXT: ins.h v0[3], v2[0]
 ; CHECK-NEXT: ret
   %0 = bitcast half %x to <2 x i8>
   %y0 = bitcast half %y to <2 x i8>
   %1 = shufflevector <2 x i8> %0, <2 x i8> %y0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
   %2 = bitcast <8 x i8> %1 to <2 x float>
   ret <2 x float> %2
 }
 

test/CodeGen/AArch64/fp16-v16-instructions.ll

 ; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
 
 
 define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {
 ; CHECK-LABEL: sitofp_i32:
 ; CHECK-DAG: scvtf [[S0:v[0-9]+\.4s]], v0.4s
 ; CHECK-DAG: scvtf [[S1:v[0-9]+\.4s]], v1.4s
 ; CHECK-DAG: scvtf [[S2:v[0-9]+\.4s]], v2.4s
 ; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s
 ; CHECK-DAG: fcvtn v0.4h, [[S0]]
 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
-; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
+; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
 
   %1 = sitofp <16 x i32> %a to <16 x half>
   ret <16 x half> %1
 }
 
 
 define <16 x half> @sitofp_i64(<16 x i64> %a) #0 {
 ; CHECK-LABEL: sitofp_i64:

 ; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
 
 ; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
 ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
 ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
 ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
-; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
+; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
 
   %1 = sitofp <16 x i64> %a to <16 x half>
   ret <16 x half> %1
 }
 
 
 define <16 x half> @uitofp_i32(<16 x i32> %a) #0 {
 ; CHECK-LABEL: uitofp_i32:
 ; CHECK-DAG: ucvtf [[S0:v[0-9]+\.4s]], v0.4s
 ; CHECK-DAG: ucvtf [[S1:v[0-9]+\.4s]], v1.4s
 ; CHECK-DAG: ucvtf [[S2:v[0-9]+\.4s]], v2.4s
 ; CHECK-DAG: ucvtf [[S3:v[0-9]+\.4s]], v3.4s
 ; CHECK-DAG: fcvtn v0.4h, [[S0]]
 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
-; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
+; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
 
   %1 = uitofp <16 x i32> %a to <16 x half>
   ret <16 x half> %1
 }
 
 
 define <16 x half> @uitofp_i64(<16 x i64> %a) #0 {
 ; CHECK-LABEL: uitofp_i64:

 ; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
 
 ; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
 ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
 ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
 ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
-; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
+; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
 
   %1 = uitofp <16 x i64> %a to <16 x half>
   ret <16 x half> %1
 }
 
 attributes #0 = { nounwind }

test/CodeGen/AArch64/fp16-v4-instructions.ll

 }
 
 define <4 x half> @d_to_h(<4 x double> %a) {
 ; CHECK-LABEL: d_to_h:
 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
-; CHECK-DAG: mov
-; CHECK-DAG: mov
-; CHECK-DAG: mov
-; CHECK-DAG: mov
+; CHECK-DAG: ins
+; CHECK-DAG: ins
+; CHECK-DAG: ins
+; CHECK-DAG: ins
   %1 = fptrunc <4 x double> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x float> @h_to_s(<4 x half> %a) {
 ; CHECK-LABEL: h_to_s:
 ; CHECK: fcvtl v0.4s, v0.4h
   %1 = fpext <4 x half> %a to <4 x float>
   ret <4 x float> %1
 }
 
 define <4 x double> @h_to_d(<4 x half> %a) {
 ; CHECK-LABEL: h_to_d:
 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
-; CHECK-DAG: mov
-; CHECK-DAG: mov
-; CHECK-DAG: mov
-; CHECK-DAG: mov
+; CHECK-DAG: ins
+; CHECK-DAG: ins
+; CHECK-DAG: ins
+; CHECK-DAG: ins
   %1 = fpext <4 x half> %a to <4 x double>
   ret <4 x double> %1
 }
 
 define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {
 ; CHECK-LABEL: bitcast_i_to_h:
 ; CHECK: mov v0.16b, v1.16b
   %2 = bitcast <4 x i16> %a to <4 x half>

test/CodeGen/AArch64/fp16-v8-instructions.ll

; CHECK: str q0, [x0]
   store <8 x half> %b, <8 x half>* %a, align 4
   ret void
 }
 
 define <8 x half> @s_to_h(<8 x float> %a) {
 ; CHECK-LABEL: s_to_h:
 ; CHECK-DAG: fcvtn v0.4h, v0.4s
 ; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s
-; CHECK: mov v0.d[1], [[REG]].d[0]
+; CHECK: ins v0.d[1], [[REG]].d[0]
   %1 = fptrunc <8 x float> %a to <8 x half>
   ret <8 x half> %1
 }
 
 define <8 x half> @d_to_h(<8 x double> %a) {
 ; CHECK-LABEL: d_to_h:
 ; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
 ; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
 ; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
 ; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: ins v{{[0-9]+}}.h
+; CHECK-DAG: ins v{{[0-9]+}}.h
+; CHECK-DAG: ins v{{[0-9]+}}.h
+; CHECK-DAG: ins v{{[0-9]+}}.h
+; CHECK-DAG: ins v{{[0-9]+}}.h
+; CHECK-DAG: ins v{{[0-9]+}}.h
+; CHECK-DAG: ins v{{[0-9]+}}.h
+; CHECK-DAG: ins v{{[0-9]+}}.h
   %1 = fptrunc <8 x double> %a to <8 x half>
   ret <8 x half> %1
 }
 
 define <8 x float> @h_to_s(<8 x half> %a) {
 ; CHECK-LABEL: h_to_s:
 ; CHECK: fcvtl2 v1.4s, v0.8h
 ; CHECK: fcvtl v0.4s, v0.4h
   %1 = fpext <8 x half> %a to <8 x float>
   ret <8 x float> %1
 }
 
 define <8 x double> @h_to_d(<8 x half> %a) {
 ; CHECK-LABEL: h_to_d:
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
-; CHECK-DAG: mov
-; CHECK-DAG: mov
-; CHECK-DAG: mov
-; CHECK-DAG: mov
+; CHECK-DAG: ins
+; CHECK-DAG: ins
+; CHECK-DAG: ins
+; CHECK-DAG: ins
   %1 = fpext <8 x half> %a to <8 x double>
   ret <8 x double> %1
 }
 
 
 define <8 x half> @bitcast_i_to_h(float, <8 x i16> %a) {
 ; CHECK-LABEL: bitcast_i_to_h:
 ; CHECK: mov v0.16b, v1.16b

 ; CHECK-LABEL: sitofp_i8:
 ; CHECK-NEXT: sshll v[[REG1:[0-9]+]].8h, v0.8b, #0
 ; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
 ; CHECK-NEXT: sshll  [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
 ; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: mov v0.d[1], v[[LOREG]].d[0]
+; CHECK: ins v0.d[1], v[[LOREG]].d[0]
   %1 = sitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-LABEL: sitofp_i16:
 ; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
 ; CHECK-NEXT: sshll  [[HI:v[0-9]+\.4s]], v0.4h, #0
 ; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: mov v0.d[1], v[[LOREG]].d[0]
+; CHECK: ins v0.d[1], v[[LOREG]].d[0]
   %1 = sitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {
 ; CHECK-LABEL: sitofp_i32:
 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
-; CHECK: mov v0.d[1], v[[REG]].d[0]
+; CHECK: ins v0.d[1], v[[REG]].d[0]
   %1 = sitofp <8 x i32> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @sitofp_i64(<8 x i64> %a) #0 {
 ; CHECK-LABEL: sitofp_i64:
 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d

 ; CHECK-LABEL: uitofp_i8:
 ; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
 ; CHECK-NEXT: ushll  [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
 ; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: mov v0.d[1], v[[LOREG]].d[0]
+; CHECK: ins v0.d[1], v[[LOREG]].d[0]
   %1 = uitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-LABEL: uitofp_i16:
 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
 ; CHECK-NEXT: ushll  [[HI:v[0-9]+\.4s]], v0.4h, #0
 ; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: mov v0.d[1], v[[LOREG]].d[0]
+; CHECK: ins v0.d[1], v[[LOREG]].d[0]
   %1 = uitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @uitofp_i32(<8 x i32> %a) #0 {
 ; CHECK-LABEL: uitofp_i32:
 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
-; CHECK: mov v0.d[1], v[[REG]].d[0]
+; CHECK: ins v0.d[1], v[[REG]].d[0]
   %1 = uitofp <8 x i32> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @uitofp_i64(<8 x i64> %a) #0 {
 ; CHECK-LABEL: uitofp_i64:
 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d

test/CodeGen/AArch64/fp16-vector-shuffle.ll

entry:
   ret <8 x half> %3
 }
 
 ; float16x4_t lane_64_64(float16x4_t a, float16x4_t b) {
 ;  return vcopy_lane_s16(a, 1, b, 2);
 ; }
 define <4 x half> @lane_64_64(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-LABEL: lane_64_64:
-; CHECK: mov
+; CHECK: ins
 entry:
   %0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
   ret <4 x half> %0
 }
 
 ; float16x8_t lane_128_64(float16x8_t a, float16x4_t b) {
 ;   return vcopyq_lane_s16(a, 1, b, 2);
 ; }
 define <8 x half> @lane_128_64(<8 x half> %a, <4 x half> %b) #0 {
 ; CHECK-LABEL: lane_128_64:
-; CHECK: mov
+; CHECK: ins
 entry:
   %0 = bitcast <4 x half> %b to <4 x i16>
   %vget_lane = extractelement <4 x i16> %0, i32 2
   %1 = bitcast <8 x half> %a to <8 x i16>
   %vset_lane = insertelement <8 x i16> %1, i16 %vget_lane, i32 1
   %2 = bitcast <8 x i16> %vset_lane to <8 x half>
   ret <8 x half> %2
 }
 
 ; float16x4_t lane_64_128(float16x4_t a, float16x8_t b) {
 ;   return vcopy_laneq_s16(a, 3, b, 5);
 ; }
 define <4 x half> @lane_64_128(<4 x half> %a, <8 x half> %b) #0 {
 ; CHECK-LABEL: lane_64_128:
-; CHECK: mov
+; CHECK: ins
 entry:
   %0 = bitcast <8 x half> %b to <8 x i16>
   %vgetq_lane = extractelement <8 x i16> %0, i32 5
   %1 = bitcast <4 x half> %a to <4 x i16>
   %vset_lane = insertelement <4 x i16> %1, i16 %vgetq_lane, i32 3
   %2 = bitcast <4 x i16> %vset_lane to <4 x half>
   ret <4 x half> %2
 }
 
 ; float16x8_t lane_128_128(float16x8_t a, float16x8_t b) {
 ;   return vcopyq_laneq_s16(a, 3, b, 5);
 ; }
 define <8 x half> @lane_128_128(<8 x half> %a, <8 x half> %b) #0 {
 ; CHECK-LABEL: lane_128_128:
-; CHECK: mov
+; CHECK: ins
 entry:
   %0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>
   ret <8 x half> %0
 }
 
 ; float16x4_t ext_64(float16x4_t a, float16x4_t b) {
 ;   return vext_s16(a, b, 3);
 ; }
; CHECK: dup
   %shuffle = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
   ret <8 x half> %shuffle
 }
 
 ; float16x8_t vcombine(float16x4_t a, float16x4_t b) { return vcombine_f16(a, b); }
 define <8 x half> @vcombine(<4 x half> %a, <4 x half> %b) #0 {
 entry:
 ; CHECK-LABEL: vcombine:
-; CHECK: mov
+; CHECK: ins
   %shuffle.i = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x half> %shuffle.i
 }
 
 ; float16x4_t get_high(float16x8_t a) { return vget_high_f16(a); }
 define <4 x half> @get_high(<8 x half> %a) #0 {
 ; CHECK-LABEL: get_high:
 ; CHECK: ext
entry:
   %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x half> %shuffle.i
 }
 
 ; float16x4_t set_lane_64(float16x4_t a, __fp16 b) { return vset_lane_f16(b, a, 2); }
 define <4 x half> @set_lane_64(<4 x half> %a, half %b) #0 {
 ; CHECK-LABEL: set_lane_64:
 ; CHECK: fmov
-; CHECK: mov
+; CHECK: ins
 entry:
   %0 = bitcast half %b to i16
   %1 = bitcast <4 x half> %a to <4 x i16>
   %vset_lane = insertelement <4 x i16> %1, i16 %0, i32 2
   %2 = bitcast <4 x i16> %vset_lane to <4 x half>
   ret <4 x half> %2
 }
 
 
 ; float16x8_t set_lane_128(float16x8_t a, __fp16 b) { return vsetq_lane_f16(b, a, 2); }
 define <8 x half> @set_lane_128(<8 x half> %a, half %b) #0 {
 ; CHECK-LABEL: set_lane_128:
 ; CHECK: fmov
-; CHECK: mov
+; CHECK: ins
 entry:
   %0 = bitcast half %b to i16
   %1 = bitcast <8 x half> %a to <8 x i16>
   %vset_lane = insertelement <8 x i16> %1, i16 %0, i32 2
   %2 = bitcast <8 x i16> %vset_lane to <8 x half>
   ret <8 x half> %2
 }
 

test/CodeGen/AArch64/vector-fcopysign.ll

 ; CHECK-NEXT:    bit.16b v0, v5, v4
 ; CHECK-NEXT:    fcvt s5, d2
 ; CHECK-NEXT:    bit.16b v6, v5, v4
 ; CHECK-NEXT:    mov d1, v1[1]
 ; CHECK-NEXT:    fcvt s1, d1
 ; CHECK-NEXT:    bit.16b v3, v1, v4
 ; CHECK-NEXT:    mov d1, v2[1]
 ; CHECK-NEXT:    fcvt s1, d1
-; CHECK-NEXT:    mov.s v0[1], v3[0]
-; CHECK-NEXT:    mov.s v0[2], v6[0]
+; CHECK-NEXT:    ins.s v0[1], v3[0]
+; CHECK-NEXT:    ins.s v0[2], v6[0]
 ; CHECK-NEXT:    bit.16b v7, v1, v4
-; CHECK-NEXT:    mov.s v0[3], v7[0]
+; CHECK-NEXT:    ins.s v0[3], v7[0]
 ; CHECK-NEXT:    ret
   %tmp0 = fptrunc <4 x double> %b to <4 x float>
   %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %tmp0)
   ret <4 x float> %r
 }
 
 declare <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) #0
 

test/MC/AArch64/arm64-advsimd.s

; CHECK: mov.d  x17, v19[0]             ; encoding: [0x71,0x3e,0x08,0x4e]
   ins.h v2[1], w5
   ins.b v2[1], w5
 
   ins   v2.d[1], x5
   ins   v2.s[1], w5
   ins   v2.h[1], w5
   ins   v2.b[1], w5
 
-; CHECK: mov.d v2[1], x5             ; encoding: [0xa2,0x1c,0x18,0x4e]
-; CHECK: mov.s v2[1], w5             ; encoding: [0xa2,0x1c,0x0c,0x4e]
-; CHECK: mov.h v2[1], w5             ; encoding: [0xa2,0x1c,0x06,0x4e]
-; CHECK: mov.b v2[1], w5             ; encoding: [0xa2,0x1c,0x03,0x4e]
-
-; CHECK: mov.d v2[1], x5             ; encoding: [0xa2,0x1c,0x18,0x4e]
-; CHECK: mov.s v2[1], w5             ; encoding: [0xa2,0x1c,0x0c,0x4e]
-; CHECK: mov.h v2[1], w5             ; encoding: [0xa2,0x1c,0x06,0x4e]
-; CHECK: mov.b v2[1], w5             ; encoding: [0xa2,0x1c,0x03,0x4e]
+; CHECK: ins.d v2[1], x5             ; encoding: [0xa2,0x1c,0x18,0x4e]
+; CHECK: ins.s v2[1], w5             ; encoding: [0xa2,0x1c,0x0c,0x4e]
+; CHECK: ins.h v2[1], w5             ; encoding: [0xa2,0x1c,0x06,0x4e]
+; CHECK: ins.b v2[1], w5             ; encoding: [0xa2,0x1c,0x03,0x4e]
+
+; CHECK: ins.d v2[1], x5             ; encoding: [0xa2,0x1c,0x18,0x4e]
+; CHECK: ins.s v2[1], w5             ; encoding: [0xa2,0x1c,0x0c,0x4e]
+; CHECK: ins.h v2[1], w5             ; encoding: [0xa2,0x1c,0x06,0x4e]
+; CHECK: ins.b v2[1], w5             ; encoding: [0xa2,0x1c,0x03,0x4e]
 
   ins.d v2[1], v15[1]
   ins.s v2[1], v15[1]
   ins.h v2[1], v15[1]
   ins.b v2[1], v15[1]
 
   ins   v2.d[1], v15.d[0]
   ins   v2.s[3], v15.s[2]
   ins   v2.h[7], v15.h[3]
   ins   v2.b[10], v15.b[5]
 
-; CHECK: mov.d v2[1], v15[1]         ; encoding: [0xe2,0x45,0x18,0x6e]
-; CHECK: mov.s v2[1], v15[1]         ; encoding: [0xe2,0x25,0x0c,0x6e]
-; CHECK: mov.h v2[1], v15[1]         ; encoding: [0xe2,0x15,0x06,0x6e]
-; CHECK: mov.b v2[1], v15[1]         ; encoding: [0xe2,0x0d,0x03,0x6e]
-
-; CHECK: mov.d v2[1], v15[0]         ; encoding: [0xe2,0x05,0x18,0x6e]
-; CHECK: mov.s v2[3], v15[2]         ; encoding: [0xe2,0x45,0x1c,0x6e]
-; CHECK: mov.h v2[7], v15[3]         ; encoding: [0xe2,0x35,0x1e,0x6e]
-; CHECK: mov.b v2[10], v15[5]        ; encoding: [0xe2,0x2d,0x15,0x6e]
+; CHECK: ins.d v2[1], v15[1]         ; encoding: [0xe2,0x45,0x18,0x6e]
+; CHECK: ins.s v2[1], v15[1]         ; encoding: [0xe2,0x25,0x0c,0x6e]
+; CHECK: ins.h v2[1], v15[1]         ; encoding: [0xe2,0x15,0x06,0x6e]
+; CHECK: ins.b v2[1], v15[1]         ; encoding: [0xe2,0x0d,0x03,0x6e]
+
+; CHECK: ins.d v2[1], v15[0]         ; encoding: [0xe2,0x05,0x18,0x6e]
+; CHECK: ins.s v2[3], v15[2]         ; encoding: [0xe2,0x45,0x1c,0x6e]
+; CHECK: ins.h v2[7], v15[3]         ; encoding: [0xe2,0x35,0x1e,0x6e]
+; CHECK: ins.b v2[10], v15[5]        ; encoding: [0xe2,0x2d,0x15,0x6e]
 
 ; MOV aliases for the above INS instructions.
   mov.d v2[1], x5
   mov.s v3[1], w6
   mov.h v4[1], w7
   mov.b v5[1], w8
 
   mov   v9.d[1], x2
   mov   v8.s[1], w3
   mov   v7.h[1], w4
   mov   v6.b[1], w5
 
   mov.d v1[1], v10[1]
   mov.s v2[1], v11[1]
   mov.h v7[1], v12[1]
   mov.b v8[1], v15[1]
 
   mov   v2.d[1], v15.d[0]
   mov   v7.s[3], v16.s[2]
   mov   v8.h[7], v17.h[3]
   mov   v9.b[10], v18.b[5]
 
-; CHECK: mov.d  v2[1], x5               ; encoding: [0xa2,0x1c,0x18,0x4e]
-; CHECK: mov.s  v3[1], w6               ; encoding: [0xc3,0x1c,0x0c,0x4e]
-; CHECK: mov.h  v4[1], w7               ; encoding: [0xe4,0x1c,0x06,0x4e]
-; CHECK: mov.b  v5[1], w8               ; encoding: [0x05,0x1d,0x03,0x4e]
-; CHECK: mov.d  v9[1], x2               ; encoding: [0x49,0x1c,0x18,0x4e]
-; CHECK: mov.s  v8[1], w3               ; encoding: [0x68,0x1c,0x0c,0x4e]
-; CHECK: mov.h  v7[1], w4               ; encoding: [0x87,0x1c,0x06,0x4e]
-; CHECK: mov.b  v6[1], w5               ; encoding: [0xa6,0x1c,0x03,0x4e]
-; CHECK: mov.d  v1[1], v10[1]           ; encoding: [0x41,0x45,0x18,0x6e]
-; CHECK: mov.s  v2[1], v11[1]           ; encoding: [0x62,0x25,0x0c,0x6e]
-; CHECK: mov.h  v7[1], v12[1]           ; encoding: [0x87,0x15,0x06,0x6e]
-; CHECK: mov.b  v8[1], v15[1]           ; encoding: [0xe8,0x0d,0x03,0x6e]
-; CHECK: mov.d  v2[1], v15[0]           ; encoding: [0xe2,0x05,0x18,0x6e]
-; CHECK: mov.s  v7[3], v16[2]           ; encoding: [0x07,0x46,0x1c,0x6e]
-; CHECK: mov.h  v8[7], v17[3]           ; encoding: [0x28,0x36,0x1e,0x6e]
-; CHECK: mov.b  v9[10], v18[5]          ; encoding: [0x49,0x2e,0x15,0x6e]
+; CHECK: ins.d  v2[1], x5               ; encoding: [0xa2,0x1c,0x18,0x4e]
+; CHECK: ins.s  v3[1], w6               ; encoding: [0xc3,0x1c,0x0c,0x4e]
+; CHECK: ins.h  v4[1], w7               ; encoding: [0xe4,0x1c,0x06,0x4e]
+; CHECK: ins.b  v5[1], w8               ; encoding: [0x05,0x1d,0x03,0x4e]
+; CHECK: ins.d  v9[1], x2               ; encoding: [0x49,0x1c,0x18,0x4e]
+; CHECK: ins.s  v8[1], w3               ; encoding: [0x68,0x1c,0x0c,0x4e]
+; CHECK: ins.h  v7[1], w4               ; encoding: [0x87,0x1c,0x06,0x4e]
+; CHECK: ins.b  v6[1], w5               ; encoding: [0xa6,0x1c,0x03,0x4e]
+; CHECK: ins.d  v1[1], v10[1]           ; encoding: [0x41,0x45,0x18,0x6e]
+; CHECK: ins.s  v2[1], v11[1]           ; encoding: [0x62,0x25,0x0c,0x6e]
+; CHECK: ins.h  v7[1], v12[1]           ; encoding: [0x87,0x15,0x06,0x6e]
+; CHECK: ins.b  v8[1], v15[1]           ; encoding: [0xe8,0x0d,0x03,0x6e]
+; CHECK: ins.d  v2[1], v15[0]           ; encoding: [0xe2,0x05,0x18,0x6e]
+; CHECK: ins.s  v7[3], v16[2]           ; encoding: [0x07,0x46,0x1c,0x6e]
+; CHECK: ins.h  v8[7], v17[3]           ; encoding: [0x28,0x36,0x1e,0x6e]
+; CHECK: ins.b  v9[10], v18[5]          ; encoding: [0x49,0x2e,0x15,0x6e]
 
 
   and.8b  v0, v0, v0
   and.16b v0, v0, v0
 
 ; CHECK: and.8b  v0, v0, v0          ; encoding: [0x00,0x1c,0x20,0x0e]
 ; CHECK: and.16b v0, v0, v0          ; encoding: [0x00,0x1c,0x20,0x4e]
 

test/MC/Disassembler/AArch64/arm64-advsimd.txt

 0xa2 0x1c 0x06 0x4e
 0xa2 0x1c 0x03 0x4e
 
 0xa2 0x1c 0x18 0x4e
 0xa2 0x1c 0x0c 0x4e
 0xa2 0x1c 0x06 0x4e
 0xa2 0x1c 0x03 0x4e
 
-# CHECK: mov.d v2[1], x5
-# CHECK: mov.s v2[1], w5
-# CHECK: mov.h v2[1], w5
-# CHECK: mov.b v2[1], w5
-
-# CHECK: mov.d v2[1], x5
-# CHECK: mov.s v2[1], w5
-# CHECK: mov.h v2[1], w5
-# CHECK: mov.b v2[1], w5
+# CHECK: ins.d v2[1], x5
+# CHECK: ins.s v2[1], w5
+# CHECK: ins.h v2[1], w5
+# CHECK: ins.b v2[1], w5
+
+# CHECK: ins.d v2[1], x5
+# CHECK: ins.s v2[1], w5
+# CHECK: ins.h v2[1], w5
+# CHECK: ins.b v2[1], w5
 
 0xe2 0x45 0x18 0x6e
 0xe2 0x25 0x0c 0x6e
 0xe2 0x15 0x06 0x6e
 0xe2 0x0d 0x03 0x6e
 
 0xe2 0x05 0x18 0x6e
 0xe2 0x45 0x1c 0x6e
 0xe2 0x35 0x1e 0x6e
 0xe2 0x2d 0x15 0x6e
 
-# CHECK: mov.d v2[1], v15[1]
-# CHECK: mov.s v2[1], v15[1]
-# CHECK: mov.h v2[1], v15[1]
-# CHECK: mov.b v2[1], v15[1]
-
-# CHECK: mov.d v2[1], v15[0]
-# CHECK: mov.s v2[3], v15[2]
-# CHECK: mov.h v2[7], v15[3]
-# CHECK: mov.b v2[10], v15[5]
+# CHECK: ins.d v2[1], v15[1]
+# CHECK: ins.s v2[1], v15[1]
+# CHECK: ins.h v2[1], v15[1]
+# CHECK: ins.b v2[1], v15[1]
+
+# CHECK: ins.d v2[1], v15[0]
+# CHECK: ins.s v2[3], v15[2]
+# CHECK: ins.h v2[7], v15[3]
+# CHECK: ins.b v2[10], v15[5]
 
 # INS/DUP (non-standard)
 0x60 0x0c 0x08 0x4e
 0x60 0x0c 0x0c 0x4e
 0x60 0x0c 0x0c 0x0e
 0x60 0x0c 0x0e 0x4e
 0x60 0x0c 0x0e 0x0e
 0x60 0x0c 0x0f 0x4e

 0xe2 0x15 0x06 0x6e
 0xe2 0x0d 0x03 0x6e
 
 0xe2 0x05 0x18 0x6e
 0xe2 0x55 0x1c 0x6e
 0xe2 0x35 0x1e 0x6e
 0xe2 0x2d 0x15 0x6e
 
-# CHECK: mov.d v2[1], v15[1]
-# CHECK: mov.s v2[1], v15[1]
-# CHECK: mov.h v2[1], v15[1]
-# CHECK: mov.b v2[1], v15[1]
-
-# CHECK: mov.d v2[1], v15[0]
-# CHECK: mov.s v2[3], v15[2]
-# CHECK: mov.h v2[7], v15[3]
-# CHECK: mov.b v2[10], v15[5]
+# CHECK: ins.d v2[1], v15[1]
+# CHECK: ins.s v2[1], v15[1]
+# CHECK: ins.h v2[1], v15[1]
+# CHECK: ins.b v2[1], v15[1]
+
+# CHECK: ins.d v2[1], v15[0]
+# CHECK: ins.s v2[3], v15[2]
+# CHECK: ins.h v2[7], v15[3]
+# CHECK: ins.b v2[10], v15[5]
 
 0x00 0x1c 0x20 0x0e
 0x00 0x1c 0x20 0x4e
 
 # CHECK: and.8b  v0, v0, v0
 # CHECK: and.16b v0, v0, v0
 
 0x00 0x1c 0x60 0x0e

utils/TableGen/AsmWriterEmitter.cpp

for (auto &Alias : Aliases.second) {
             CGA.TheDef->getValueAsListOfDefs("Predicates");
         std::copy_if(RF.begin(), RF.end(), std::back_inserter(ReqFeatures),
                      [](Record *R) {
                        return R->getValueAsBit("AssemblerMatcherPredicate");
                      });
       }
 
       unsigned NumMIOps = 0;
-      for (auto &Operand : CGA.ResultInst->Operands.OperandList)
-        NumMIOps += Operand.MINumOperands;
+      for (auto &Operand : CGA.ResultOperands)
+        NumMIOps += Operand.getMINumOperands();
 
       std::string Cond;
       Cond = std::string("MI->getNumOperands() == ") + utostr(NumMIOps);
       IAP.addCond(Cond);
 
       bool CantHandle = false;
 
       unsigned MIOpNum = 0;
       for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
-        // Skip over tied operands as they're not part of an alias declaration.
-        if (CGA.ResultInst->Operands[MIOpNum].MINumOperands == 1 &&
-            CGA.ResultInst->Operands[MIOpNum].getTiedRegister() != -1)
-          ++MIOpNum;
-
         std::string Op = "MI->getOperand(" + utostr(MIOpNum) + ")";
 
         const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
 
         switch (RO.Kind) {
         case CodeGenInstAlias::ResultOperand::K_Record: {
           const Record *Rec = RO.getRecord();
           StringRef ROName = RO.getName();