[GlobalISel] Pointers are legal operands for G_SELECT on AArch64

[kristof.beyls]

Summary

This makes another 13 tests pass in the test-suite for me.

I'm not sure if we could tablegen the functionality I'm touching in this patch.
Even if we did, I think that manually fixing this is helpful, as it results in other issues being hidden less while we don't have tablegen for this.

[dsanders]

This looks good to me but I don't feel I have sufficiently complete knowledge of AArch64 to be approving codegen changes yet. It would be good to get an LGTM from one of the other reviewers before committing.

I'm not sure if we could tablegen the functionality I'm touching in this patch.

The current code looks like it will fit in to the tablegen definitions I've been sketching.

Even if we did, I think that manually fixing this is helpful, as it results in other issues being hidden less while we don't have tablegen for this.

I agree. It will be a while before the tablegen pass is complete enough to handle the things it needs to and there's no need to block this fix on that work.

[rengolin]

Looks pretty straight-forward.

llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp

case TargetOpcode::G_SELECT: {
     const unsigned CondReg = I.getOperand(1).getReg();
     const unsigned TReg = I.getOperand(2).getReg();
     const unsigned FReg = I.getOperand(3).getReg();
 
     unsigned CSelOpc = 0;
 
     if (Ty == LLT::scalar(32)) {
       CSelOpc = AArch64::CSELWr;
-    } else if (Ty == LLT::scalar(64)) {
+    } else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
       CSelOpc = AArch64::CSELXr;
     } else {
       return false;
     }
 
     MachineInstr &TstMI =
         *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
              .addDef(AArch64::WZR)

llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp

for (auto Ty : { s32, s64 }) {
     setAction({G_UITOFP, 0, Ty}, Legal);
   }
 
   // Control-flow
   for (auto Ty : {s1, s8, s16, s32})
     setAction({G_BRCOND, Ty}, Legal);
 
   // Select
-  for (auto Ty : {s1, s8, s16, s32, s64})
+  for (auto Ty : {s1, s8, s16, s32, s64, p0})
     setAction({G_SELECT, Ty}, Legal);
 
   setAction({G_SELECT, 1, s1}, Legal);
 
   // Pointer-handling
   setAction({G_FRAME_INDEX, p0}, Legal);
   setAction({G_GLOBAL_VALUE, p0}, Legal);
 

llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr32 }
 # CHECK-NEXT:  - { id: 1, class: gpr32 }
 # CHECK-NEXT:  - { id: 2, class: gpr32 }
 # CHECK-NEXT:  - { id: 3, class: gpr32 }
 # CHECK-NEXT:  - { id: 4, class: gpr64 }
 # CHECK-NEXT:  - { id: 5, class: gpr64 }
 # CHECK-NEXT:  - { id: 6, class: gpr64 }
+# CHECK-NEXT:  - { id: 7, class: gpr64 }
+# CHECK-NEXT:  - { id: 8, class: gpr64 }
+# CHECK-NEXT:  - { id: 9, class: gpr64 }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
+  - { id: 8, class: gpr }
+  - { id: 9, class: gpr }
 
 # CHECK:  body:
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
 # CHECK:      %3 = CSELWr %1, %2, 1, implicit %nzcv
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
 # CHECK:      %6 = CSELXr %4, %5, 1, implicit %nzcv
+# CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK:      %9 = CSELXr %7, %8, 1, implicit %nzcv
 body:             |
   bb.0:
     liveins: %w0, %w1, %w2
     %0(s1) = COPY %w0
 
     %1(s32) = COPY %w1
     %2(s32) = COPY %w2
     %3(s32) = G_SELECT %0, %1, %2
 
     %4(s64) = COPY %x0
     %5(s64) = COPY %x1
     %6(s64) = G_SELECT %0, %4, %5
+
+    %7(p0) = COPY %x0
+    %8(p0) = COPY %x1
+    %9(p0) = G_SELECT %0, %7, %8
 ...