[AArch64] Generate literals by the little end

[evandro]

Summary

ARM seems to prefer that long literals be formed from their little end (v. "Cortex A57 Software Optimisation Guide", section 4.14).

This also promotes fusion of literal generation using the instrs pairs MOV/MOVK and MOVK/MOVK on Cortex A57 and others.

[rengolin]

Hi Evandro,

Isn't this specific to A57 (as in D28698)? Do you have any data that this will perform equally or better on the other AArch64 cores, too?

Also, the commit message could be improved by mentioning why "ARM seems to prefer that long literals be formed from their little end.", ie. a reference to the A57 manual.

cheers,
--renato

[evandro]

Hi, @rengolin .

Isn't this specific to A57 (as in D28698)? Do you have any data that this will perform equally or better on the other AArch64 cores, too?

D28698 needs this change, but I think that it makes more sense to have both patches separated.

Unfortunately, I don't have access to other targets. On A57, which may fuse the resulting instr sequence, benefits from this change. On the only other target that I have access to, the M1, which doesn't fuse literals generation, this change was a wash.

Also, the commit message could be improved by mentioning why "ARM seems to prefer that long literals be formed from their little end.", ie. a reference to the A57 manual.

OK

[rengolin]

Ok, I'm adding Kristof to check the other cores' behaviour.

[kristof.beyls]

In D28697#648532, @rengolin wrote:

Ok, I'm adding Kristof to check the other cores' behaviour.

For the cores for which I know the answer, this change is either beneficial or neutral.
In other words, the code generation change in this patch is OK from my perspective.

[rengolin]

Thanks Kristof! I can't see any problem either. LGTM. Thanks!

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
   } else {
     FirstOpc = (isNeg ? AArch64::MOVNXi : AArch64::MOVZXi);
   }
   unsigned Shift = 0;     // LSL amount for high bits with MOVZ/MOVN
   unsigned LastShift = 0; // LSL amount for last MOVK
   if (Imm != 0) {
     unsigned LZ = countLeadingZeros(Imm);
     unsigned TZ = countTrailingZeros(Imm);
-    Shift = ((63 - LZ) / 16) * 16;
-    LastShift = (TZ / 16) * 16;
+    Shift = (TZ / 16) * 16;
+    LastShift = ((63 - LZ) / 16) * 16;
   }
   unsigned Imm16 = (Imm >> Shift) & Mask;
   bool DstIsDead = MI.getOperand(0).isDead();
   MachineInstrBuilder MIB1 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(FirstOpc))
           .addReg(DstReg, RegState::Define |
-                              getDeadRegState(DstIsDead && Shift == LastShift))
           .addImm(Imm16)
           .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));
 
   // If a MOVN was used for the high bits of a negative value, flip the rest
   // of the bits back for use with MOVK.
   if (isNeg)
     Imm = ~Imm;
 
   if (Shift == LastShift) {
     transferImpOps(MI, MIB1, MIB1);
     MI.eraseFromParent();
     return true;
   }
 
   MachineInstrBuilder MIB2;
   unsigned Opc = (BitSize == 32 ? AArch64::MOVKWi : AArch64::MOVKXi);
-  while (Shift != LastShift) {
-    Shift -= 16;
+  while (Shift < LastShift) {
+    Shift += 16;
     Imm16 = (Imm >> Shift) & Mask;
     if (Imm16 == (isNeg ? Mask : 0))
       continue; // This 16-bit portion is already set correctly.
     MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
                .addReg(DstReg,
                        RegState::Define |
-                           getDeadRegState(DstIsDead && Shift == LastShift))
                .addReg(DstReg)
                .addImm(Imm16)
                .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));
   }
 
   transferImpOps(MI, MIB1, MIB2);
   MI.eraseFromParent();
   return true;

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

if ((OpFlags & AArch64II::MO_GOT) != 0) {
     BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
         .addGlobalAddress(GV, 0, AArch64II::MO_GOT);
     BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
         .addReg(Reg, RegState::Kill)
         .addImm(0)
         .addMemOperand(*MI.memoperands_begin());
   } else if (TM.getCodeModel() == CodeModel::Large) {
     BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
-        .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
+        .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
         .addReg(Reg, RegState::Kill)
-        .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
+        .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16);
     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
         .addReg(Reg, RegState::Kill)
-        .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16);
+        .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
     BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
         .addReg(Reg, RegState::Kill)
-        .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
+        .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
     BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
         .addReg(Reg, RegState::Kill)
         .addImm(0)
         .addMemOperand(*MI.memoperands_begin());
   } else {
     BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
         .addGlobalAddress(GV, 0, OpFlags | AArch64II::MO_PAGE);
     unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | MO_NC;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def : Pat<(f64 fpimm:$in),
   (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
 
 
 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
 // sequences.
 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
                              tglobaladdr:$g1, tglobaladdr:$g0),
-          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
-                                  tglobaladdr:$g2, 32),
+          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0),
                                   tglobaladdr:$g1, 16),
-                  tglobaladdr:$g0, 0)>;
+                          tglobaladdr:$g2, 32),
+                  tglobaladdr:$g3, 48)>;
 
 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
                              tblockaddress:$g1, tblockaddress:$g0),
-          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
-                                  tblockaddress:$g2, 32),
+          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0),
                                   tblockaddress:$g1, 16),
-                  tblockaddress:$g0, 0)>;
+                          tblockaddress:$g2, 32),
+                  tblockaddress:$g3, 48)>;
 
 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
                              tconstpool:$g1, tconstpool:$g0),
-          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
-                                  tconstpool:$g2, 32),
+          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0),
                                   tconstpool:$g1, 16),
-                  tconstpool:$g0, 0)>;
+                          tconstpool:$g2, 32),
+                  tconstpool:$g3, 48)>;
 
 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
                              tjumptable:$g1, tjumptable:$g0),
-          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
-                                  tjumptable:$g2, 32),
+          (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0),
                                   tjumptable:$g1, 16),
-                  tjumptable:$g0, 0)>;
+                          tjumptable:$g2, 32),
+                  tjumptable:$g3, 48)>;
 
 
 //===----------------------------------------------------------------------===//
 // Arithmetic instructions.
 //===----------------------------------------------------------------------===//
 
 // Add/subtract with carry.
 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;

llvm/test/CodeGen/AArch64/arm64-addrmode.ll

; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
   %1 = add i64 %a, 81909218222800896   ;0x123000000000000
   %2 = inttoptr i64 %1 to i64*
   %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
 define void @t11(i64 %a) {
 ; CHECK-LABEL: t11:
-; CHECK: mov w[[NUM:[0-9]+]], #19070976
-; CHECK: movk w[[NUM:[0-9]+]], #17767
+; CHECK: mov w[[NUM:[0-9]+]], #17767
+; CHECK: movk w[[NUM:[0-9]+]], #291
 ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
   %1 = add i64 %a, 19088743   ;0x1234567
   %2 = inttoptr i64 %1 to i64*
   %3 = load volatile i64, i64* %2, align 8
   ret void
 }
 
 ; Test some boundaries that should not use movz/movn/orr

llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll

 
 ; Check if we can still catch bfm instruction when we drop some high bits
 ; and some low bits and a masking operation has to be kept
 define void @fct16(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct16:
 ; CHECK: ldr [[REG1:w[0-9]+]],
 ; Create the constant
-; CHECK: mov [[REGCST:w[0-9]+]], #1703936
-; CHECK: movk [[REGCST]], #33120
+; CHECK: mov [[REGCST:w[0-9]+]], #33120
+; CHECK: movk [[REGCST]], #26, lsl #16
 ; Do the masking
 ; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
 ; CHECK-NEXT: bfxil [[REG2]], w1, #16, #3
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: ubfx [[REG3:w[0-9]+]], [[REG2]], #2, #28
 ; CHECK-NEXT: str [[REG3]],
 ; CHECK-NEXT: ret
   %0 = load i32, i32* %y, align 8

 ; Check if we can still catch bfm instruction when we drop some high bits
 ; and some low bits and a masking operation has to be kept
 ; (i64 version)
 define void @fct17(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
 entry:
 ; CHECK-LABEL: fct17:
 ; CHECK: ldr [[REG1:x[0-9]+]],
 ; Create the constant
-; CHECK: mov w[[REGCST:[0-9]+]], #1703936
-; CHECK: movk w[[REGCST]], #33120
+; CHECK: mov w[[REGCST:[0-9]+]], #33120
+; CHECK: movk w[[REGCST]], #26, lsl #16
 ; Do the masking
 ; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
 ; CHECK-NEXT: bfxil [[REG2]], x1, #16, #3
 ; lsr is an alias of ubfm
 ; CHECK-NEXT: ubfx [[REG3:x[0-9]+]], [[REG2]], #2, #60
 ; CHECK-NEXT: str [[REG3]],
 ; CHECK-NEXT: ret
   %0 = load i64, i64* %y, align 8

llvm/test/CodeGen/AArch64/arm64-blockaddress.ll

 ; CHECK: adrp [[REG:x[0-9]+]], Ltmp1@PAGE
 ; CHECK: add {{x[0-9]+}}, [[REG]], Ltmp1@PAGEOFF
 
 ; CHECK-LINUX-LABEL: t:
 ; CHECK-LINUX: adrp [[REG:x[0-9]+]], .Ltmp1
 ; CHECK-LINUX: add {{x[0-9]+}}, [[REG]], :lo12:.Ltmp1
 
 ; CHECK-LARGE-LABEL: t:
-; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g3:[[DEST_LBL:.Ltmp[0-9]+]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
+; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g0_nc:[[DEST_LBL:.Ltmp[0-9]+]]
 ; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g0_nc:[[DEST_LBL]]
+; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
+; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g3:[[DEST_LBL]]
 
   %recover = alloca i64, align 8
   store volatile i64 ptrtoint (i8* blockaddress(@t, %mylabel) to i64), i64* %recover, align 8
   br label %mylabel
 
 mylabel:
   %tmp = load volatile i64, i64* %recover, align 8
   ret i64 %tmp
 }

llvm/test/CodeGen/AArch64/arm64-code-model-large-abs.ll

 ; RUN: llc -mtriple=arm64-none-linux-gnu -code-model=large < %s | FileCheck %s
 
 @var8 = global i8 0
 @var16 = global i16 0
 @var32 = global i32 0
 @var64 = global i64 0
 
 define i8* @global_addr() {
 ; CHECK-LABEL: global_addr:
   ret i8* @var8
   ; The movz/movk calculation should end up returned directly in x0.
-; CHECK: movz x0, #:abs_g3:var8
-; CHECK: movk x0, #:abs_g2_nc:var8
+; CHECK: movz x0, #:abs_g0_nc:var8
 ; CHECK: movk x0, #:abs_g1_nc:var8
-; CHECK: movk x0, #:abs_g0_nc:var8
+; CHECK: movk x0, #:abs_g2_nc:var8
+; CHECK: movk x0, #:abs_g3:var8
 ; CHECK-NEXT: ret
 }
 
 define i8 @global_i8() {
 ; CHECK-LABEL: global_i8:
   %val = load i8, i8* @var8
   ret i8 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var8
 ; CHECK: ldrb w0, [x[[ADDR_REG]]]
 }
 
 define i16 @global_i16() {
 ; CHECK-LABEL: global_i16:
   %val = load i16, i16* @var16
   ret i16 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var16
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var16
 ; CHECK: ldrh w0, [x[[ADDR_REG]]]
 }
 
 define i32 @global_i32() {
 ; CHECK-LABEL: global_i32:
   %val = load i32, i32* @var32
   ret i32 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var32
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var32
 ; CHECK: ldr w0, [x[[ADDR_REG]]]
 }
 
 define i64 @global_i64() {
 ; CHECK-LABEL: global_i64:
   %val = load i64, i64* @var64
   ret i64 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var64
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var64
 ; CHECK: ldr x0, [x[[ADDR_REG]]]
 }
 
 define <2 x i64> @constpool() {
 ; CHECK-LABEL: constpool:
   ret <2 x i64> <i64 123456789, i64 987654321100>
 
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:[[CPADDR]]
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:[[CPADDR]]
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:[[CPADDR]]
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:[[CPADDR]]
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:[[CPADDR]]
 ; CHECK: ldr q0, [x[[ADDR_REG]]]
 }

llvm/test/CodeGen/AArch64/arm64-const-addr.ll

 ; RUN: llc -mtriple=arm64-darwin-unknown < %s | FileCheck %s
 
 %T = type { i32, i32, i32, i32 }
 
 ; Test if the constant base address gets only materialized once.
 define i32 @test1() nounwind {
 ; CHECK-LABEL:  test1
-; CHECK:        mov  w8, #68091904
-; CHECK-NEXT:   movk  w8, #49152
+; CHECK:        mov  w8, #49152
+; CHECK-NEXT:   movk  w8, #1039, lsl #16
 ; CHECK-NEXT:   ldp w9, w10, [x8, #4]
 ; CHECK:        ldr w8, [x8, #12]
   %at = inttoptr i64 68141056 to %T*
   %o1 = getelementptr %T, %T* %at, i32 0, i32 1
   %t1 = load i32, i32* %o1
   %o2 = getelementptr %T, %T* %at, i32 0, i32 2
   %t2 = load i32, i32* %o2
   %a1 = add i32 %t1, %t2
   %o3 = getelementptr %T, %T* %at, i32 0, i32 3
   %t3 = load i32, i32* %o3
   %a2 = add i32 %a1, %t3
   ret i32 %a2
 }
 

llvm/test/CodeGen/AArch64/arm64-extern-weak.ll

 ; otherwise a litpool entry.
   ret i32()* @var
 
 ; CHECK: adrp x[[VAR:[0-9]+]], :got:var
 ; CHECK: ldr x0, [x[[VAR]], :got_lo12:var]
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
-; CHECK-LARGE: movz x0, #:abs_g3:var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:var
+; CHECK-LARGE: movz x0, #:abs_g0_nc:var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:var
+; CHECK-LARGE: movk x0, #:abs_g2_nc:var
+; CHECK-LARGE: movk x0, #:abs_g3:var
 }
 
 
 @arr_var = extern_weak global [10 x i32]
 
 define i32* @bar() {
   %addr = getelementptr [10 x i32], [10 x i32]* @arr_var, i32 0, i32 5
 ; CHECK: adrp x[[ARR_VAR_HI:[0-9]+]], :got:arr_var
 ; CHECK: ldr [[ARR_VAR:x[0-9]+]], [x[[ARR_VAR_HI]], :got_lo12:arr_var]
 ; CHECK: add x0, [[ARR_VAR]], #20
   ret i32* %addr
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
-; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g3:arr_var
-; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g2_nc:arr_var
+; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g0_nc:arr_var
 ; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g1_nc:arr_var
-; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g0_nc:arr_var
+; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g2_nc:arr_var
+; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g3:arr_var
 }
 
 @defined_weak_var = internal unnamed_addr global i32 0
 
 define i32* @wibble() {
   ret i32* @defined_weak_var
 ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
 ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
 
-; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
+; CHECK-LARGE: movz x0, #:abs_g0_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
+; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
+; CHECK-LARGE: movk x0, #:abs_g3:defined_weak_var
 }

llvm/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll

 
 ; Load an address with a ridiculously large offset.
 ; rdar://12505553
 @pd2 = common global i8* null, align 8
 
 define signext i8 @foo3() nounwind ssp {
 entry:
 ; CHECK-LABEL: @foo3
-; CHECK: mov x[[REG:[0-9]+]], #12343736008704
+; CHECK: mov x[[REG:[0-9]+]], #12274
 ; CHECK: movk x[[REG]], #29646, lsl #16
-; CHECK: movk x[[REG]], #12274
+; CHECK: movk x[[REG]], #2874, lsl #32
   %0 = load i8*, i8** @pd2, align 8
   %arrayidx = getelementptr inbounds i8, i8* %0, i64 12345678901234
   %1 = load i8, i8* %arrayidx, align 1
   ret i8 %1
 }

llvm/test/CodeGen/AArch64/arm64-movi.ll

 define i32 @movz() nounwind {
 ; CHECK-LABEL: movz:
 ; CHECK: mov w0, #5
   ret i32 5
 }
 
 define i64 @movz_3movk() nounwind {
 ; CHECK-LABEL: movz_3movk:
-; CHECK:      mov x0, #1407374883553280
-; CHECK-NEXT: movk x0, #4660, lsl #32
+; CHECK:      mov x0, #22136
 ; CHECK-NEXT: movk x0, #43981, lsl #16
-; CHECK-NEXT: movk x0, #22136
+; CHECK-NEXT: movk x0, #4660, lsl #32
+; CHECK-NEXT: movk x0, #5, lsl #48
   ret i64 1427392313513592
 }
 
 define i64 @movz_movk_skip1() nounwind {
 ; CHECK-LABEL: movz_movk_skip1:
-; CHECK:      mov x0, #21474836480
-; CHECK-NEXT: movk x0, #17185, lsl #16
+; CHECK:      mov x0, #1126236160
+; CHECK-NEXT: movk x0, #5, lsl #32
   ret i64 22601072640
 }
 
 define i64 @movz_skip1_movk() nounwind {
 ; CHECK-LABEL: movz_skip1_movk:
-; CHECK:      mov x0, #147695335374848
-; CHECK-NEXT: movk x0, #4660
+; CHECK:      mov x0, #4660
+; CHECK-NEXT: movk x0, #34388, lsl #32
   ret i64 147695335379508
 }
 
 ;==--------------------------------------------------------------------------==
 ; Tests for MOVN with MOVK.
 ;==--------------------------------------------------------------------------==
 
 define i64 @movn() nounwind {
 ; CHECK-LABEL: movn:
 ; CHECK: mov x0, #-42
   ret i64 -42
 }
 
 define i64 @movn_skip1_movk() nounwind {
 ; CHECK-LABEL: movn_skip1_movk:
-; CHECK:      mov x0, #-176093659137
-; CHECK-NEXT: movk x0, #4660
+; CHECK:      mov x0, #-60876
+; CHECK-NEXT: movk x0, #65494, lsl #32
   ret i64 -176093720012
 }
 
 ;==--------------------------------------------------------------------------==
 ; Tests for ORR with MOVK.
 ;==--------------------------------------------------------------------------==
 ; rdar://14987673
 

 ; CHECK: movk x0, #57005
 ; CHECK: movk x0, #57005, lsl #48
   ret i64 -2401245434149282131
 }
 
 ; rdar://13944082
 define i64 @g() nounwind {
 ; CHECK-LABEL: g:
-; CHECK: mov x0, #-281474976710656
-; CHECK: movk x0, #2
+; CHECK: mov x0, #2
+; CHECK: movk x0, #65535, lsl #48
 entry:
   ret i64 -281474976710654
 }

llvm/test/CodeGen/AArch64/bitfield-insert.ll

define i32 @test5(i32 %a) {
   %1 = and i32 %a, 4294967280 ; 0xfffffff0
   %2 = or i32 %1, 6           ; 0x00000006
   ret i32 %2
 }
 
 ; BFXIL will use the same constant as the ORR, so we don't care how the constant
 ; is materialized (it's an equal cost either way).
 ; CHECK-LABEL: @test6
-; CHECK: mov [[REG:w[0-9]+]], #720896
-; CHECK: movk [[REG]], #23250
+; CHECK: mov [[REG:w[0-9]+]], #23250
+; CHECK: movk [[REG]], #11, lsl #16
 ; CHECK: bfxil w0, [[REG]], #0, #20
 define i32 @test6(i32 %a) {
   %1 = and i32 %a, 4293918720 ; 0xfff00000
   %2 = or i32 %1, 744146      ; 0x000b5ad2
   ret i32 %2
 }
 
 ; BFIs that require the same number of instruction to materialize the constant
 ; as the original ORR are okay.
 ; CHECK-LABEL: @test7
-; CHECK: mov [[REG:w[0-9]+]], #327680
-; CHECK: movk [[REG]], #44393
+; CHECK: mov [[REG:w[0-9]+]], #44393
+; CHECK: movk [[REG]], #5, lsl #16
 ; CHECK: bfi w0, [[REG]], #1, #19
 define i32 @test7(i32 %a) {
   %1 = and i32 %a, 4293918721 ; 0xfff00001
   %2 = or i32 %1, 744146      ; 0x000b5ad2
   ret i32 %2
 }
 
 ; BFIs that require more instructions to materialize the constant as compared
 ; to the original ORR are not okay.  In this case we would be replacing the
 ; 'and' with a 'movk', which would decrease ILP while using the same number of
 ; instructions.
 ; CHECK-LABEL: @test8
-; CHECK: mov [[REG2:x[0-9]+]], #157599529959424
+; CHECK: mov [[REG2:x[0-9]+]], #2035482624
 ; CHECK: and [[REG1:x[0-9]+]], x0, #0xff000000000000ff
-; CHECK: movk [[REG2]], #31059, lsl #16
+; CHECK: movk [[REG2]], #36694, lsl #32
 ; CHECK: orr x0, [[REG1]], [[REG2]]
 define i64 @test8(i64 %a) {
   %1 = and i64 %a, -72057594037927681 ; 0xff000000000000ff
   %2 = or i64 %1, 157601565442048     ; 0x00008f5679530000
   ret i64 %2
 }
 
 ; This test exposed an issue with an overly aggressive assert.  The bit of code

llvm/test/CodeGen/AArch64/blockaddress.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -code-model=large -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LARGE %s
 
 @addr = global i8* null
 
 define void @test_blockaddress() {
 ; CHECK-LABEL: test_blockaddress:
   store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
   %val = load volatile i8*, i8** @addr
   indirectbr i8* %val, [label %block]
 ; CHECK: adrp [[DEST_HI:x[0-9]+]], [[DEST_LBL:.Ltmp[0-9]+]]
 ; CHECK: add [[DEST:x[0-9]+]], [[DEST_HI]], {{#?}}:lo12:[[DEST_LBL]]
 ; CHECK: str [[DEST]],
 ; CHECK: ldr [[NEWDEST:x[0-9]+]]
 ; CHECK: br [[NEWDEST]]
 
-; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g3:[[DEST_LBL:.Ltmp[0-9]+]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
+; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g0_nc:[[DEST_LBL:.Ltmp[0-9]+]]
 ; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g0_nc:[[DEST_LBL]]
+; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
+; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g3:[[DEST_LBL]]
 ; CHECK-LARGE: str [[ADDR_REG]],
 ; CHECK-LARGE: ldr [[NEWDEST:x[0-9]+]]
 ; CHECK-LARGE: br [[NEWDEST]]
 
 block:
   ret void
 }

llvm/test/CodeGen/AArch64/code-model-large-abs.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -code-model=large -o - %s | FileCheck %s
 
 @var8 = global i8 0
 @var16 = global i16 0
 @var32 = global i32 0
 @var64 = global i64 0
 
 define i8* @global_addr() {
 ; CHECK-LABEL: global_addr:
   ret i8* @var8
   ; The movz/movk calculation should end up returned directly in x0.
-; CHECK: movz x0, #:abs_g3:var8
-; CHECK: movk x0, #:abs_g2_nc:var8
+; CHECK: movz x0, #:abs_g0_nc:var8
 ; CHECK: movk x0, #:abs_g1_nc:var8
-; CHECK: movk x0, #:abs_g0_nc:var8
+; CHECK: movk x0, #:abs_g2_nc:var8
+; CHECK: movk x0, #:abs_g3:var8
 ; CHECK-NEXT: ret
 }
 
 define i8 @global_i8() {
 ; CHECK-LABEL: global_i8:
   %val = load i8, i8* @var8
   ret i8 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var8
 ; CHECK: ldrb w0, [x[[ADDR_REG]]]
 }
 
 define i16 @global_i16() {
 ; CHECK-LABEL: global_i16:
   %val = load i16, i16* @var16
   ret i16 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var16
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var16
 ; CHECK: ldrh w0, [x[[ADDR_REG]]]
 }
 
 define i32 @global_i32() {
 ; CHECK-LABEL: global_i32:
   %val = load i32, i32* @var32
   ret i32 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var32
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var32
 ; CHECK: ldr w0, [x[[ADDR_REG]]]
 }
 
 define i64 @global_i64() {
 ; CHECK-LABEL: global_i64:
   %val = load i64, i64* @var64
   ret i64 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
+; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var64
 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64
+; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
+; CHECK: movk x[[ADDR_REG]], #:abs_g3:var64
 ; CHECK: ldr x0, [x[[ADDR_REG]]]
 }

llvm/test/CodeGen/AArch64/extern-weak.ll

; otherwise a litpool entry.
   ret i32()* @var
 
 
 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:var
 ; CHECK: ldr x0, [x[[ADDRHI]], :got_lo12:var]
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
-; CHECK-LARGE: movz x0, #:abs_g3:var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:var
+; CHECK-LARGE: movz x0, #:abs_g0_nc:var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:var
+; CHECK-LARGE: movk x0, #:abs_g2_nc:var
+; CHECK-LARGE: movk x0, #:abs_g3:var
 }
 
 
 @arr_var = extern_weak global [10 x i32]
 
 define i32* @bar() {
   %addr = getelementptr [10 x i32], [10 x i32]* @arr_var, i32 0, i32 5
 
 
 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:arr_var
 ; CHECK: ldr [[BASE:x[0-9]+]], [x[[ADDRHI]], :got_lo12:arr_var]
 ; CHECK: add x0, [[BASE]], #20
 
   ret i32* %addr
 
   ; In the large model, the usual relocations are absolute and can
   ; materialise 0.
-; CHECK-LARGE: movz [[ADDR:x[0-9]+]], #:abs_g3:arr_var
-; CHECK-LARGE: movk [[ADDR]], #:abs_g2_nc:arr_var
+; CHECK-LARGE: movz [[ADDR:x[0-9]+]], #:abs_g0_nc:arr_var
 ; CHECK-LARGE: movk [[ADDR]], #:abs_g1_nc:arr_var
-; CHECK-LARGE: movk [[ADDR]], #:abs_g0_nc:arr_var
+; CHECK-LARGE: movk [[ADDR]], #:abs_g2_nc:arr_var
+; CHECK-LARGE: movk [[ADDR]], #:abs_g3:arr_var
 }
 
 @defined_weak_var = internal unnamed_addr global i32 0
 
 define i32* @wibble() {
   ret i32* @defined_weak_var
 
 ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
 ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
 
-; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
+; CHECK-LARGE: movz x0, #:abs_g0_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
+; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
+; CHECK-LARGE: movk x0, #:abs_g3:defined_weak_var
 }

llvm/test/CodeGen/AArch64/fpimm.ll

; CHECK-DAG: fmov {{d[0-9]+}}, #8.5
   store volatile double %newval2, double* @varf64
 ; CHECK-DAG: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI1_0
 
 ; CHECK: ret
   ret void
 }
 
 ; LARGE-LABEL: check_float2
-; LARGE:       mov [[REG:w[0-9]+]], #1078525952
-; LARGE-NEXT:  movk [[REG]], #4059
+; LARGE:       mov [[REG:w[0-9]+]], #4059
+; LARGE-NEXT:  movk [[REG]], #16457, lsl #16
 ; LARGE-NEXT:  fmov s0, [[REG]]
 define float @check_float2() {
   ret float 3.14159274101257324218750
 }
 
 ; LARGE-LABEL: check_double2
-; LARGE:       mov [[REG:x[0-9]+]], #4614219293217783808
-; LARGE-NEXT:  movk [[REG]], #8699, lsl #32
+; LARGE:       mov [[REG:x[0-9]+]], #11544
 ; LARGE-NEXT:  movk [[REG]], #21572, lsl #16
-; LARGE-NEXT:  movk [[REG]], #11544
+; LARGE-NEXT:  movk [[REG]], #8699, lsl #32
+; LARGE-NEXT:  movk [[REG]], #16393, lsl #48
 ; LARGE-NEXT:  fmov d0, [[REG]]
 define double @check_double2() {
   ret double 3.1415926535897931159979634685441851615905761718750
 }

llvm/test/CodeGen/AArch64/jump-table.ll

switch i32 %in, label %def [
     i32 2, label %lbl3
     i32 4, label %lbl4
   ]
 ; CHECK: adrp [[JTPAGE:x[0-9]+]], .LJTI0_0
 ; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0
 ; CHECK: ldr [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #3]
 ; CHECK: br [[DEST]]
 
-; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g3:.LJTI0_0
-; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0
+; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g0_nc:.LJTI0_0
 ; CHECK-LARGE: movk x[[JTADDR]], #:abs_g1_nc:.LJTI0_0
-; CHECK-LARGE: movk x[[JTADDR]], #:abs_g0_nc:.LJTI0_0
+; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0
+; CHECK-LARGE: movk x[[JTADDR]], #:abs_g3:.LJTI0_0
 ; CHECK-LARGE: ldr [[DEST:x[0-9]+]], [x[[JTADDR]], {{x[0-9]+}}, lsl #3]
 ; CHECK-LARGE: br [[DEST]]
 
 ; CHECK-PIC: adrp [[JTPAGE:x[0-9]+]], .LJTI0_0
 ; CHECK-PIC: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0
 ; CHECK-PIC: ldrsw [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #2]
 ; CHECK-PIC: add [[TABLE:x[0-9]+]], [[DEST]], x[[JT]]
 ; CHECK-PIC: br [[TABLE]]

llvm/test/CodeGen/AArch64/large-consts.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu -o - %s -code-model=large -show-mc-encoding | FileCheck %s
 
 ; Make sure the shift amount is encoded into the instructions by LLVM because
 ; it's not the linker's job to put it there.
 
 define double @foo() {
 
-; CHECK: movz [[CPADDR:x[0-9]+]], #:abs_g3:.LCPI0_0   // encoding: [0bAAA01000,A,0b111AAAAA,0xd2]
-; CHECK: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b110AAAAA,0xf2]
+; CHECK: movz [[CPADDR:x[0-9]+]], #:abs_g0_nc:.LCPI0_0   // encoding: [0bAAA01000,A,0b100AAAAA,0xd2]
 ; CHECK: movk [[CPADDR]], #:abs_g1_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b101AAAAA,0xf2]
-; CHECK: movk [[CPADDR]], #:abs_g0_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b100AAAAA,0xf2]
+; CHECK: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [0bAAA01000,A,0b110AAAAA,0xf2]
+; CHECK: movk [[CPADDR]], #:abs_g3:.LCPI0_0 // encoding: [0bAAA01000,A,0b111AAAAA,0xf2]
 
   ret double 3.14159
 }

llvm/test/CodeGen/AArch64/literal_pools_float.ll

 ; CHECK-LABEL: floating_lits:
 
   %floatval = load float, float* @varfloat
   %newfloat = fadd float %floatval, 128.0
 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
 ; CHECK-NOFP-NOT: ldr {{s[0-9]+}},
 
-; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
-; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
+; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
-; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
+; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
+; CHECK-LARGE: movk x[[LITADDR]], #:abs_g3:[[CURLIT]]
 ; CHECK-LARGE: ldr {{s[0-9]+}}, [x[[LITADDR]]]
 ; CHECK-LARGE: fadd
 ; CHECK-NOFP-LARGE-NOT: ldr {{s[0-9]+}},
 ; CHECK-NOFP-LARGE-NOT: fadd
 
   store float %newfloat, float* @varfloat
 
   %doubleval = load double, double* @vardouble
   %newdouble = fadd double %doubleval, 129.0
 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK: ldr [[LIT129:d[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
 ; CHECK-NOFP-NOT: ldr {{d[0-9]+}},
 ; CHECK-NOFP-NOT: fadd
 
-; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
-; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
+; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]]
 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
-; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
+; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
+; CHECK-LARGE: movk x[[LITADDR]], #:abs_g3:[[CURLIT]]
 ; CHECK-LARGE: ldr {{d[0-9]+}}, [x[[LITADDR]]]
 ; CHECK-NOFP-LARGE-NOT: ldr {{d[0-9]+}},
 
   store double %newdouble, double* @vardouble
 
   ret void
 }

llvm/test/CodeGen/AArch64/movw-shift-encoding.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu < %s -show-mc-encoding -code-model=large | FileCheck %s
 
 @var = global i32 0
 
 ; CodeGen should ensure that the correct shift bits are set, because the linker
 ; isn't going to!
 
 define i32* @get_var() {
   ret i32* @var
 
-; CHECK: movz    x0, #:abs_g3:var        // encoding: [0bAAA00000,A,0b111AAAAA,0xd2]
-; CHECK: movk    x0, #:abs_g2_nc:var     // encoding: [0bAAA00000,A,0b110AAAAA,0xf2]
-; CHECK: movk    x0, #:abs_g1_nc:var     // encoding: [0bAAA00000,A,0b101AAAAA,0xf2]
-; CHECK: movk    x0, #:abs_g0_nc:var     // encoding: [0bAAA00000,A,0b100AAAAA,0xf2]
+; CHECK: movz    x0, #:abs_g0_nc:var // encoding: [0bAAA00000,A,0b100AAAAA,0xd2]
+; CHECK: movk    x0, #:abs_g1_nc:var // encoding: [0bAAA00000,A,0b101AAAAA,0xf2]
+; CHECK: movk    x0, #:abs_g2_nc:var // encoding: [0bAAA00000,A,0b110AAAAA,0xf2]
+; CHECK: movk    x0, #:abs_g3:var    // encoding: [0bAAA00000,A,0b111AAAAA,0xf2]
 }

llvm/test/CodeGen/AArch64/stack_guard_remat.ll

 ; DARWIN: ldr {{x[0-9]+}}, {{\[}}[[R1]]{{\]}}
 
 ; PIC-LINUX: foo2
 ; PIC-LINUX: adrp [[R0:x[0-9]+]], :got:__stack_chk_guard
 ; PIC-LINUX: ldr [[R1:x[0-9]+]], {{\[}}[[R0]], :got_lo12:__stack_chk_guard{{\]}}
 ; PIC-LINUX: ldr {{x[0-9]+}}, {{\[}}[[R1]]{{\]}}
 
 ; STATIC-LARGE: foo2
-; STATIC-LARGE: movz [[R0:x[0-9]+]], #:abs_g3:__stack_chk_guard
-; STATIC-LARGE: movk [[R0]], #:abs_g2_nc:__stack_chk_guard
+; STATIC-LARGE: movz [[R0:x[0-9]+]], #:abs_g0_nc:__stack_chk_guard
 ; STATIC-LARGE: movk [[R0]], #:abs_g1_nc:__stack_chk_guard
-; STATIC-LARGE: movk [[R0]], #:abs_g0_nc:__stack_chk_guard
+; STATIC-LARGE: movk [[R0]], #:abs_g2_nc:__stack_chk_guard
+; STATIC-LARGE: movk [[R0]], #:abs_g3:__stack_chk_guard
 ; STATIC-LARGE: ldr {{x[0-9]+}}, {{\[}}[[R0]]{{\]}}
 
 ; STATIC-SMALL: foo2
 ; STATIC-SMALL: adrp [[R0:x[0-9]+]], __stack_chk_guard
 ; STATIC-SMALL: ldr {{x[0-9]+}}, {{\[}}[[R0]], :lo12:__stack_chk_guard{{\]}}
 
 define i32 @test_stack_guard_remat() #0 {
 entry: