[GlobalIsel] Add support for address-taken basic blocks

[kristof.beyls]

Summary

In this patch, support for handling address-taken basic blocks in GlobalISel is added.
Together with https://reviews.llvm.org/D28079, this makes SingleSource/Regression/C/2004-03-15-IndirectGoto in the test-suite run correctly with -mllvm -global-isel=true -mllvm -global-isel-abort=1.

To make this work, pointers from the MachineBasicBlock to the LLVM-IR-level basic blocks need to be initialized, as the AsmPrinter uses this link to be able to print out labels for the basic blocks that are address-taken.
Most of the patch therefore is adapting existing tests to include the basic block name that is now printed out in the MIR format, now that the name becomes available as the link to the LLVM-IR basic block is initialized.
The relevant test change for the functionality added in this patch are the added "(address-taken)" strings in test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll.

[qcolombet]

LGTM

lib/CodeGen/GlobalISel/IRTranslator.cpp

if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
     llvm_unreachable("unhandled memory instruction");
 
   return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
 }
 
 MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
   MachineBasicBlock *&MBB = BBToMBB[&BB];
   if (!MBB) {
-    MBB = MF->CreateMachineBasicBlock();
+    MBB = MF->CreateMachineBasicBlock(&BB);
     MF->push_back(MBB);
+
+    if (BB.hasAddressTaken())
+      MBB->setHasAddressTaken();
   }
   return *MBB;
 }
 
 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
                                      MachineIRBuilder &MIRBuilder) {
   // FIXME: handle signed/unsigned wrapping flags.
 

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

define void @allocai64() {
   ret void
 }
 
 ; Tests for br.
 ; CHECK-LABEL: name: uncondbr
 ; CHECK: body:
 ;
 ; ABI/constant lowering and IR-level entry basic block.
-; CHECK: {{bb.[0-9]+}}:
+; CHECK: {{bb.[0-9]+}} (%ir-block.{{[0-9]+}}):
 ;
 ; Make sure we have one successor and only one.
-; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)
+; CHECK-NEXT: successors: %[[END:bb.[0-9]+.end]](0x80000000)
 ;
 ; Check that we emit the correct branch.
 ; CHECK: G_BR %[[END]]
 ;
 ; Check that end contains the return instruction.
 ; CHECK: [[END]]:
 ; CHECK-NEXT: RET_ReallyLR
 define void @uncondbr() {
   br label %end
 end:
   ret void
 }
 
 ; Tests for conditional br.
 ; CHECK-LABEL: name: condbr
 ; CHECK: body:
 ;
 ; ABI/constant lowering and IR-level entry basic block.
-; CHECK: {{bb.[0-9]+}}:
+; CHECK: {{bb.[0-9]+}} (%ir-block.{{[0-9]+}}):
 ; Make sure we have two successors
-; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),
-; CHECK:                  %[[FALSE:bb.[0-9]+]](0x40000000)
+; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+.true]](0x40000000),
+; CHECK:                  %[[FALSE:bb.[0-9]+.false]](0x40000000)
 ;
 ; CHECK: [[ADDR:%.*]](p0) = COPY %x0
 ;
 ; Check that we emit the correct branch.
 ; CHECK: [[TST:%.*]](s1) = G_LOAD [[ADDR]](p0)
 ; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]
 ; CHECK: G_BR %[[FALSE]]
 ;
false:
   ret void
 }
 
 ; Tests for indirect br.
 ; CHECK-LABEL: name: indirectbr
 ; CHECK: body:
 ;
 ; ABI/constant lowering and IR-level entry basic block.
-; CHECK: {{bb.[0-9]+}}:
+; CHECK: {{bb.[0-9]+.entry}}:
 ; Make sure we have one successor
-; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+]](0x80000000)
+; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+.L1]](0x80000000)
 ; CHECK: G_BR %[[BB_L1]]
 ;
 ; Check basic block L1 has 2 successors: BBL1 and BBL2
-; CHECK: [[BB_L1]]:
+; CHECK: [[BB_L1]] (address-taken):
 ; CHECK-NEXT: successors: %[[BB_L1]](0x40000000),
-; CHECK:                  %[[BB_L2:bb.[0-9]+]](0x40000000)
+; CHECK:                  %[[BB_L2:bb.[0-9]+.L2]](0x40000000)
 ; CHECK: G_BRINDIRECT %{{[0-9]+}}(p0)
 ;
 ; Check basic block L2 is the return basic block
-; CHECK: [[BB_L2]]:
+; CHECK: [[BB_L2]] (address-taken):
 ; CHECK-NEXT: RET_ReallyLR
 
 @indirectbr.L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@indirectbr, %L1), i8* blockaddress(@indirectbr, %L2), i8* null], align 8
 
 define void @indirectbr() {
 entry:
   br label %L1
 L1:                                               ; preds = %entry, %L1

 ; CHECK: RET_ReallyLR implicit %x0
 define i64* @trivial_bitcast(i8* %a) {
   %val = bitcast i8* %a to i64*
   ret i64* %val
 }
 
 ; CHECK-LABEL: name: trivial_bitcast_with_copy
 ; CHECK:     [[A:%[0-9]+]](p0) = COPY %x0
-; CHECK:     G_BR %[[CAST:bb\.[0-9]+]]
+; CHECK:     G_BR %[[CAST:bb\.[0-9]+.cast]]
 
 ; CHECK: [[CAST]]:
 ; CHECK:     {{%[0-9]+}}(p0) = COPY [[A]]
-; CHECK:     G_BR %[[END:bb\.[0-9]+]]
+; CHECK:     G_BR %[[END:bb\.[0-9]+.end]]
 
 ; CHECK: [[END]]:
 define i64* @trivial_bitcast_with_copy(i8* %a) {
   br label %cast
 
 end:
   ret i64* %val
 
define void @intrinsics(i32 %cur, i32 %bits) {
   %ptr = call i8* @llvm.returnaddress(i32 0)
   %ptr.vec = alloca <8 x i8>
   %vec = load <8 x i8>, <8 x i8>* %ptr.vec
   call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec, <8 x i8> %vec, i8* %ptr)
   ret void
 }
 
 ; CHECK-LABEL: name: test_phi
-; CHECK:     G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+]]
-; CHECK:     G_BR %[[FALSE:bb\.[0-9]+]]
+; CHECK:     G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+.true]]
+; CHECK:     G_BR %[[FALSE:bb\.[0-9]+.false]]
 
 ; CHECK: [[TRUE]]:
 ; CHECK:     [[RES1:%[0-9]+]](s32) = G_LOAD
 
 ; CHECK: [[FALSE]]:
 ; CHECK:     [[RES2:%[0-9]+]](s32) = G_LOAD
 
 ; CHECK:     [[RES:%[0-9]+]](s32) = PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]

 }
 
 ; When there was no formal argument handling (so the first BB was empty) we used
 ; to insert the constants at the end of the block, even if they were encountered
 ; after the block's terminators had been emitted. Also make sure the order is
 ; correct.
 define i8* @test_const_placement() {
 ; CHECK-LABEL: name: test_const_placement
-; CHECK: bb.{{[0-9]+}}:
+; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
 ; CHECK:   [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42
 ; CHECK:   [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
 ; CHECK:   G_BR
   br label %next
 
 next:
   ret i8* inttoptr(i32 42 to i8*)
 }

test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll

 ; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
 
 @_ZTIi = external global i8*
 
 declare i32 @foo(i32)
 declare i32 @__gxx_personality_v0(...)
 declare i32 @llvm.eh.typeid.for(i8*)
 
 ; CHECK: name: bar
 ; CHECK: body:
-; CHECK-NEXT:   bb.1:
-; CHECK:     successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
+; CHECK-NEXT:   bb.1 (%ir-block.0):
+; CHECK:     successors: %[[GOOD:bb.[0-9]+.continue]]{{.*}}%[[BAD:bb.[0-9]+.broken]]
 ; CHECK:     EH_LABEL
 ; CHECK:     %w0 = COPY
 ; CHECK:     BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
 ; CHECK:     {{%[0-9]+}}(s32) = COPY %w0
 ; CHECK:     EH_LABEL
 
 ; CHECK:   [[BAD]] (landing-pad):
 ; CHECK:     EH_LABEL

test/CodeGen/X86/GlobalISel/irtranslator-call.ll

 ; CHECK-NEXT:   maxAlignment:    0
 ; CHECK-NEXT:   adjustsStack:    false
 ; CHECK-NEXT:   hasCalls:        false
 ; CHECK-NEXT:   maxCallFrameSize: 0
 ; CHECK-NEXT:   hasOpaqueSPAdjustment: false
 ; CHECK-NEXT:   hasVAStart:      false
 ; CHECK-NEXT:   hasMustTailInVarArgFunc: false
 ; CHECK-NEXT: body:
-; CHECK-NEXT:   bb.1:
+; CHECK-NEXT:   bb.1.entry:
 ; CHECK-NEXT:     RET 0
 entry:
   ret void
 }