RuntimeDyldELF: add support for R_AARCH64_ADD_ABS_LO12_NC

[davide]

The code looks correct, but I left a comment inline.

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

417–421

This is correct, but while you're here, I'd rather see if you can have a common helper for all the relocations updating immediates in AArch64 instructions (e.g., ldr, str) as we do in lld (see or32AArch64Imm).

[evgeny777]

Addressed review comments.
Now lld and RuntimeDyldELF uses two identical sets of helper functions, so it probably makes sense to move them to header file and provide patch for lld.

[davide]

This looks much better now. Please split in two patches. The first one which does the refactoring, the second one which adds the new functionality. @lhames , what do you think?

[davide]

Minor comment inline.

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

42–45

Prefer the ternary operator here:
return (isBE) ? write<T, support::big>(...) : write<T, support:little>(...);

[davide]

In D28115#631088, @evgeny777 wrote:

Addressed review comments.
Now lld and RuntimeDyldELF uses two identical sets of helper functions, so it probably makes sense to move them to header file and provide patch for lld.

Maybe. I have no opinions on the topic (bluntly, I don't care), but there have been discussions recently about sharing code between the JIT and the static linker. You may want to check with the involved parties before going on, but I think it makes sense to do this as a follow-up.

[evgeny777]

So, can it be pushed as is?

[davide]

In D28115#631099, @evgeny777 wrote:

So, can it be pushed as is?

Yes, but please split the NFC changes from the functionality changes first.

[evgeny777]

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

42–45

Ok, but it's actually void.

[evgeny777]

Do you propose to push extra reloc first and than refactoring as a subsequent patch?

[davide]

In D28115#631102, @evgeny777 wrote:

Do you propose to push extra reloc first and than refactoring as a subsequent patch?

Either way.

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 using namespace llvm::object;
+using namespace llvm::support::endian;
 
 #define DEBUG_TYPE "dyld"
 
+static void or32le(void *P, int32_t V) { write32le(P, read32le(P) | V); }
+
+static void or32AArch64Imm(void *L, uint64_t Imm) {
+  or32le(L, (Imm & 0xFFF) << 10);
+}
+
+template <class T> static void write(bool isBE, void *P, T V) {
+  if (isBE)
+    write<T, support::big>(P, V);
+  else
+    write<T, support::little>(P, V);
+}
+
+static void write32AArch64Addr(void *L, uint64_t Imm) {
+  uint32_t ImmLo = (Imm & 0x3) << 29;
+  uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
+  uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
+  write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
+}
+
+// Return the bits [Start, End] from Val shifted Start bits.
+// For instance, getBits(0xF0, 4, 8) returns 0xF.
+static uint64_t getBits(uint64_t Val, int Start, int End) {
+  uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
+  return (Val >> Start) & Mask;
+}
+
 namespace {
 
 template <class ELFT> class DyldELFObject : public ELFObjectFile<ELFT> {
   LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
 
   typedef Elf_Shdr_Impl<ELFT> Elf_Shdr;
   typedef Elf_Sym_Impl<ELFT> Elf_Sym;
   typedef Elf_Rel_Impl<ELFT, false> Elf_Rel;
DEBUG(dbgs() << "resolveAArch64Relocation, LocalAddress: 0x"
                << " Value: 0x" << format("%llx", Value) << " Type: 0x"
                << format("%x", Type) << " Addend: 0x" << format("%llx", Addend)
                << "\n");
 
   switch (Type) {
   default:
     llvm_unreachable("Relocation type not implemented yet!");
     break;
-  case ELF::R_AARCH64_ABS64: {
-    uint64_t *TargetPtr =
-        reinterpret_cast<uint64_t *>(Section.getAddressWithOffset(Offset));
-    if (isBE)
-      support::ubig64_t::ref{TargetPtr} = Value + Addend;
-    else
-      support::ulittle64_t::ref{TargetPtr} = Value + Addend;
+  case ELF::R_AARCH64_ABS64:
+    write(isBE, TargetPtr, Value + Addend);
     break;
-  }
   case ELF::R_AARCH64_PREL32: {
     uint64_t Result = Value + Addend - FinalAddress;
     assert(static_cast<int64_t>(Result) >= INT32_MIN &&
            static_cast<int64_t>(Result) <= UINT32_MAX);
-    if (isBE)
-      support::ubig32_t::ref{TargetPtr} =
-        static_cast<uint32_t>(Result & 0xffffffffU);
-    else
-      support::ulittle32_t::ref{TargetPtr} =
-        static_cast<uint32_t>(Result & 0xffffffffU);
+    write(isBE, TargetPtr, static_cast<uint32_t>(Result & 0xffffffffU));
     break;
   }
   case ELF::R_AARCH64_CALL26: // fallthrough
   case ELF::R_AARCH64_JUMP26: {
     // Operation: S+A-P. Set Call or B immediate value to bits fff_fffc of the
     // calculation.
     uint64_t BranchImm = Value + Addend - FinalAddress;
-    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
-
-    // "Check that -2^27 <= result < 2^27".
     assert(isInt<28>(BranchImm));
 
-    // AArch64 code is emitted with .rela relocations. The data already in any
-    // bits affected by the relocation on entry is garbage.
-    TargetValue &= 0xfc000000U;
-    // Immediate goes in bits 25:0 of B and BL.
-    TargetValue |= static_cast<uint32_t>(BranchImm & 0xffffffcU) >> 2;
-    support::ulittle32_t::ref{TargetPtr} = TargetValue;
-    break;
-  }
-  case ELF::R_AARCH64_MOVW_UABS_G3: {
-    uint64_t Result = Value + Addend;
-    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
-
-    // AArch64 code is emitted with .rela relocations. The data already in any
-    // bits affected by the relocation on entry is garbage.
-    TargetValue &= 0xffe0001fU;
-    // Immediate goes in bits 20:5 of MOVZ/MOVK instruction
-    TargetValue |= ((Result & 0xffff000000000000ULL) >> (48 - 5));
-    // Shift must be "lsl #48", in bits 22:21
-    assert((TargetValue >> 21 & 0x3) == 3 && "invalid shift for relocation");
-    support::ulittle32_t::ref{TargetPtr} = TargetValue;
-    break;
-  }
-  case ELF::R_AARCH64_MOVW_UABS_G2_NC: {
-    uint64_t Result = Value + Addend;
-    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
-
-    // AArch64 code is emitted with .rela relocations. The data already in any
-    // bits affected by the relocation on entry is garbage.
-    TargetValue &= 0xffe0001fU;
-    // Immediate goes in bits 20:5 of MOVZ/MOVK instruction
-    TargetValue |= ((Result & 0xffff00000000ULL) >> (32 - 5));
-    // Shift must be "lsl #32", in bits 22:21
-    assert((TargetValue >> 21 & 0x3) == 2 && "invalid shift for relocation");
-    support::ulittle32_t::ref{TargetPtr} = TargetValue;
-    break;
-  }
-  case ELF::R_AARCH64_MOVW_UABS_G1_NC: {
-    uint64_t Result = Value + Addend;
-    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
-
-    // AArch64 code is emitted with .rela relocations. The data already in any
-    // bits affected by the relocation on entry is garbage.
-    TargetValue &= 0xffe0001fU;
-    // Immediate goes in bits 20:5 of MOVZ/MOVK instruction
-    TargetValue |= ((Result & 0xffff0000U) >> (16 - 5));
-    // Shift must be "lsl #16", in bits 22:2
-    assert((TargetValue >> 21 & 0x3) == 1 && "invalid shift for relocation");
-    support::ulittle32_t::ref{TargetPtr} = TargetValue;
-    break;
-  }
-  case ELF::R_AARCH64_MOVW_UABS_G0_NC: {
-    uint64_t Result = Value + Addend;
-    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
-
-    // AArch64 code is emitted with .rela relocations. The data already in any
-    // bits affected by the relocation on entry is garbage.
-    TargetValue &= 0xffe0001fU;
-    // Immediate goes in bits 20:5 of MOVZ/MOVK instruction
-    TargetValue |= ((Result & 0xffffU) << 5);
-    // Shift must be "lsl #0", in bits 22:21.
-    assert((TargetValue >> 21 & 0x3) == 0 && "invalid shift for relocation");
-    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+    // "Check that -2^27 <= result < 2^27".
+    or32le(TargetPtr, (BranchImm & 0x0FFFFFFC) >> 2);
     break;
   }
+  case ELF::R_AARCH64_MOVW_UABS_G3:
+    or32le(TargetPtr, ((Value + Addend) & 0xFFFF000000000000) >> 43);
+    break;
+  case ELF::R_AARCH64_MOVW_UABS_G2_NC:
+    or32le(TargetPtr, ((Value + Addend) & 0xFFFF00000000) >> 27);
+    break;
+  case ELF::R_AARCH64_MOVW_UABS_G1_NC:
+    or32le(TargetPtr, ((Value + Addend) & 0xFFFF0000) >> 11);
+    break;
+  case ELF::R_AARCH64_MOVW_UABS_G0_NC:
+    or32le(TargetPtr, ((Value + Addend) & 0xFFFF) << 5);
+    break;
   case ELF::R_AARCH64_ADR_PREL_PG_HI21: {
     // Operation: Page(S+A) - Page(P)
     uint64_t Result =
         ((Value + Addend) & ~0xfffULL) - (FinalAddress & ~0xfffULL);
-    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
 
     // Check that -2^32 <= X < 2^32
     assert(isInt<33>(Result) && "overflow check failed for relocation");
-
-    // AArch64 code is emitted with .rela relocations. The data already in any
-    // bits affected by the relocation on entry is garbage.
-    TargetValue &= 0x9f00001fU;
-    // Immediate goes in bits 30:29 + 5:23 of ADRP instruction, taken
-    // from bits 32:12 of X.
-    TargetValue |= ((Result & 0x3000U) << (29 - 12));
-    TargetValue |= ((Result & 0x1ffffc000ULL) >> (14 - 5));
-    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+    write32AArch64Addr(TargetPtr, Result >> 12);
     break;
   }
-  case ELF::R_AARCH64_LDST32_ABS_LO12_NC: {
+  case ELF::R_AARCH64_ADD_ABS_LO12_NC:
     // Operation: S + A
-    uint64_t Result = Value + Addend;
-    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
-
-    // AArch64 code is emitted with .rela relocations. The data already in any
-    // bits affected by the relocation on entry is garbage.
-    TargetValue &= 0xffc003ffU;
-    // Immediate goes in bits 21:10 of LD/ST instruction, taken
-    // from bits 11:2 of X
-    TargetValue |= ((Result & 0xffc) << (10 - 2));
-    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+    or32AArch64Imm(TargetPtr, Value + Addend);
     break;
-  }
-  case ELF::R_AARCH64_LDST64_ABS_LO12_NC: {
+  case ELF::R_AARCH64_LDST32_ABS_LO12_NC:
     // Operation: S + A
-    uint64_t Result = Value + Addend;
-    uint32_t TargetValue = support::ulittle32_t::ref{TargetPtr};
-
-    // AArch64 code is emitted with .rela relocations. The data already in any
-    // bits affected by the relocation on entry is garbage.
-    TargetValue &= 0xffc003ffU;
-    // Immediate goes in bits 21:10 of LD/ST instruction, taken
-    // from bits 11:3 of X
-    TargetValue |= ((Result & 0xff8) << (10 - 3));
-    support::ulittle32_t::ref{TargetPtr} = TargetValue;
+    or32AArch64Imm(TargetPtr, getBits(Value + Addend, 2, 11));
     break;
-  }
+  case ELF::R_AARCH64_LDST64_ABS_LO12_NC:
+    // Operation: S + A
+    or32AArch64Imm(TargetPtr, getBits(Value + Addend, 3, 11));
   }
 }
 
 void RuntimeDyldELF::resolveARMRelocation(const SectionEntry &Section,
                                           uint64_t Offset, uint32_t Value,
                                           uint32_t Type, int32_t Addend) {
   // TODO: Add Thumb relocations.
   uint32_t *TargetPtr =

test/ExecutionEngine/RuntimeDyld/AArch64/ELF_ARM64_relocations.s

 # RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o %T/reloc.o %s
 # RUN: llvm-rtdyld -triple=arm64-none-linux-gnu -verify -dummy-extern f=0x0123456789abcdef -check=%s %T/reloc.o
 
         .text
         .globl  g
         .p2align        2
         .type   g,@function
 g:
 # R_AARCH64_MOVW_UABS_G3
         movz    x0, #:abs_g3:f
 # R_AARCH64_MOVW_UABS_G2_NC
         movk    x0, #:abs_g2_nc:f
 # R_AARCH64_MOVW_UABS_G1_NC
         movk    x0, #:abs_g1_nc:f
 # R_AARCH64_MOVW_UABS_G0_NC
         movk    x0, #:abs_g0_nc:f
+a:
+# R_AARCH64_ADD_ABS_LO12_NC
+        add x0, x0, :lo12:f
         ret
         .Lfunc_end0:
         .size   g, .Lfunc_end0-g
 
         .type   k,@object
         .data
         .globl  k
         .p2align        3
 k:
         .xword  f
         .size   k, 8
 
 # rtdyld-check: *{4}(g) = 0xd2e02460
 # rtdyld-check: *{4}(g + 4) = 0xf2c8ace0
 # rtdyld-check: *{4}(g + 8) = 0xf2b13560
 # rtdyld-check: *{4}(g + 12) = 0xf299bde0
 # rtdyld-check: *{8}k = f
+
+## f & 0xFFF = 0xdef (bits 11:0 of f)
+## 0xdef << 10 = 0x37bc00
+# rtdyld-check: *{4}(a) = 0x9137bc00