[AArch64] Refactor LSE support as feature separate from V8.1a support.

[joelkevinjones]

Summary

This is preparation for ThunderX processors that have Large System Extension (LSE)
instructions, but not the other instructions introduced by V8.1a. This will mimic changes to GCC as described here: https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00388.html

LSE instructions are: LD/ST<op>, CAS*, SWP

[t.p.northover]

lib/Target/AArch64/AArch64.td

39

Can we expand "LSE" in the description here? I still can't actually think what it could mean.

[joelkevinjones]

Ping?

[t.p.northover]

So what is LSE, exactly?

[rengolin]

lib/Target/AArch64/AArch64.td

39

Ditto.

[joelkevinjones]

Added requested explanation of what LSE is.

[t.p.northover]

OK, I eventually managed to track it down to "large system extensions", I think we should include that somewhere. Probably alongside noting that it's the atomics because the link is decidedly non-obvious even with the expanded name.

[rengolin]

In D26621#605013, @t.p.northover wrote:

OK, I eventually managed to track it down to "large system extensions", I think we should include that somewhere. Probably alongside noting that it's the atomics because the link is decidedly non-obvious even with the expanded name.

I think the current description is better than if it just said "Large System Extension", as it actually tells you what it is about. :)

I don't mind as it is, or an additional comment just about the declaration. Everything else looks fine, too. Leaving to Tim to approve.

cheers,
--renato

[t.p.northover]

I think the current description is better than if it just said "Large System Extension", as it actually tells you what it is about. :)

I agree, I was pretty disappointed about how opaque it turned out to be. I still think it's better to have both though. Unexplained acronyms are really annoying.

Tim.

[joelkevinjones]

lib/Target/AArch64/AArch64.td

39

So line 39 should be:

"Enable ARMv8.1 atomic memory access Large System Extension (LSE) instructions">'

or:

"Enable ARMv8.1 Large System Extension (LSE) atomic memory access instructions">'

First, second, or something else?

[t.p.northover]

lib/Target/AArch64/AArch64.td

39

I vaguely prefer the second (and dark blue, really closer to navy but not quite; with yellow spots), but either would be fine. No need to reupload a patch, the rest looks fine to me.

include/llvm/Support/AArch64TargetParser.def

 #ifndef AARCH64_ARCH
 #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT)
 #endif
 AARCH64_ARCH("invalid", AK_INVALID, nullptr, nullptr,
              ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
 AARCH64_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
              FK_CRYPTO_NEON_FP_ARMV8,
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-              AArch64::AEK_SIMD))
+              AArch64::AEK_SIMD | AArch64::AEK_LSE))
 AARCH64_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a",
              ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-              AArch64::AEK_SIMD))
+              AArch64::AEK_SIMD | AArch64::AEK_LSE))
 AARCH64_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a",
              ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8,
              (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-              AArch64::AEK_SIMD | AArch64::AEK_RAS))
+              AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
 #undef AARCH64_ARCH
 
 #ifndef AARCH64_ARCH_EXT_NAME
 #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
 #endif
 // FIXME: This would be nicer were it tablegen
 AARCH64_ARCH_EXT_NAME("invalid",  AArch64::AEK_INVALID,  nullptr,  nullptr)
 AARCH64_ARCH_EXT_NAME("none",     AArch64::AEK_NONE,     nullptr,  nullptr)
 AARCH64_ARCH_EXT_NAME("crc",      AArch64::AEK_CRC,      "+crc",   "-crc")
+AARCH64_ARCH_EXT_NAME("lse",      AArch64::AEK_LSE,      "+lse",   "-lse")
 AARCH64_ARCH_EXT_NAME("crypto",   AArch64::AEK_CRYPTO,   "+crypto","-crypto")
 AARCH64_ARCH_EXT_NAME("fp",       AArch64::AEK_FP,       "+fp-armv8",  "-fp-armv8")
 AARCH64_ARCH_EXT_NAME("simd",     AArch64::AEK_SIMD,     "+neon",  "-neon")
 AARCH64_ARCH_EXT_NAME("fp16",     AArch64::AEK_FP16,     "+fullfp16",  "-fullfp16")
 AARCH64_ARCH_EXT_NAME("profile",     AArch64::AEK_PROFILE,     "+spe",  "-spe")
 AARCH64_ARCH_EXT_NAME("ras",     AArch64::AEK_RAS,     "+ras",  "-ras")
 #undef AARCH64_ARCH_EXT_NAME
 

include/llvm/Support/TargetParser.h

enum ArchExtKind : unsigned {
   AEK_INVALID = 0x0,
   AEK_NONE = 0x1,
   AEK_CRC = 0x2,
   AEK_CRYPTO = 0x4,
   AEK_FP = 0x8,
   AEK_SIMD = 0x10,
   AEK_FP16 = 0x20,
   AEK_PROFILE = 0x40,
-  AEK_RAS = 0x80
+  AEK_RAS = 0x80,
+  AEK_LSE = 0x100
 };
 
 StringRef getCanonicalArchName(StringRef Arch);
 
 // Information by ID
 StringRef getFPUName(unsigned FPUKind);
 unsigned getFPUVersion(unsigned FPUKind);
 unsigned getFPUNeonSupportLevel(unsigned FPUKind);

lib/Target/AArch64/AArch64.td

def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
   "Enable cryptographic instructions">;
 
 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
   "Enable ARMv8 CRC-32 checksum instructions">;
 
 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
 
+def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
+  "Enable ARMv8.1 LSE instructions">;
+
 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
   "Enable ARMv8 PMUv3 Performance Monitors extension">;
 
 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
   "Full FP16", [FeatureFPARMv8]>;
 
 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
   "Enable Statistical Profiling extension">;
def FeatureUseRSqrt : SubtargetFeature<
     "use-reciprocal-square-root", "UseRSqrt", "true",
     "Use the reciprocal square root approximation">;
 
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
-  "Support ARM v8.1a instructions", [FeatureCRC]>;
+  "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE]>;
 
 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
   "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 

lib/Target/AArch64/AArch64InstrFormats.td

 // CASP{<order>} <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>]
 // SWP{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
 // SWP{<order>} <Xs>, <Xt>, [<Xn|SP>]
 // LD<OP>{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
 // LD<OP>{<order>} <Xs>, <Xt>, [<Xn|SP>]
 // ST<OP>{<order>}[<size>] <Ws>, [<Xn|SP>]
 // ST<OP>{<order>} <Xs>, [<Xn|SP>]
 
-let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
+let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
 class BaseCASEncoding<dag oops, dag iops, string asm, string operands,
                       string cstr, list<dag> pattern>
       : I<oops, iops, asm, operands, cstr, pattern> {
   bits<2> Sz;
   bit NP;
   bit Acq;
   bit Rel;
   bits<5> Rs;
   bits<5> Rn;
   bits<5> Rt;
   let Inst{31-30} = Sz;
   let Inst{29-24} = 0b001000;
   let Inst{23} = NP;
   let Inst{22} = Acq;
   let Inst{21} = 0b1;
   let Inst{20-16} = Rs;
   let Inst{15} = Rel;
   let Inst{14-10} = 0b11111;
   let Inst{9-5} = Rn;
   let Inst{4-0} = Rt;
+  let Predicates = [HasLSE];
 }
 
 class BaseCAS<string order, string size, RegisterClass RC>
       : BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn),
                         "cas" # order # size, "\t$Rs, $Rt, [$Rn]",
                         "$out = $Rs",[]>,
         Sched<[WriteAtomic]> {
   let NP = 1;

 
 multiclass CompareAndSwapPair<bits<1> Acq, bits<1> Rel, string order> {
   let Sz = 0b00, Acq = Acq, Rel = Rel in 
     def s : BaseCASP<order, "", WSeqPairClassOperand>;
   let Sz = 0b01, Acq = Acq, Rel = Rel in 
     def d : BaseCASP<order, "", XSeqPairClassOperand>;
 }
 
-let Predicates = [HasV8_1a] in
+let Predicates = [HasLSE] in
 class BaseSWP<string order, string size, RegisterClass RC>
       : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "swp" # order # size,
           "\t$Rs, $Rt, [$Rn]","",[]>,
         Sched<[WriteAtomic]> {
   bits<2> Sz;
   bit Acq;
   bit Rel;
   bits<5> Rs;
   bits<3> opc = 0b000;
   bits<5> Rn;
   bits<5> Rt;
   let Inst{31-30} = Sz;
   let Inst{29-24} = 0b111000;
   let Inst{23} = Acq;
   let Inst{22} = Rel;
   let Inst{21} = 0b1;
   let Inst{20-16} = Rs;
   let Inst{15} = 0b1;
   let Inst{14-12} = opc;
   let Inst{11-10} = 0b00;
   let Inst{9-5} = Rn;
   let Inst{4-0} = Rt;
+  let Predicates = [HasLSE];
 }
 
 multiclass Swap<bits<1> Acq, bits<1> Rel, string order> {
   let Sz = 0b00, Acq = Acq, Rel = Rel in def b : BaseSWP<order, "b", GPR32>;
   let Sz = 0b01, Acq = Acq, Rel = Rel in def h : BaseSWP<order, "h", GPR32>;
   let Sz = 0b10, Acq = Acq, Rel = Rel in def s : BaseSWP<order, "", GPR32>;
   let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseSWP<order, "", GPR64>;
 }
 
-let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
+let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
 class BaseLDOPregister<string op, string order, string size, RegisterClass RC>
       : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "ld" # op # order # size,
           "\t$Rs, $Rt, [$Rn]","",[]>,
         Sched<[WriteAtomic]> {
   bits<2> Sz;
   bit Acq;
   bit Rel;
   bits<5> Rs;
   bits<3> opc;
   bits<5> Rn;
   bits<5> Rt;
   let Inst{31-30} = Sz;
   let Inst{29-24} = 0b111000;
   let Inst{23} = Acq;
   let Inst{22} = Rel;
   let Inst{21} = 0b1;
   let Inst{20-16} = Rs;
   let Inst{15} = 0b0;
   let Inst{14-12} = opc;
   let Inst{11-10} = 0b00;
   let Inst{9-5} = Rn;
   let Inst{4-0} = Rt;
+  let Predicates = [HasLSE];
 }
 
 multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel, 
                         string order> {
   let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in 
     def b : BaseLDOPregister<op, order, "b", GPR32>;
   let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in 
     def h : BaseLDOPregister<op, order, "h", GPR32>;
   let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in 
     def s : BaseLDOPregister<op, order, "", GPR32>;
   let Sz = 0b11, Acq = Acq, Rel = Rel, opc = opc in 
     def d : BaseLDOPregister<op, order, "", GPR64>;
 }
 
-let Predicates = [HasV8_1a] in
+let Predicates = [HasLSE] in
 class BaseSTOPregister<string asm, RegisterClass OP, Register Reg,
                         Instruction inst> :
       InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn)>;
 
 multiclass STOPregister<string asm, string instr> {
   def : BaseSTOPregister<asm # "lb", GPR32, WZR, 
                     !cast<Instruction>(instr # "Lb")>;
   def : BaseSTOPregister<asm # "lh", GPR32, WZR, 

lib/Target/AArch64/AArch64InstrInfo.td

 def HasFPARMv8       : Predicate<"Subtarget->hasFPARMv8()">,
                                AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
 def HasNEON          : Predicate<"Subtarget->hasNEON()">,
                                  AssemblerPredicate<"FeatureNEON", "neon">;
 def HasCrypto        : Predicate<"Subtarget->hasCrypto()">,
                                  AssemblerPredicate<"FeatureCrypto", "crypto">;
 def HasCRC           : Predicate<"Subtarget->hasCRC()">,
                                  AssemblerPredicate<"FeatureCRC", "crc">;
+def HasLSE           : Predicate<"Subtarget->hasLSE()">,
+                                 AssemblerPredicate<"FeatureLSE", "lse">;
 def HasRAS           : Predicate<"Subtarget->hasRAS()">,
                                  AssemblerPredicate<"FeatureRAS", "ras">;
 def HasPerfMon       : Predicate<"Subtarget->hasPerfMon()">;
 def HasFullFP16      : Predicate<"Subtarget->hasFullFP16()">,
                                  AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
 def HasSPE           : Predicate<"Subtarget->hasSPE()">,
                                  AssemblerPredicate<"FeatureSPE", "spe">;
 

lib/Target/AArch64/AArch64Subtarget.h

protected:
 
   bool HasV8_1aOps = false;
   bool HasV8_2aOps = false;
 
   bool HasFPARMv8 = false;
   bool HasNEON = false;
   bool HasCrypto = false;
   bool HasCRC = false;
+  bool HasLSE = false;
   bool HasRAS = false;
   bool HasPerfMon = false;
   bool HasFullFP16 = false;
   bool HasSPE = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
 
public:
 
   bool requiresStrictAlign() const { return StrictAlign; }
 
   bool isX18Reserved() const { return ReserveX18; }
   bool hasFPARMv8() const { return HasFPARMv8; }
   bool hasNEON() const { return HasNEON; }
   bool hasCrypto() const { return HasCrypto; }
   bool hasCRC() const { return HasCRC; }
+  bool hasLSE() const { return HasLSE; }
   bool hasRAS() const { return HasRAS; }
   bool balanceFPOps() const { return BalanceFPOps; }
   bool predictableSelectIsExpensive() const {
     return PredictableSelectIsExpensive;
   }
   bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
   bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
   bool avoidQuadLdStPairs() const { return AvoidQuadLdStPairs; }

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 } ExtensionMap[] = {
   { "crc", {AArch64::FeatureCRC} },
   { "crypto", {AArch64::FeatureCrypto} },
   { "fp", {AArch64::FeatureFPARMv8} },
   { "simd", {AArch64::FeatureNEON} },
   { "ras", {AArch64::FeatureRAS} },
 
   // FIXME: Unsupported extensions
-  { "lse", {} },
+  { "lse", {AArch64::FeatureLSE} },
   { "pan", {} },
   { "lor", {} },
   { "rdma", {} },
   { "profile", {} },
 };
 
 /// parseDirectiveArch
 ///   ::= .arch token

test/MC/AArch64/arm64v8.1-diagno-predicate.s

+// RUN: not llvm-mc  -triple=arm64-linux-gnu -mattr=armv8.1a -mattr=-lse < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+
+        casa  w5, w7, [x20]
+// CHECK-ERROR: error: instruction requires: lse
+// CHECK-ERROR-NEXT:        casa  w5, w7, [x20]
+// CHECK-ERROR-NEXT:        ^
+

test/MC/AArch64/directive-arch-negative.s

 # CHECK:  aese v0.8h, v1.8h
 # CHECK:  ^
 
   .arch armv8.1-a+noras
   esb
 
 # CHECK: error: instruction requires: ras
 # CHECK:         esb
+
+  .arch armv8.1-a+nolse
+        casa  w5, w7, [x20]
+
+# CHECK: error: instruction requires: lse
+# CHECK:        casa  w5, w7, [x20]

test/MC/AArch64/directive-cpu.s

// RUN: not llvm-mc -triple aarch64-unknown-none-eabi -filetype asm -o - %s 2>&1 | FileCheck %s
   .cpu generic+crypto+nocrc
 
   aesd v0.16b, v2.16b
 
   .cpu generic+nocrypto+crc
 
   aesd v0.16b, v2.16b
 
+  .cpu generic+v8.1a+nolse
+        casa  w5, w7, [x20]
+
+  .cpu generic+v8.1a+lse
+        casa  w5, w7, [x20]
+
 // NOTE: the errors precede the actual output!  The errors appear in order
 // though, so validate by hoisting them to the top and preservering relative
 // ordering
 
 // CHECK: error: instruction requires: fp-armv8
 // CHECK:   fminnm d0, d0, d1
 // CHECK:   ^
 
 // CHECK: error: instruction requires: neon
 // CHECK:   addp v0.4s, v0.4s, v0.4s
 // CHECK:   ^
 
 // CHECK: error: instruction requires: crc
 // CHECK:   crc32cx w0, w1, x3
 // CHECK:   ^
 
 // CHECK: error: instruction requires: crypto
 // CHECK:   aesd v0.16b, v2.16b
 // CHECK:   ^
 
+// CHECK: error: instruction requires: lse
+// CHECK:       casa  w5, w7, [x20]
+// CHECK:       ^
+
 // CHECK: fminnm d0, d0, d1
 // CHECK: fminnm d0, d0, d1
 // CHECK: addp v0.4s, v0.4s, v0.4s
 // CHECK: crc32cx w0, w1, x3
 // CHECK: aesd v0.16b, v2.16b
+// CHECK:       casa  w5, w7, [x20]