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Differential D25412

Move the global variables representing each Target behind accessor function
ClosedPublic

Authored by mehdi_amini on Oct 9 2016, 2:37 PM.

Details

Reviewers
chandlerc
• tstellarAMD
echristo
jlebar
Commits
rGf42454b94b03: Move the global variables representing each Target behind accessor function
rL283702: Move the global variables representing each Target behind accessor function
Summary

This avoids "static initialization order fiasco"

Diff Detail

Event Timeline

mehdi_amini updated this revision to Diff 74083.Oct 9 2016, 2:37 PM
mehdi_amini retitled this revision from to Move the global variables representing each Target behind accessor function.
mehdi_amini updated this object.
mehdi_amini added reviewers: echristo, chandlerc.
mehdi_amini added a subscriber: llvm-commits.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptOct 9 2016, 2:37 PM
Herald added subscribers: nhaehnle, nemanjai, jyknight and 4 others. · View Herald Transcript
jlebar added a subscriber: jlebar.Oct 9 2016, 3:19 PM
jlebar added inline comments.
lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
26

Add // namespace llvm?

lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
13–16

Typo? If not I'm not sure what you're trying to do here, probably deserves a comment.

15

Same for this function body -- if it's not a typo, it's not clear to me what you're trying to do, or why.

lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp
18–27

// namespace llvm?

lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp
21

"// namespace llvm"?

mehdi_amini updated this revision to Diff 74086.Oct 9 2016, 4:05 PM
mehdi_amini marked an inline comment as done.
mehdi_amini edited edge metadata.

Address Justin's comments.

Herald edited edge metadata. · View Herald TranscriptOct 9 2016, 4:05 PM
Herald added a subscriber: wdng. · View Herald Transcript
mehdi_amini marked 4 inline comments as done.Oct 9 2016, 4:05 PM
mehdi_amini added inline comments.
lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
15

That's the script I used to update all these that went wrong...
(And AVR is experimental so not built by default)

jlebar accepted this revision.Oct 9 2016, 4:07 PM
jlebar added a reviewer: jlebar.
jlebar added inline comments.
lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
14

Probably should be called TheAVRTarget?

This revision is now accepted and ready to land.Oct 9 2016, 4:07 PM
mehdi_amini marked an inline comment as done.Oct 9 2016, 4:09 PM

Thanks Justin!

lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp
14

Sure, did the change before committing.

ast added a subscriber: ast.Oct 9 2016, 5:14 PM

BPF bits look fine. Thanks

mehdi_amini closed this revision.Oct 9 2016, 8:24 PM

r283702

Revision Contents

PathSize
docs/
6 lines
include/
llvm/
Support/
9 lines
lib/
Target/
AArch64/
6 lines
6 lines
AsmParser/
6 lines
Disassembler/
12 lines
MCTargetDesc/
6 lines
8 lines
TargetInfo/
25 lines
AMDGPU/
4 lines
6 lines
4 lines
AsmParser/
4 lines
Disassembler/
6 lines
MCTargetDesc/
4 lines
13 lines
TargetInfo/
17 lines
ARM/
8 lines
8 lines
AsmParser/
8 lines
Disassembler/
8 lines
MCTargetDesc/
6 lines
18 lines
TargetInfo/
34 lines
AVR/
2 lines
2 lines
AsmParser/
2 lines
MCTargetDesc/
2 lines
19 lines
TargetInfo/
10 lines
BPF/
6 lines
6 lines
MCTargetDesc/
6 lines
27 lines
TargetInfo/
26 lines
Hexagon/
AsmParser/
2 lines
Disassembler/
2 lines
2 lines
2 lines
MCTargetDesc/
2 lines
20 lines
TargetInfo/
8 lines
Lanai/
AsmParser/
2 lines
Disassembler/
4 lines
2 lines
2 lines
3 lines
MCTargetDesc/
2 lines
23 lines
TargetInfo/
9 lines
MSP430/
MCTargetDesc/
2 lines
11 lines
2 lines
2 lines
TargetInfo/
11 lines
Mips/
AsmParser/
8 lines
Disassembler/
14 lines
MCTargetDesc/
8 lines
17 lines
8 lines
8 lines
TargetInfo/
31 lines
NVPTX/
MCTargetDesc/
4 lines
2 lines
4 lines
4 lines
4 lines
TargetInfo/
14 lines
PowerPC/
AsmParser/
6 lines
Disassembler/
6 lines
MCTargetDesc/
6 lines
3 lines
9 lines
6 lines
TargetInfo/
25 lines
Sparc/
AsmParser/
6 lines
Disassembler/
10 lines
MCTargetDesc/
6 lines
15 lines
6 lines
6 lines
TargetInfo/
21 lines
SystemZ/
AsmParser/
2 lines
Disassembler/
2 lines
MCTargetDesc/
2 lines
16 lines
2 lines
2 lines
TargetInfo/
9 lines
WebAssembly/
Disassembler/
4 lines
MCTargetDesc/
4 lines
3 lines
TargetInfo/
8 lines
4 lines
6 lines
X86/
AsmParser/
4 lines
Disassembler/
4 lines
MCTargetDesc/
3 lines
6 lines
TargetInfo/
17 lines
4 lines
4 lines

Diff 74086

docs/WritingAnLLVMBackend.rst

Show First 20 Lines • Show All 282 Lines • ▼ Show 20 Lines
All targets should declare a global ``Target`` object which is used to All targets should declare a global ``Target`` object which is used to
represent the target during registration. Then, in the target's ``TargetInfo`` represent the target during registration. Then, in the target's ``TargetInfo``
library, the target should define that object and use the ``RegisterTarget`` library, the target should define that object and use the ``RegisterTarget``
template to register the target. For example, the Sparc registration code template to register the target. For example, the Sparc registration code
looks like this: looks like this:
.. code-block:: c++ .. code-block:: c++
Target llvm::TheSparcTarget; Target llvm::getTheSparcTarget();
extern "C" void LLVMInitializeSparcTargetInfo() { extern "C" void LLVMInitializeSparcTargetInfo() {
RegisterTarget<Triple::sparc, /*HasJIT=*/false> RegisterTarget<Triple::sparc, /*HasJIT=*/false>
X(TheSparcTarget, "sparc", "Sparc"); X(getTheSparcTarget(), "sparc", "Sparc");
} }
This allows the ``TargetRegistry`` to look up the target by name or by target This allows the ``TargetRegistry`` to look up the target by name or by target
triple. In addition, most targets will also register additional features which triple. In addition, most targets will also register additional features which
are available in separate libraries. These registration steps are separate, are available in separate libraries. These registration steps are separate,
because some clients may wish to only link in some parts of the target --- the because some clients may wish to only link in some parts of the target --- the
JIT code generator does not require the use of the assembler printer, for JIT code generator does not require the use of the assembler printer, for
example. Here is an example of registering the Sparc assembly printer: example. Here is an example of registering the Sparc assembly printer:
.. code-block:: c++ .. code-block:: c++
extern "C" void LLVMInitializeSparcAsmPrinter() { extern "C" void LLVMInitializeSparcAsmPrinter() {
RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget); RegisterAsmPrinter<SparcAsmPrinter> X(getTheSparcTarget());
} }
For more information, see "`llvm/Target/TargetRegistry.h For more information, see "`llvm/Target/TargetRegistry.h
</doxygen/TargetRegistry_8h-source.html>`_". </doxygen/TargetRegistry_8h-source.html>`_".
Register Set and Register Classes Register Set and Register Classes
================================= =================================
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include/llvm/Support/TargetRegistry.h

Show First 20 Lines • Show All 843 Lines • ▼ Show 20 Lines
}; };
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// RegisterTarget - Helper template for registering a target, for use in the /// RegisterTarget - Helper template for registering a target, for use in the
/// target's initialization function. Usage: /// target's initialization function. Usage:
/// ///
/// ///
/// Target TheFooTarget; // The global target instance. /// Target &getTheFooTarget() { // The global target instance.
/// /// static Target TheFooTarget;
/// return TheFooTarget;
/// }
/// extern "C" void LLVMInitializeFooTargetInfo() { /// extern "C" void LLVMInitializeFooTargetInfo() {
/// RegisterTarget<Triple::foo> X(TheFooTarget, "foo", "Foo description"); /// RegisterTarget<Triple::foo> X(getTheFooTarget(), "foo", "Foo
/// description");
/// } /// }
template <Triple::ArchType TargetArchType = Triple::UnknownArch, template <Triple::ArchType TargetArchType = Triple::UnknownArch,
bool HasJIT = false> bool HasJIT = false>
struct RegisterTarget { struct RegisterTarget {
RegisterTarget(Target &T, const char *Name, const char *Desc) { RegisterTarget(Target &T, const char *Name, const char *Desc) {
TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch, HasJIT); TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch, HasJIT);
} }
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lib/Target/AArch64/AArch64AsmPrinter.cpp

Show First 20 Lines • Show All 571 Lines • ▼ Show 20 Linesvoid AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Finally, do the automated lowerings for everything else. // Finally, do the automated lowerings for everything else.
MCInst TmpInst; MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst); MCInstLowering.Lower(MI, TmpInst);
EmitToStreamer(*OutStreamer, TmpInst); EmitToStreamer(*OutStreamer, TmpInst);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeAArch64AsmPrinter() { extern "C" void LLVMInitializeAArch64AsmPrinter() {
RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64leTarget); RegisterAsmPrinter<AArch64AsmPrinter> X(getTheAArch64leTarget());
RegisterAsmPrinter<AArch64AsmPrinter> Y(TheAArch64beTarget); RegisterAsmPrinter<AArch64AsmPrinter> Y(getTheAArch64beTarget());
RegisterAsmPrinter<AArch64AsmPrinter> Z(TheARM64Target); RegisterAsmPrinter<AArch64AsmPrinter> Z(getTheARM64Target());
} }

lib/Target/AArch64/AArch64TargetMachine.cpp

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
static cl::opt<bool> static cl::opt<bool>
EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
cl::desc("Enable the loop data prefetch pass"), cl::desc("Enable the loop data prefetch pass"),
cl::init(true)); cl::init(true));
extern "C" void LLVMInitializeAArch64Target() { extern "C" void LLVMInitializeAArch64Target() {
// Register the target. // Register the target.
RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget); RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget); RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target); RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
auto PR = PassRegistry::getPassRegistry(); auto PR = PassRegistry::getPassRegistry();
initializeGlobalISel(*PR); initializeGlobalISel(*PR);
initializeAArch64A53Fix835769Pass(*PR); initializeAArch64A53Fix835769Pass(*PR);
initializeAArch64A57FPLoadBalancingPass(*PR); initializeAArch64A57FPLoadBalancingPass(*PR);
initializeAArch64AddressTypePromotionPass(*PR); initializeAArch64AddressTypePromotionPass(*PR);
initializeAArch64AdvSIMDScalarPass(*PR); initializeAArch64AdvSIMDScalarPass(*PR);
initializeAArch64CollectLOHPass(*PR); initializeAArch64CollectLOHPass(*PR);
initializeAArch64ConditionalComparesPass(*PR); initializeAArch64ConditionalComparesPass(*PR);
▲ Show 20 Lines • Show All 333 Lines • Show Last 20 Lines

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Show First 20 Lines • Show All 4,547 Lines • ▼ Show 20 LinesAArch64AsmParser::classifySymbolRef(const MCExpr *Expr,
// It's some symbol reference + a constant addend, but really // It's some symbol reference + a constant addend, but really
// shouldn't use both Darwin and ELF syntax. // shouldn't use both Darwin and ELF syntax.
return ELFRefKind == AArch64MCExpr::VK_INVALID || return ELFRefKind == AArch64MCExpr::VK_INVALID ||
DarwinRefKind == MCSymbolRefExpr::VK_None; DarwinRefKind == MCSymbolRefExpr::VK_None;
} }
/// Force static initialization. /// Force static initialization.
extern "C" void LLVMInitializeAArch64AsmParser() { extern "C" void LLVMInitializeAArch64AsmParser() {
RegisterMCAsmParser<AArch64AsmParser> X(TheAArch64leTarget); RegisterMCAsmParser<AArch64AsmParser> X(getTheAArch64leTarget());
RegisterMCAsmParser<AArch64AsmParser> Y(TheAArch64beTarget); RegisterMCAsmParser<AArch64AsmParser> Y(getTheAArch64beTarget());
RegisterMCAsmParser<AArch64AsmParser> Z(TheARM64Target); RegisterMCAsmParser<AArch64AsmParser> Z(getTheARM64Target());
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_SUBTARGET_FEATURE_NAME #define GET_SUBTARGET_FEATURE_NAME
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#include "AArch64GenAsmMatcher.inc" #include "AArch64GenAsmMatcher.inc"
// Define this matcher function after the auto-generated include so we // Define this matcher function after the auto-generated include so we
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 LinescreateAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
LLVMSymbolLookupCallback SymbolLookUp, LLVMSymbolLookupCallback SymbolLookUp,
void *DisInfo, MCContext *Ctx, void *DisInfo, MCContext *Ctx,
std::unique_ptr<MCRelocationInfo> &&RelInfo) { std::unique_ptr<MCRelocationInfo> &&RelInfo) {
return new llvm::AArch64ExternalSymbolizer(*Ctx, move(RelInfo), GetOpInfo, return new llvm::AArch64ExternalSymbolizer(*Ctx, move(RelInfo), GetOpInfo,
SymbolLookUp, DisInfo); SymbolLookUp, DisInfo);
} }
extern "C" void LLVMInitializeAArch64Disassembler() { extern "C" void LLVMInitializeAArch64Disassembler() {
TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget, TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
createAArch64Disassembler); createAArch64Disassembler);
TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget, TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
createAArch64Disassembler); createAArch64Disassembler);
TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget, TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
createAArch64ExternalSymbolizer); createAArch64ExternalSymbolizer);
TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget, TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
createAArch64ExternalSymbolizer); createAArch64ExternalSymbolizer);
TargetRegistry::RegisterMCDisassembler(TheARM64Target, TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
createAArch64Disassembler); createAArch64Disassembler);
TargetRegistry::RegisterMCSymbolizer(TheARM64Target, TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
createAArch64ExternalSymbolizer); createAArch64ExternalSymbolizer);
} }
static const unsigned FPR128DecoderTable[] = { static const unsigned FPR128DecoderTable[] = {
AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
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lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

Show All 29 Lines
class MCTargetOptions; class MCTargetOptions;
class MCTargetStreamer; class MCTargetStreamer;
class StringRef; class StringRef;
class Target; class Target;
class Triple; class Triple;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheAArch64leTarget; Target &getTheAArch64leTarget();
extern Target TheAArch64beTarget; Target &getTheAArch64beTarget();
extern Target TheARM64Target; Target &getTheARM64Target();
MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createAArch64leAsmBackend(const Target &T, MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU, const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
Show All 38 Lines

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
} }
static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) { static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
return new MCInstrAnalysis(Info); return new MCInstrAnalysis(Info);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeAArch64TargetMC() { extern "C" void LLVMInitializeAArch64TargetMC() {
for (Target *T : for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
{&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) { &getTheARM64Target()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
// Register the MC codegen info. // Register the MC codegen info.
TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts); TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
Show All 21 Lines for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
// Register the asm streamer. // Register the asm streamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, TargetRegistry::RegisterAsmTargetStreamer(*T,
createAArch64AsmTargetStreamer); createAArch64AsmTargetStreamer);
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter); TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
} }
// Register the asm backend. // Register the asm backend.
for (Target *T : {&TheAArch64leTarget, &TheARM64Target}) for (Target *T : {&getTheAArch64leTarget(), &getTheARM64Target()})
TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend); TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget, TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),
createAArch64beAsmBackend); createAArch64beAsmBackend);
} }

lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp

//===-- AArch64TargetInfo.cpp - AArch64 Target Implementation -----------------===// //===-- AArch64TargetInfo.cpp - AArch64 Target Implementation -----------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/ADT/Triple.h" #include "llvm/ADT/Triple.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
namespace llvm { namespace llvm {
Target TheAArch64leTarget; Target &getTheAArch64leTarget() {
Target TheAArch64beTarget; static Target TheAArch64leTarget;
Target TheARM64Target; return TheAArch64leTarget;
} // end namespace llvm }
Target &getTheAArch64beTarget() {
static Target TheAArch64beTarget;
return TheAArch64beTarget;
}
Target &getTheARM64Target() {
static Target TheARM64Target;
return TheARM64Target;
}
} // namespace llvm
jlebarUnsubmitted
Done
ReplyInline Actions

Add // namespace llvm?

jlebar: Add `// namespace llvm`?
extern "C" void LLVMInitializeAArch64TargetInfo() { extern "C" void LLVMInitializeAArch64TargetInfo() {
// Now register the "arm64" name for use with "-march". We don't want it to // Now register the "arm64" name for use with "-march". We don't want it to
// take possession of the Triple::aarch64 tag though. // take possession of the Triple::aarch64 tag though.
TargetRegistry::RegisterTarget(TheARM64Target, "arm64", TargetRegistry::RegisterTarget(getTheARM64Target(), "arm64",
"ARM64 (little endian)", "ARM64 (little endian)",
[](Triple::ArchType) { return false; }, true); [](Triple::ArchType) { return false; }, true);
RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z( RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z(
TheAArch64leTarget, "aarch64", "AArch64 (little endian)"); getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)");
RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W( RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W(
TheAArch64beTarget, "aarch64_be", "AArch64 (big endian)"); getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)");
} }

lib/Target/AMDGPU/AMDGPU.h

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
extern char &SIAnnotateControlFlowPassID; extern char &SIAnnotateControlFlowPassID;
void initializeSIDebuggerInsertNopsPass(PassRegistry&); void initializeSIDebuggerInsertNopsPass(PassRegistry&);
extern char &SIDebuggerInsertNopsID; extern char &SIDebuggerInsertNopsID;
void initializeSIInsertWaitsPass(PassRegistry&); void initializeSIInsertWaitsPass(PassRegistry&);
extern char &SIInsertWaitsID; extern char &SIInsertWaitsID;
extern Target TheAMDGPUTarget; Target &getTheAMDGPUTarget();
extern Target TheGCNTarget; Target &getTheGCNTarget();
namespace AMDGPU { namespace AMDGPU {
enum TargetIndex { enum TargetIndex {
TI_CONSTDATA_START, TI_CONSTDATA_START,
TI_SCRATCH_RSRC_DWORD0, TI_SCRATCH_RSRC_DWORD0,
TI_SCRATCH_RSRC_DWORD1, TI_SCRATCH_RSRC_DWORD1,
TI_SCRATCH_RSRC_DWORD2, TI_SCRATCH_RSRC_DWORD2,
TI_SCRATCH_RSRC_DWORD3 TI_SCRATCH_RSRC_DWORD3
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lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

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static AsmPrinter * static AsmPrinter *
createAMDGPUAsmPrinterPass(TargetMachine &tm, createAMDGPUAsmPrinterPass(TargetMachine &tm,
std::unique_ptr<MCStreamer> &&Streamer) { std::unique_ptr<MCStreamer> &&Streamer) {
return new AMDGPUAsmPrinter(tm, std::move(Streamer)); return new AMDGPUAsmPrinter(tm, std::move(Streamer));
} }
extern "C" void LLVMInitializeAMDGPUAsmPrinter() { extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass); TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass); createAMDGPUAsmPrinterPass);
TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
createAMDGPUAsmPrinterPass);
} }
AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
std::unique_ptr<MCStreamer> Streamer) std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer)) {} : AsmPrinter(TM, std::move(Streamer)) {}
StringRef AMDGPUAsmPrinter::getPassName() const { StringRef AMDGPUAsmPrinter::getPassName() const {
return "AMDGPU Assembly Printer"; return "AMDGPU Assembly Printer";
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lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
static cl::opt<bool> EnableLoadStoreVectorizer( static cl::opt<bool> EnableLoadStoreVectorizer(
"amdgpu-load-store-vectorizer", "amdgpu-load-store-vectorizer",
cl::desc("Enable load store vectorizer"), cl::desc("Enable load store vectorizer"),
cl::init(true), cl::init(true),
cl::Hidden); cl::Hidden);
extern "C" void LLVMInitializeAMDGPUTarget() { extern "C" void LLVMInitializeAMDGPUTarget() {
// Register the target // Register the target
RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget); RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget); RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
PassRegistry *PR = PassRegistry::getPassRegistry(); PassRegistry *PR = PassRegistry::getPassRegistry();
initializeSILowerI1CopiesPass(*PR); initializeSILowerI1CopiesPass(*PR);
initializeSIFixSGPRCopiesPass(*PR); initializeSIFixSGPRCopiesPass(*PR);
initializeSIFoldOperandsPass(*PR); initializeSIFoldOperandsPass(*PR);
initializeSIShrinkInstructionsPass(*PR); initializeSIShrinkInstructionsPass(*PR);
initializeSIFixControlFlowLiveIntervalsPass(*PR); initializeSIFixControlFlowLiveIntervalsPass(*PR);
initializeSILoadStoreOptimizerPass(*PR); initializeSILoadStoreOptimizerPass(*PR);
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lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Show First 20 Lines • Show All 3,046 Lines • ▼ Show 20 Lines if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa) {
std::advance(it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2)); std::advance(it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));
Inst.insert(it, Inst.getOperand(0)); // src2 = dst Inst.insert(it, Inst.getOperand(0)); // src2 = dst
} }
} }
/// Force static initialization. /// Force static initialization.
extern "C" void LLVMInitializeAMDGPUAsmParser() { extern "C" void LLVMInitializeAMDGPUAsmParser() {
RegisterMCAsmParser<AMDGPUAsmParser> A(TheAMDGPUTarget); RegisterMCAsmParser<AMDGPUAsmParser> A(getTheAMDGPUTarget());
RegisterMCAsmParser<AMDGPUAsmParser> B(TheGCNTarget); RegisterMCAsmParser<AMDGPUAsmParser> B(getTheGCNTarget());
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#include "AMDGPUGenAsmMatcher.inc" #include "AMDGPUGenAsmMatcher.inc"
// This fuction should be defined after auto-generated include so that we have // This fuction should be defined after auto-generated include so that we have
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lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Show First 20 Lines • Show All 489 Lines • ▼ Show 20 Lines
static MCDisassembler *createAMDGPUDisassembler(const Target &T, static MCDisassembler *createAMDGPUDisassembler(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new AMDGPUDisassembler(STI, Ctx); return new AMDGPUDisassembler(STI, Ctx);
} }
extern "C" void LLVMInitializeAMDGPUDisassembler() { extern "C" void LLVMInitializeAMDGPUDisassembler() {
TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler); TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
TargetRegistry::RegisterMCSymbolizer(TheGCNTarget, createAMDGPUSymbolizer); createAMDGPUDisassembler);
TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
createAMDGPUSymbolizer);
} }

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h

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class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class StringRef; class StringRef;
class Target; class Target;
class Triple; class Triple;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheAMDGPUTarget; Target &getTheAMDGPUTarget();
extern Target TheGCNTarget; Target &getTheGCNTarget();
MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
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lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Linesstatic MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
MCCodeEmitter *Emitter, bool RelaxAll) { MCCodeEmitter *Emitter, bool RelaxAll) {
if (T.getOS() == Triple::AMDHSA) if (T.getOS() == Triple::AMDHSA)
return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll); return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll); return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
} }
extern "C" void LLVMInitializeAMDGPUTargetMC() { extern "C" void LLVMInitializeAMDGPUTargetMC() {
for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) { for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T); RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter); TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend); TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
} }
// R600 specific registration // R600 specific registration
TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget, TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
createR600MCCodeEmitter); createR600MCCodeEmitter);
// GCN specific registration // GCN specific registration
TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
createSIMCCodeEmitter);
TargetRegistry::RegisterAsmTargetStreamer(TheGCNTarget, TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
createAMDGPUAsmTargetStreamer); createAMDGPUAsmTargetStreamer);
TargetRegistry::RegisterObjectTargetStreamer(TheGCNTarget, TargetRegistry::RegisterObjectTargetStreamer(
createAMDGPUObjectTargetStreamer); getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
} }

lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp

Show All 12 Lines
#include "AMDGPUTargetMachine.h" #include "AMDGPUTargetMachine.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
/// \brief The target which suports all AMD GPUs. This will eventually /// \brief The target which suports all AMD GPUs. This will eventually
/// be deprecated and there will be a R600 target and a GCN target. /// be deprecated and there will be a R600 target and a GCN target.
Target llvm::TheAMDGPUTarget; Target &llvm::getTheAMDGPUTarget() {
static Target TheAMDGPUTarget;
return TheAMDGPUTarget;
}
/// \brief The target for GCN GPUs /// \brief The target for GCN GPUs
Target llvm::TheGCNTarget; Target &llvm::getTheGCNTarget() {
static Target TheGCNTarget;
return TheGCNTarget;
}
/// \brief Extern function to initialize the targets for the AMDGPU backend /// \brief Extern function to initialize the targets for the AMDGPU backend
extern "C" void LLVMInitializeAMDGPUTargetInfo() { extern "C" void LLVMInitializeAMDGPUTargetInfo() {
RegisterTarget<Triple::r600, false> RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600",
R600(TheAMDGPUTarget, "r600", "AMD GPUs HD2XXX-HD6XXX"); "AMD GPUs HD2XXX-HD6XXX");
RegisterTarget<Triple::amdgcn, false> GCN(TheGCNTarget, "amdgcn", "AMD GCN GPUs"); RegisterTarget<Triple::amdgcn, false> GCN(getTheGCNTarget(), "amdgcn",
"AMD GCN GPUs");
} }

lib/Target/ARM/ARMAsmPrinter.cpp

Show First 20 Lines • Show All 2,058 Lines • ▼ Show 20 Lines
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Target Registry Stuff // Target Registry Stuff
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeARMAsmPrinter() { extern "C" void LLVMInitializeARMAsmPrinter() {
RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget); RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget); RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget); RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget); RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());
} }

lib/Target/ARM/ARMTargetMachine.cpp

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
// FIXME: Unify control over GlobalMerge. // FIXME: Unify control over GlobalMerge.
static cl::opt<cl::boolOrDefault> static cl::opt<cl::boolOrDefault>
EnableGlobalMerge("arm-global-merge", cl::Hidden, EnableGlobalMerge("arm-global-merge", cl::Hidden,
cl::desc("Enable the global merge pass")); cl::desc("Enable the global merge pass"));
extern "C" void LLVMInitializeARMTarget() { extern "C" void LLVMInitializeARMTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget); RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget); RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget); RegisterTargetMachine<ThumbLETargetMachine> A(getTheThumbLETarget());
RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget); RegisterTargetMachine<ThumbBETargetMachine> B(getTheThumbBETarget());
PassRegistry &Registry = *PassRegistry::getPassRegistry(); PassRegistry &Registry = *PassRegistry::getPassRegistry();
initializeARMLoadStoreOptPass(Registry); initializeARMLoadStoreOptPass(Registry);
initializeARMPreAllocLoadStoreOptPass(Registry); initializeARMPreAllocLoadStoreOptPass(Registry);
} }
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
if (TT.isOSBinFormatMachO()) if (TT.isOSBinFormatMachO())
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lib/Target/ARM/AsmParser/ARMAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 10,402 Lines • ▼ Show 20 Lines if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
return true; return true;
getTargetStreamer().emitThumbSet(Sym, Value); getTargetStreamer().emitThumbSet(Sym, Value);
return false; return false;
} }
/// Force static initialization. /// Force static initialization.
extern "C" void LLVMInitializeARMAsmParser() { extern "C" void LLVMInitializeARMAsmParser() {
RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget); RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget); RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget); RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget); RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_SUBTARGET_FEATURE_NAME #define GET_SUBTARGET_FEATURE_NAME
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#include "ARMGenAsmMatcher.inc" #include "ARMGenAsmMatcher.inc"
// FIXME: This structure should be moved inside ARMTargetParser // FIXME: This structure should be moved inside ARMTargetParser
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lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Show First 20 Lines • Show All 855 Lines • ▼ Show 20 LinesDecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
} }
Size = 0; Size = 0;
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
extern "C" void LLVMInitializeARMDisassembler() { extern "C" void LLVMInitializeARMDisassembler() {
TargetRegistry::RegisterMCDisassembler(TheARMLETarget, TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
createARMDisassembler); createARMDisassembler);
TargetRegistry::RegisterMCDisassembler(TheARMBETarget, TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
createARMDisassembler); createARMDisassembler);
TargetRegistry::RegisterMCDisassembler(TheThumbLETarget, TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
createThumbDisassembler); createThumbDisassembler);
TargetRegistry::RegisterMCDisassembler(TheThumbBETarget, TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
createThumbDisassembler); createThumbDisassembler);
} }
static const uint16_t GPRDecoderTable[] = { static const uint16_t GPRDecoderTable[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R12, ARM::SP, ARM::LR, ARM::PC ARM::R12, ARM::SP, ARM::LR, ARM::PC
▲ Show 20 Lines • Show All 4,435 Lines • Show Last 20 Lines

lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

Show All 31 Lines
class MCRelocationInfo; class MCRelocationInfo;
class MCTargetStreamer; class MCTargetStreamer;
class StringRef; class StringRef;
class Target; class Target;
class Triple; class Triple;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheARMLETarget, TheThumbLETarget; Target &getTheARMLETarget();
extern Target TheARMBETarget, TheThumbBETarget; Target &getTheThumbLETarget();
Target &getTheARMBETarget();
Target &getTheThumbBETarget();
namespace ARM_MC { namespace ARM_MC {
std::string ParseARMTriple(const Triple &TT, StringRef CPU); std::string ParseARMTriple(const Triple &TT, StringRef CPU);
/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
/// do not need to go through TargetRegistry. /// do not need to go through TargetRegistry.
MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS); StringRef FS);
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lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

Show First 20 Lines • Show All 268 Lines • ▼ Show 20 Lines
} }
static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) { static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
return new ARMMCInstrAnalysis(Info); return new ARMMCInstrAnalysis(Info);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeARMTargetMC() { extern "C" void LLVMInitializeARMTargetMC() {
for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget, for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
&TheThumbBETarget}) { &getTheThumbLETarget(), &getTheThumbBETarget()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);
Show All 22 Lines for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter); TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);
// Register the MC relocation info. // Register the MC relocation info.
TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo); TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);
} }
// Register the MC Code Emitter // Register the MC Code Emitter
for (Target *T : {&TheARMLETarget, &TheThumbLETarget}) for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()})
TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);
for (Target *T : {&TheARMBETarget, &TheThumbBETarget}) for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()})
TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);
// Register the asm backend. // Register the asm backend.
TargetRegistry::RegisterMCAsmBackend(TheARMLETarget, createARMLEAsmBackend); TargetRegistry::RegisterMCAsmBackend(getTheARMLETarget(),
TargetRegistry::RegisterMCAsmBackend(TheARMBETarget, createARMBEAsmBackend); createARMLEAsmBackend);
TargetRegistry::RegisterMCAsmBackend(TheThumbLETarget, TargetRegistry::RegisterMCAsmBackend(getTheARMBETarget(),
createARMBEAsmBackend);
TargetRegistry::RegisterMCAsmBackend(getTheThumbLETarget(),
createThumbLEAsmBackend); createThumbLEAsmBackend);
TargetRegistry::RegisterMCAsmBackend(TheThumbBETarget, TargetRegistry::RegisterMCAsmBackend(getTheThumbBETarget(),
createThumbBEAsmBackend); createThumbBEAsmBackend);
} }

lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp

//===-- ARMTargetInfo.cpp - ARM Target Implementation ---------------------===// //===-- ARMTargetInfo.cpp - ARM Target Implementation ---------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MCTargetDesc/ARMMCTargetDesc.h" #include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::TheARMLETarget, llvm::TheARMBETarget; Target &llvm::getTheARMLETarget() {
Target llvm::TheThumbLETarget, llvm::TheThumbBETarget; static Target TheARMLETarget;
return TheARMLETarget;
}
Target &llvm::getTheARMBETarget() {
static Target TheARMBETarget;
return TheARMBETarget;
}
Target &llvm::getTheThumbLETarget() {
static Target TheThumbLETarget;
return TheThumbLETarget;
}
Target &llvm::getTheThumbBETarget() {
static Target TheThumbBETarget;
return TheThumbBETarget;
}
extern "C" void LLVMInitializeARMTargetInfo() { extern "C" void LLVMInitializeARMTargetInfo() {
RegisterTarget<Triple::arm, /*HasJIT=*/true> RegisterTarget<Triple::arm, /*HasJIT=*/true> X(getTheARMLETarget(), "arm",
X(TheARMLETarget, "arm", "ARM"); "ARM");
RegisterTarget<Triple::armeb, /*HasJIT=*/true> RegisterTarget<Triple::armeb, /*HasJIT=*/true> Y(getTheARMBETarget(), "armeb",
Y(TheARMBETarget, "armeb", "ARM (big endian)"); "ARM (big endian)");
RegisterTarget<Triple::thumb, /*HasJIT=*/true> RegisterTarget<Triple::thumb, /*HasJIT=*/true> A(getTheThumbLETarget(),
A(TheThumbLETarget, "thumb", "Thumb"); "thumb", "Thumb");
RegisterTarget<Triple::thumbeb, /*HasJIT=*/true> RegisterTarget<Triple::thumbeb, /*HasJIT=*/true> B(
B(TheThumbBETarget, "thumbeb", "Thumb (big endian)"); getTheThumbBETarget(), "thumbeb", "Thumb (big endian)");
} }

lib/Target/AVR/AVRAsmPrinter.cpp

Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Linesvoid AVRAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst I; MCInst I;
MCInstLowering.lowerInstruction(*MI, I); MCInstLowering.lowerInstruction(*MI, I);
EmitToStreamer(*OutStreamer, I); EmitToStreamer(*OutStreamer, I);
} }
} // end of namespace llvm } // end of namespace llvm
extern "C" void LLVMInitializeAVRAsmPrinter() { extern "C" void LLVMInitializeAVRAsmPrinter() {
llvm::RegisterAsmPrinter<llvm::AVRAsmPrinter> X(llvm::TheAVRTarget); llvm::RegisterAsmPrinter<llvm::AVRAsmPrinter> X(llvm::getTheAVRTarget());
} }

lib/Target/AVR/AVRTargetMachine.cpp

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
} // namespace } // namespace
TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) { TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
return new AVRPassConfig(this, PM); return new AVRPassConfig(this, PM);
} }
extern "C" void LLVMInitializeAVRTarget() { extern "C" void LLVMInitializeAVRTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<AVRTargetMachine> X(TheAVRTarget); RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
} }
const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const { const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
return &SubTarget; return &SubTarget;
} }
const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const { const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
return &SubTarget; return &SubTarget;
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lib/Target/AVR/AsmParser/AVRAsmParser.cpp

Show First 20 Lines • Show All 576 Lines • ▼ Show 20 Linesbool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
} }
Parser.Lex(); // Consume the EndOfStatement Parser.Lex(); // Consume the EndOfStatement
return false; return false;
} }
bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) { return true; } bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) { return true; }
extern "C" void LLVMInitializeAVRAsmParser() { extern "C" void LLVMInitializeAVRAsmParser() {
RegisterMCAsmParser<AVRAsmParser> X(TheAVRTarget); RegisterMCAsmParser<AVRAsmParser> X(getTheAVRTarget());
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#include "AVRGenAsmMatcher.inc" #include "AVRGenAsmMatcher.inc"
// Uses enums defined in AVRGenAsmMatcher.inc // Uses enums defined in AVRGenAsmMatcher.inc
unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
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lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h

Show All 24 Lines
class MCObjectWriter; class MCObjectWriter;
class MCRegisterInfo; class MCRegisterInfo;
class MCTargetOptions; class MCTargetOptions;
class StringRef; class StringRef;
class Target; class Target;
class Triple; class Triple;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheAVRTarget; Target &getTheAVRTarget();
/// Creates a machine code emitter for AVR. /// Creates a machine code emitter for AVR.
MCCodeEmitter *createAVRMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createAVRMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
/// Creates an assembly backend for AVR. /// Creates an assembly backend for AVR.
MCAsmBackend *createAVRAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createAVRAsmBackend(const Target &T, const MCRegisterInfo &MRI,
Show All 18 Lines

lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Linesstatic MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S,
formatted_raw_ostream &OS, formatted_raw_ostream &OS,
MCInstPrinter *InstPrint, MCInstPrinter *InstPrint,
bool isVerboseAsm) { bool isVerboseAsm) {
return new AVRTargetAsmStreamer(S); return new AVRTargetAsmStreamer(S);
} }
extern "C" void LLVMInitializeAVRTargetMC() { extern "C" void LLVMInitializeAVRTargetMC() {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfo<AVRMCAsmInfo> X(TheAVRTarget); RegisterMCAsmInfo<AVRMCAsmInfo> X(getTheAVRTarget());
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheAVRTarget, createAVRMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(getTheAVRTarget(), createAVRMCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(TheAVRTarget, createAVRMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(getTheAVRTarget(), createAVRMCRegisterInfo);
// Register the MC subtarget info. // Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheAVRTarget, TargetRegistry::RegisterMCSubtargetInfo(getTheAVRTarget(),
createAVRMCSubtargetInfo); createAVRMCSubtargetInfo);
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(TheAVRTarget, createAVRMCInstPrinter); TargetRegistry::RegisterMCInstPrinter(getTheAVRTarget(),
createAVRMCInstPrinter);
// Register the ELF streamer // Register the ELF streamer
TargetRegistry::RegisterELFStreamer(TheAVRTarget, createMCStreamer); TargetRegistry::RegisterELFStreamer(getTheAVRTarget(), createMCStreamer);
// Register the obj target streamer. // Register the obj target streamer.
TargetRegistry::RegisterObjectTargetStreamer(TheAVRTarget, TargetRegistry::RegisterObjectTargetStreamer(getTheAVRTarget(),
createAVRObjectTargetStreamer); createAVRObjectTargetStreamer);
// Register the asm target streamer. // Register the asm target streamer.
TargetRegistry::RegisterAsmTargetStreamer(TheAVRTarget, TargetRegistry::RegisterAsmTargetStreamer(getTheAVRTarget(),
createMCAsmTargetStreamer); createMCAsmTargetStreamer);
// Register the asm backend (as little endian). // Register the asm backend (as little endian).
TargetRegistry::RegisterMCAsmBackend(TheAVRTarget, createAVRAsmBackend); TargetRegistry::RegisterMCAsmBackend(getTheAVRTarget(), createAVRAsmBackend);
} }

lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp

//===-- AVRTargetInfo.cpp - AVR Target Implementation ---------------------===// //===-- AVRTargetInfo.cpp - AVR Target Implementation ---------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
namespace llvm { namespace llvm {
Target TheAVRTarget; Target &getTheAVRTarget() {
static Target getTheAVRTarget;
jlebarUnsubmitted
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Probably should be called TheAVRTarget?

jlebar: Probably should be called TheAVRTarget?
mehdi_aminiAuthorUnsubmitted
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Sure, did the change before committing.

mehdi_amini: Sure, did the change before committing.
return getTheAVRTarget;
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Same for this function body -- if it's not a typo, it's not clear to me what you're trying to do, or why.

jlebar: Same for this function body -- if it's not a typo, it's not clear to me what you're trying to…
mehdi_aminiAuthorUnsubmitted
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That's the script I used to update all these that went wrong...
(And AVR is experimental so not built by default)

mehdi_amini: That's the script I used to update all these that went wrong... (And AVR is experimental so not…
}
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Typo? If not I'm not sure what you're trying to do here, probably deserves a comment.

jlebar: Typo? If not I'm not sure what you're trying to do here, probably deserves a comment.
} }
extern "C" void LLVMInitializeAVRTargetInfo() { extern "C" void LLVMInitializeAVRTargetInfo() {
llvm::RegisterTarget<llvm::Triple::avr> X( llvm::RegisterTarget<llvm::Triple::avr> X(llvm::getTheAVRTarget(), "avr",
llvm::TheAVRTarget, "avr", "Atmel AVR Microcontroller"); "Atmel AVR Microcontroller");
} }

lib/Target/BPF/BPFAsmPrinter.cpp

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesvoid BPFAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst TmpInst; MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst); MCInstLowering.Lower(MI, TmpInst);
EmitToStreamer(*OutStreamer, TmpInst); EmitToStreamer(*OutStreamer, TmpInst);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeBPFAsmPrinter() { extern "C" void LLVMInitializeBPFAsmPrinter() {
RegisterAsmPrinter<BPFAsmPrinter> X(TheBPFleTarget); RegisterAsmPrinter<BPFAsmPrinter> X(getTheBPFleTarget());
RegisterAsmPrinter<BPFAsmPrinter> Y(TheBPFbeTarget); RegisterAsmPrinter<BPFAsmPrinter> Y(getTheBPFbeTarget());
RegisterAsmPrinter<BPFAsmPrinter> Z(TheBPFTarget); RegisterAsmPrinter<BPFAsmPrinter> Z(getTheBPFTarget());
} }

lib/Target/BPF/BPFTargetMachine.cpp

Show All 18 Lines
#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/FormattedStream.h" #include "llvm/Support/FormattedStream.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
using namespace llvm; using namespace llvm;
extern "C" void LLVMInitializeBPFTarget() { extern "C" void LLVMInitializeBPFTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<BPFTargetMachine> X(TheBPFleTarget); RegisterTargetMachine<BPFTargetMachine> X(getTheBPFleTarget());
RegisterTargetMachine<BPFTargetMachine> Y(TheBPFbeTarget); RegisterTargetMachine<BPFTargetMachine> Y(getTheBPFbeTarget());
RegisterTargetMachine<BPFTargetMachine> Z(TheBPFTarget); RegisterTargetMachine<BPFTargetMachine> Z(getTheBPFTarget());
} }
// DataLayout: little or big endian // DataLayout: little or big endian
static std::string computeDataLayout(const Triple &TT) { static std::string computeDataLayout(const Triple &TT) {
if (TT.getArch() == Triple::bpfeb) if (TT.getArch() == Triple::bpfeb)
return "E-m:e-p:64:64-i64:64-n32:64-S128"; return "E-m:e-p:64:64-i64:64-n32:64-S128";
else else
return "e-m:e-p:64:64-i64:64-n32:64-S128"; return "e-m:e-p:64:64-i64:64-n32:64-S128";
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h

Show All 26 Lines
class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class StringRef; class StringRef;
class Target; class Target;
class Triple; class Triple;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheBPFleTarget; Target &getTheBPFleTarget();
extern Target TheBPFbeTarget; Target &getTheBPFbeTarget();
extern Target TheBPFTarget; Target &getTheBPFTarget();
MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
Show All 26 Lines

lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Linesstatic MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new BPFInstPrinter(MAI, MII, MRI); return new BPFInstPrinter(MAI, MII, MRI);
return 0; return 0;
} }
extern "C" void LLVMInitializeBPFTargetMC() { extern "C" void LLVMInitializeBPFTargetMC() {
for (Target *T : {&TheBPFleTarget, &TheBPFbeTarget, &TheBPFTarget}) { for (Target *T :
{&getTheBPFleTarget(), &getTheBPFbeTarget(), &getTheBPFTarget()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfo<BPFMCAsmInfo> X(*T); RegisterMCAsmInfo<BPFMCAsmInfo> X(*T);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createBPFMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createBPFMCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(*T, createBPFMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(*T, createBPFMCRegisterInfo);
// Register the MC subtarget info. // Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(*T, TargetRegistry::RegisterMCSubtargetInfo(*T,
createBPFMCSubtargetInfo); createBPFMCSubtargetInfo);
// Register the object streamer // Register the object streamer
TargetRegistry::RegisterELFStreamer(*T, createBPFMCStreamer); TargetRegistry::RegisterELFStreamer(*T, createBPFMCStreamer);
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(*T, createBPFMCInstPrinter); TargetRegistry::RegisterMCInstPrinter(*T, createBPFMCInstPrinter);
} }
// Register the MC code emitter // Register the MC code emitter
TargetRegistry::RegisterMCCodeEmitter(TheBPFleTarget, createBPFMCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(getTheBPFleTarget(),
TargetRegistry::RegisterMCCodeEmitter(TheBPFbeTarget, createBPFbeMCCodeEmitter); createBPFMCCodeEmitter);
TargetRegistry::RegisterMCCodeEmitter(getTheBPFbeTarget(),
createBPFbeMCCodeEmitter);
// Register the ASM Backend // Register the ASM Backend
TargetRegistry::RegisterMCAsmBackend(TheBPFleTarget, createBPFAsmBackend); TargetRegistry::RegisterMCAsmBackend(getTheBPFleTarget(),
TargetRegistry::RegisterMCAsmBackend(TheBPFbeTarget, createBPFbeAsmBackend); createBPFAsmBackend);
TargetRegistry::RegisterMCAsmBackend(getTheBPFbeTarget(),
createBPFbeAsmBackend);
if (sys::IsLittleEndianHost) { if (sys::IsLittleEndianHost) {
TargetRegistry::RegisterMCCodeEmitter(TheBPFTarget, createBPFMCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(getTheBPFTarget(),
TargetRegistry::RegisterMCAsmBackend(TheBPFTarget, createBPFAsmBackend); createBPFMCCodeEmitter);
TargetRegistry::RegisterMCAsmBackend(getTheBPFTarget(),
createBPFAsmBackend);
} else { } else {
TargetRegistry::RegisterMCCodeEmitter(TheBPFTarget, createBPFbeMCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(getTheBPFTarget(),
TargetRegistry::RegisterMCAsmBackend(TheBPFTarget, createBPFbeAsmBackend); createBPFbeMCCodeEmitter);
TargetRegistry::RegisterMCAsmBackend(getTheBPFTarget(),
createBPFbeAsmBackend);
} }
} }

lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp

//===-- BPFTargetInfo.cpp - BPF Target Implementation ---------------------===// //===-- BPFTargetInfo.cpp - BPF Target Implementation ---------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "BPF.h" #include "BPF.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
namespace llvm { namespace llvm {
Target TheBPFleTarget; Target &getTheBPFleTarget() {
Target TheBPFbeTarget; static Target TheBPFleTarget;
Target TheBPFTarget; return TheBPFleTarget;
} }
Target &getTheBPFbeTarget() {
static Target TheBPFbeTarget;
return TheBPFbeTarget;
}
Target &getTheBPFTarget() {
static Target TheBPFTarget;
return TheBPFTarget;
}
} // namespace llvm
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// namespace llvm?

jlebar: `// namespace llvm`?
extern "C" void LLVMInitializeBPFTargetInfo() { extern "C" void LLVMInitializeBPFTargetInfo() {
TargetRegistry::RegisterTarget(TheBPFTarget, "bpf", TargetRegistry::RegisterTarget(getTheBPFTarget(), "bpf", "BPF (host endian)",
"BPF (host endian)",
[](Triple::ArchType) { return false; }, true); [](Triple::ArchType) { return false; }, true);
RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X( RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X(getTheBPFleTarget(), "bpfel",
TheBPFleTarget, "bpfel", "BPF (little endian)"); "BPF (little endian)");
RegisterTarget<Triple::bpfeb, /*HasJIT=*/true> Y( RegisterTarget<Triple::bpfeb, /*HasJIT=*/true> Y(getTheBPFbeTarget(), "bpfeb",
TheBPFbeTarget, "bpfeb", "BPF (big endian)"); "BPF (big endian)");
} }

lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

Show First 20 Lines • Show All 1,059 Lines • ▼ Show 20 Lines
bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const { bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
return true; return true;
} }
// extern "C" void LLVMInitializeHexagonAsmLexer(); // extern "C" void LLVMInitializeHexagonAsmLexer();
/// Force static initialization. /// Force static initialization.
extern "C" void LLVMInitializeHexagonAsmParser() { extern "C" void LLVMInitializeHexagonAsmParser() {
RegisterMCAsmParser<HexagonAsmParser> X(TheHexagonTarget); RegisterMCAsmParser<HexagonAsmParser> X(getTheHexagonTarget());
} }
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#include "HexagonGenAsmMatcher.inc" #include "HexagonGenAsmMatcher.inc"
namespace { namespace {
bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) { bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) {
▲ Show 20 Lines • Show All 1,091 Lines • Show Last 20 Lines

lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
static MCDisassembler *createHexagonDisassembler(const Target &T, static MCDisassembler *createHexagonDisassembler(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
} }
extern "C" void LLVMInitializeHexagonDisassembler() { extern "C" void LLVMInitializeHexagonDisassembler() {
TargetRegistry::RegisterMCDisassembler(TheHexagonTarget, TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(),
createHexagonDisassembler); createHexagonDisassembler);
} }
DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes, ArrayRef<uint8_t> Bytes,
uint64_t Address, uint64_t Address,
raw_ostream &os, raw_ostream &os,
raw_ostream &cs) const { raw_ostream &cs) const {
▲ Show 20 Lines • Show All 1,451 Lines • Show Last 20 Lines

lib/Target/Hexagon/HexagonAsmPrinter.cpp

Show First 20 Lines • Show All 594 Lines • ▼ Show 20 Linesvoid HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
assert(Ok); assert(Ok);
(void)Ok; (void)Ok;
if(HexagonMCInstrInfo::bundleSize(MCB) == 0) if(HexagonMCInstrInfo::bundleSize(MCB) == 0)
return; return;
OutStreamer->EmitInstruction(MCB, getSubtargetInfo()); OutStreamer->EmitInstruction(MCB, getSubtargetInfo());
} }
extern "C" void LLVMInitializeHexagonAsmPrinter() { extern "C" void LLVMInitializeHexagonAsmPrinter() {
RegisterAsmPrinter<HexagonAsmPrinter> X(TheHexagonTarget); RegisterAsmPrinter<HexagonAsmPrinter> X(getTheHexagonTarget());
} }

lib/Target/Hexagon/HexagonTargetMachine.cpp

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
/// library. In particular, it seems that it is not possible to get /// library. In particular, it seems that it is not possible to get
/// things to work on Win32 without this. Though it is unused, do not /// things to work on Win32 without this. Though it is unused, do not
/// remove it. /// remove it.
extern "C" int HexagonTargetMachineModule; extern "C" int HexagonTargetMachineModule;
int HexagonTargetMachineModule = 0; int HexagonTargetMachineModule = 0;
extern "C" void LLVMInitializeHexagonTarget() { extern "C" void LLVMInitializeHexagonTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget); RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
} }
static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) { static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>()); return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
} }
static MachineSchedRegistry static MachineSchedRegistry
SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
▲ Show 20 Lines • Show All 234 Lines • Show Last 20 Lines

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h

Show All 29 Lines
class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
class Triple; class Triple;
class StringRef; class StringRef;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheHexagonTarget; Target &getTheHexagonTarget();
extern cl::opt<bool> HexagonDisableCompound; extern cl::opt<bool> HexagonDisableCompound;
extern cl::opt<bool> HexagonDisableDuplex; extern cl::opt<bool> HexagonDisableDuplex;
extern const InstrStage HexagonStages[]; extern const InstrStage HexagonStages[];
MCInstrInfo *createHexagonMCInstrInfo(); MCInstrInfo *createHexagonMCInstrInfo();
MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
Show All 31 Lines

lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

Show First 20 Lines • Show All 224 Lines • ▼ Show 20 Lines
static MCTargetStreamer * static MCTargetStreamer *
createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) { createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) {
return new HexagonTargetELFStreamer(S, STI); return new HexagonTargetELFStreamer(S, STI);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeHexagonTargetMC() { extern "C" void LLVMInitializeHexagonTargetMC() {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo); RegisterMCAsmInfoFn X(getTheHexagonTarget(), createHexagonMCAsmInfo);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget, TargetRegistry::RegisterMCInstrInfo(getTheHexagonTarget(),
createHexagonMCInstrInfo); createHexagonMCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(TheHexagonTarget, TargetRegistry::RegisterMCRegInfo(getTheHexagonTarget(),
createHexagonMCRegisterInfo); createHexagonMCRegisterInfo);
// Register the MC subtarget info. // Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget, TargetRegistry::RegisterMCSubtargetInfo(getTheHexagonTarget(),
createHexagonMCSubtargetInfo); createHexagonMCSubtargetInfo);
// Register the MC Code Emitter // Register the MC Code Emitter
TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget, TargetRegistry::RegisterMCCodeEmitter(getTheHexagonTarget(),
createHexagonMCCodeEmitter); createHexagonMCCodeEmitter);
// Register the asm backend // Register the asm backend
TargetRegistry::RegisterMCAsmBackend(TheHexagonTarget, TargetRegistry::RegisterMCAsmBackend(getTheHexagonTarget(),
createHexagonAsmBackend); createHexagonAsmBackend);
// Register the obj streamer // Register the obj streamer
TargetRegistry::RegisterELFStreamer(TheHexagonTarget, createMCStreamer); TargetRegistry::RegisterELFStreamer(getTheHexagonTarget(), createMCStreamer);
// Register the asm streamer // Register the asm streamer
TargetRegistry::RegisterAsmTargetStreamer(TheHexagonTarget, TargetRegistry::RegisterAsmTargetStreamer(getTheHexagonTarget(),
createMCAsmTargetStreamer); createMCAsmTargetStreamer);
// Register the MC Inst Printer // Register the MC Inst Printer
TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget, TargetRegistry::RegisterMCInstPrinter(getTheHexagonTarget(),
createHexagonMCInstPrinter); createHexagonMCInstPrinter);
TargetRegistry::RegisterObjectTargetStreamer( TargetRegistry::RegisterObjectTargetStreamer(
TheHexagonTarget, createHexagonObjectTargetStreamer); getTheHexagonTarget(), createHexagonObjectTargetStreamer);
} }

lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp

//===-- HexagonTargetInfo.cpp - Hexagon Target Implementation ------------------===// //===-- HexagonTargetInfo.cpp - Hexagon Target Implementation ------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "Hexagon.h" #include "Hexagon.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::TheHexagonTarget; Target &llvm::getTheHexagonTarget() {
static Target TheHexagonTarget;
return TheHexagonTarget;
}
extern "C" void LLVMInitializeHexagonTargetInfo() { extern "C" void LLVMInitializeHexagonTargetInfo() {
RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(TheHexagonTarget, "hexagon", "Hexagon"); RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(getTheHexagonTarget(),
"hexagon", "Hexagon");
} }

lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp

Show First 20 Lines • Show All 1,201 Lines • ▼ Show 20 Lines
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#include "LanaiGenAsmMatcher.inc" #include "LanaiGenAsmMatcher.inc"
} // namespace } // namespace
extern "C" void LLVMInitializeLanaiAsmParser() { extern "C" void LLVMInitializeLanaiAsmParser() {
RegisterMCAsmParser<LanaiAsmParser> x(TheLanaiTarget); RegisterMCAsmParser<LanaiAsmParser> x(getTheLanaiTarget());
} }
} // namespace llvm } // namespace llvm

lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp

Show All 21 Lines
#include "llvm/Support/MemoryObject.h" #include "llvm/Support/MemoryObject.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
typedef MCDisassembler::DecodeStatus DecodeStatus; typedef MCDisassembler::DecodeStatus DecodeStatus;
namespace llvm { namespace llvm {
extern Target TheLanaiTarget; Target &getTheLanaiTarget();
} }
static MCDisassembler *createLanaiDisassembler(const Target & /*T*/, static MCDisassembler *createLanaiDisassembler(const Target & /*T*/,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new LanaiDisassembler(STI, Ctx); return new LanaiDisassembler(STI, Ctx);
} }
extern "C" void LLVMInitializeLanaiDisassembler() { extern "C" void LLVMInitializeLanaiDisassembler() {
// Register the disassembler // Register the disassembler
TargetRegistry::RegisterMCDisassembler(TheLanaiTarget, TargetRegistry::RegisterMCDisassembler(getTheLanaiTarget(),
createLanaiDisassembler); createLanaiDisassembler);
} }
LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
: MCDisassembler(STI, Ctx) {} : MCDisassembler(STI, Ctx) {}
// Forward declare because the autogenerated code will reference this. // Forward declare because the autogenerated code will reference this.
// Definition is further down. // Definition is further down.
▲ Show 20 Lines • Show All 191 Lines • Show Last 20 Lines

lib/Target/Lanai/Lanai.h

Show All 39 Lines
// createLanaiMemAluCombinerPass - This pass combines loads/stores and // createLanaiMemAluCombinerPass - This pass combines loads/stores and
// arithmetic operations. // arithmetic operations.
FunctionPass *createLanaiMemAluCombinerPass(); FunctionPass *createLanaiMemAluCombinerPass();
// createLanaiSetflagAluCombinerPass - This pass combines SET_FLAG and ALU // createLanaiSetflagAluCombinerPass - This pass combines SET_FLAG and ALU
// operations. // operations.
FunctionPass *createLanaiSetflagAluCombinerPass(); FunctionPass *createLanaiSetflagAluCombinerPass();
extern Target TheLanaiTarget; Target &getTheLanaiTarget();
} // namespace llvm } // namespace llvm
#endif // LLVM_LIB_TARGET_LANAI_LANAI_H #endif // LLVM_LIB_TARGET_LANAI_LANAI_H

lib/Target/Lanai/LanaiAsmPrinter.cpp

Show First 20 Lines • Show All 233 Lines • ▼ Show 20 Linesbool LanaiAsmPrinter::isBlockOnlyReachableByFallthrough(
while (I != Pred->begin() && !(--I)->isTerminator()) { while (I != Pred->begin() && !(--I)->isTerminator()) {
} }
return !I->isBarrier(); return !I->isBarrier();
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeLanaiAsmPrinter() { extern "C" void LLVMInitializeLanaiAsmPrinter() {
RegisterAsmPrinter<LanaiAsmPrinter> X(TheLanaiTarget); RegisterAsmPrinter<LanaiAsmPrinter> X(getTheLanaiTarget());
} }

lib/Target/Lanai/LanaiTargetMachine.cpp

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using namespace llvm; using namespace llvm;
namespace llvm { namespace llvm {
void initializeLanaiMemAluCombinerPass(PassRegistry &); void initializeLanaiMemAluCombinerPass(PassRegistry &);
} // namespace llvm } // namespace llvm
extern "C" void LLVMInitializeLanaiTarget() { extern "C" void LLVMInitializeLanaiTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<LanaiTargetMachine> registered_target(TheLanaiTarget); RegisterTargetMachine<LanaiTargetMachine> registered_target(
getTheLanaiTarget());
} }
static std::string computeDataLayout() { static std::string computeDataLayout() {
// Data layout (keep in sync with clang/lib/Basic/Targets.cpp) // Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
return "E" // Big endian return "E" // Big endian
"-m:e" // ELF name manging "-m:e" // ELF name manging
"-p:32:32" // 32-bit pointers, 32 bit aligned "-p:32:32" // 32-bit pointers, 32 bit aligned
"-i64:64" // 64 bit integers, 64 bit aligned "-i64:64" // 64 bit integers, 64 bit aligned
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lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h

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class MCObjectWriter; class MCObjectWriter;
class MCRelocationInfo; class MCRelocationInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
class Triple; class Triple;
class StringRef; class StringRef;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheLanaiTarget; Target &getTheLanaiTarget();
MCCodeEmitter *createLanaiMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createLanaiMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TheTriple, StringRef CPU, const Triple &TheTriple, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
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lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
}; };
static MCInstrAnalysis *createLanaiInstrAnalysis(const MCInstrInfo *Info) { static MCInstrAnalysis *createLanaiInstrAnalysis(const MCInstrInfo *Info) {
return new LanaiMCInstrAnalysis(Info); return new LanaiMCInstrAnalysis(Info);
} }
extern "C" void LLVMInitializeLanaiTargetMC() { extern "C" void LLVMInitializeLanaiTargetMC() {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfo<LanaiMCAsmInfo> X(TheLanaiTarget); RegisterMCAsmInfo<LanaiMCAsmInfo> X(getTheLanaiTarget());
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheLanaiTarget, createLanaiMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(getTheLanaiTarget(),
createLanaiMCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(TheLanaiTarget, createLanaiMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(getTheLanaiTarget(),
createLanaiMCRegisterInfo);
// Register the MC subtarget info. // Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheLanaiTarget, TargetRegistry::RegisterMCSubtargetInfo(getTheLanaiTarget(),
createLanaiMCSubtargetInfo); createLanaiMCSubtargetInfo);
// Register the MC code emitter // Register the MC code emitter
TargetRegistry::RegisterMCCodeEmitter(TheLanaiTarget, TargetRegistry::RegisterMCCodeEmitter(getTheLanaiTarget(),
llvm::createLanaiMCCodeEmitter); llvm::createLanaiMCCodeEmitter);
// Register the ASM Backend // Register the ASM Backend
TargetRegistry::RegisterMCAsmBackend(TheLanaiTarget, createLanaiAsmBackend); TargetRegistry::RegisterMCAsmBackend(getTheLanaiTarget(),
createLanaiAsmBackend);
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(TheLanaiTarget, TargetRegistry::RegisterMCInstPrinter(getTheLanaiTarget(),
createLanaiMCInstPrinter); createLanaiMCInstPrinter);
// Register the ELF streamer. // Register the ELF streamer.
TargetRegistry::RegisterELFStreamer(TheLanaiTarget, createMCStreamer); TargetRegistry::RegisterELFStreamer(getTheLanaiTarget(), createMCStreamer);
// Register the MC relocation info. // Register the MC relocation info.
TargetRegistry::RegisterMCRelocationInfo(TheLanaiTarget, TargetRegistry::RegisterMCRelocationInfo(getTheLanaiTarget(),
createLanaiElfRelocation); createLanaiElfRelocation);
// Register the MC instruction analyzer. // Register the MC instruction analyzer.
TargetRegistry::RegisterMCInstrAnalysis(TheLanaiTarget, TargetRegistry::RegisterMCInstrAnalysis(getTheLanaiTarget(),
createLanaiInstrAnalysis); createLanaiInstrAnalysis);
} }

lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp

//===-- LanaiTargetInfo.cpp - Lanai Target Implementation -----------------===// //===-- LanaiTargetInfo.cpp - Lanai Target Implementation -----------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "Lanai.h" #include "Lanai.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::TheLanaiTarget; namespace llvm {
Target &getTheLanaiTarget() {
static Target TheLanaiTarget;
return TheLanaiTarget;
}
} // namespace llvm
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extern "C" void LLVMInitializeLanaiTargetInfo() { extern "C" void LLVMInitializeLanaiTargetInfo() {
RegisterTarget<Triple::lanai> X(TheLanaiTarget, "lanai", "Lanai"); RegisterTarget<Triple::lanai> X(getTheLanaiTarget(), "lanai", "Lanai");
} }

lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h

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#ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H #ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H
#define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H #define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H
#include "llvm/Support/DataTypes.h" #include "llvm/Support/DataTypes.h"
namespace llvm { namespace llvm {
class Target; class Target;
extern Target TheMSP430Target; Target &getTheMSP430Target();
} // End llvm namespace } // End llvm namespace
// Defines symbolic names for MSP430 registers. // Defines symbolic names for MSP430 registers.
// This defines a mapping from register name to register number. // This defines a mapping from register name to register number.
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
#include "MSP430GenRegisterInfo.inc" #include "MSP430GenRegisterInfo.inc"
// Defines symbolic names for the MSP430 instructions. // Defines symbolic names for the MSP430 instructions.
#define GET_INSTRINFO_ENUM #define GET_INSTRINFO_ENUM
#include "MSP430GenInstrInfo.inc" #include "MSP430GenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_ENUM
#include "MSP430GenSubtargetInfo.inc" #include "MSP430GenSubtargetInfo.inc"
#endif #endif

lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Linesstatic MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new MSP430InstPrinter(MAI, MII, MRI); return new MSP430InstPrinter(MAI, MII, MRI);
return nullptr; return nullptr;
} }
extern "C" void LLVMInitializeMSP430TargetMC() { extern "C" void LLVMInitializeMSP430TargetMC() {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target); RegisterMCAsmInfo<MSP430MCAsmInfo> X(getTheMSP430Target());
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo); TargetRegistry::RegisterMCInstrInfo(getTheMSP430Target(),
createMSP430MCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(TheMSP430Target, TargetRegistry::RegisterMCRegInfo(getTheMSP430Target(),
createMSP430MCRegisterInfo); createMSP430MCRegisterInfo);
// Register the MC subtarget info. // Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target, TargetRegistry::RegisterMCSubtargetInfo(getTheMSP430Target(),
createMSP430MCSubtargetInfo); createMSP430MCSubtargetInfo);
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(TheMSP430Target, TargetRegistry::RegisterMCInstPrinter(getTheMSP430Target(),
createMSP430MCInstPrinter); createMSP430MCInstPrinter);
} }

lib/Target/MSP430/MSP430AsmPrinter.cpp

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Linesvoid MSP430AsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst TmpInst; MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst); MCInstLowering.Lower(MI, TmpInst);
EmitToStreamer(*OutStreamer, TmpInst); EmitToStreamer(*OutStreamer, TmpInst);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeMSP430AsmPrinter() { extern "C" void LLVMInitializeMSP430AsmPrinter() {
RegisterAsmPrinter<MSP430AsmPrinter> X(TheMSP430Target); RegisterAsmPrinter<MSP430AsmPrinter> X(getTheMSP430Target());
} }

lib/Target/MSP430/MSP430TargetMachine.cpp

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#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/LegacyPassManager.h"
#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
extern "C" void LLVMInitializeMSP430Target() { extern "C" void LLVMInitializeMSP430Target() {
// Register the target. // Register the target.
RegisterTargetMachine<MSP430TargetMachine> X(TheMSP430Target); RegisterTargetMachine<MSP430TargetMachine> X(getTheMSP430Target());
} }
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
if (!RM.hasValue()) if (!RM.hasValue())
return Reloc::Static; return Reloc::Static;
return *RM; return *RM;
} }
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lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp

//===-- MSP430TargetInfo.cpp - MSP430 Target Implementation ---------------===// //===-- MSP430TargetInfo.cpp - MSP430 Target Implementation ---------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MSP430.h" #include "MSP430.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::TheMSP430Target; Target &llvm::getTheMSP430Target() {
static Target TheMSP430Target;
return TheMSP430Target;
}
extern "C" void LLVMInitializeMSP430TargetInfo() { extern "C" void LLVMInitializeMSP430TargetInfo() {
RegisterTarget<Triple::msp430> RegisterTarget<Triple::msp430> X(getTheMSP430Target(), "msp430",
X(TheMSP430Target, "msp430", "MSP430 [experimental]"); "MSP430 [experimental]");
} }

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 6,463 Lines • ▼ Show 20 Linesbool MipsAsmParser::parseInternalDirectiveReallowModule() {
getTargetStreamer().reallowModuleDirective(); getTargetStreamer().reallowModuleDirective();
getParser().Lex(); // Eat EndOfStatement token. getParser().Lex(); // Eat EndOfStatement token.
return false; return false;
} }
extern "C" void LLVMInitializeMipsAsmParser() { extern "C" void LLVMInitializeMipsAsmParser() {
RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget); RegisterMCAsmParser<MipsAsmParser> X(getTheMipsTarget());
RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget); RegisterMCAsmParser<MipsAsmParser> Y(getTheMipselTarget());
RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target); RegisterMCAsmParser<MipsAsmParser> A(getTheMips64Target());
RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget); RegisterMCAsmParser<MipsAsmParser> B(getTheMips64elTarget());
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#include "MipsGenAsmMatcher.inc" #include "MipsGenAsmMatcher.inc"

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Show First 20 Lines • Show All 513 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
namespace llvm { namespace llvm {
extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, Target &getTheMipselTarget();
TheMips64elTarget; Target &getTheMipsTarget();
Target &getTheMips64Target();
Target &getTheMips64elTarget();
} }
static MCDisassembler *createMipsDisassembler( static MCDisassembler *createMipsDisassembler(
const Target &T, const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new MipsDisassembler(STI, Ctx, true); return new MipsDisassembler(STI, Ctx, true);
} }
static MCDisassembler *createMipselDisassembler( static MCDisassembler *createMipselDisassembler(
const Target &T, const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new MipsDisassembler(STI, Ctx, false); return new MipsDisassembler(STI, Ctx, false);
} }
extern "C" void LLVMInitializeMipsDisassembler() { extern "C" void LLVMInitializeMipsDisassembler() {
// Register the disassembler. // Register the disassembler.
TargetRegistry::RegisterMCDisassembler(TheMipsTarget, TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(),
createMipsDisassembler); createMipsDisassembler);
TargetRegistry::RegisterMCDisassembler(TheMipselTarget, TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(),
createMipselDisassembler); createMipselDisassembler);
TargetRegistry::RegisterMCDisassembler(TheMips64Target, TargetRegistry::RegisterMCDisassembler(getTheMips64Target(),
createMipsDisassembler); createMipsDisassembler);
TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(),
createMipselDisassembler); createMipselDisassembler);
} }
#include "MipsGenDisassemblerTables.inc" #include "MipsGenDisassemblerTables.inc"
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
▲ Show 20 Lines • Show All 1,939 Lines • Show Last 20 Lines

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

Show All 25 Lines
class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class StringRef; class StringRef;
class Target; class Target;
class Triple; class Triple;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheMipsTarget; Target &getTheMipsTarget();
extern Target TheMipselTarget; Target &getTheMipselTarget();
extern Target TheMips64Target; Target &getTheMips64Target();
extern Target TheMips64elTarget; Target &getTheMips64elTarget();
MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
Show All 39 Lines

lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
}; };
} }
static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) { static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
return new MipsMCInstrAnalysis(Info); return new MipsMCInstrAnalysis(Info);
} }
extern "C" void LLVMInitializeMipsTargetMC() { extern "C" void LLVMInitializeMipsTargetMC() {
for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target, for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
&TheMips64elTarget}) { &getTheMips64Target(), &getTheMips64elTarget()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
Show All 16 Lines for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter); TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
TargetRegistry::RegisterObjectTargetStreamer( TargetRegistry::RegisterObjectTargetStreamer(
*T, createMipsObjectTargetStreamer); *T, createMipsObjectTargetStreamer);
} }
// Register the MC Code Emitter // Register the MC Code Emitter
for (Target *T : {&TheMipsTarget, &TheMips64Target}) for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB); TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
for (Target *T : {&TheMipselTarget, &TheMips64elTarget}) for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
// Register the asm backend. // Register the asm backend.
TargetRegistry::RegisterMCAsmBackend(TheMipsTarget, TargetRegistry::RegisterMCAsmBackend(getTheMipsTarget(),
createMipsAsmBackendEB32); createMipsAsmBackendEB32);
TargetRegistry::RegisterMCAsmBackend(TheMipselTarget, TargetRegistry::RegisterMCAsmBackend(getTheMipselTarget(),
createMipsAsmBackendEL32); createMipsAsmBackendEL32);
TargetRegistry::RegisterMCAsmBackend(TheMips64Target, TargetRegistry::RegisterMCAsmBackend(getTheMips64Target(),
createMipsAsmBackendEB64); createMipsAsmBackendEB64);
TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget, TargetRegistry::RegisterMCAsmBackend(getTheMips64elTarget(),
createMipsAsmBackendEL64); createMipsAsmBackendEL64);
} }

lib/Target/Mips/MipsAsmPrinter.cpp

Show First 20 Lines • Show All 1,060 Lines • ▼ Show 20 Lines
bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const { bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
return (Opcode == Mips::LONG_BRANCH_LUi return (Opcode == Mips::LONG_BRANCH_LUi
|| Opcode == Mips::LONG_BRANCH_ADDiu || Opcode == Mips::LONG_BRANCH_ADDiu
|| Opcode == Mips::LONG_BRANCH_DADDiu); || Opcode == Mips::LONG_BRANCH_DADDiu);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeMipsAsmPrinter() { extern "C" void LLVMInitializeMipsAsmPrinter() {
RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget); RegisterAsmPrinter<MipsAsmPrinter> X(getTheMipsTarget());
RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget); RegisterAsmPrinter<MipsAsmPrinter> Y(getTheMipselTarget());
RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target); RegisterAsmPrinter<MipsAsmPrinter> A(getTheMips64Target());
RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget); RegisterAsmPrinter<MipsAsmPrinter> B(getTheMips64elTarget());
} }

lib/Target/Mips/MipsTargetMachine.cpp

Show All 33 Lines
#include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "mips" #define DEBUG_TYPE "mips"
extern "C" void LLVMInitializeMipsTarget() { extern "C" void LLVMInitializeMipsTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget); RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget); RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target); RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget); RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget());
} }
static std::string computeDataLayout(const Triple &TT, StringRef CPU, static std::string computeDataLayout(const Triple &TT, StringRef CPU,
const TargetOptions &Options, const TargetOptions &Options,
bool isLittle) { bool isLittle) {
std::string Ret = ""; std::string Ret = "";
MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
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lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp

//===-- MipsTargetInfo.cpp - Mips Target Implementation -------------------===// //===-- MipsTargetInfo.cpp - Mips Target Implementation -------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "Mips.h" #include "Mips.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::TheMipsTarget, llvm::TheMipselTarget; Target &llvm::getTheMipsTarget() {
Target llvm::TheMips64Target, llvm::TheMips64elTarget; static Target TheMipsTarget;
return TheMipsTarget;
}
Target &llvm::getTheMipselTarget() {
static Target TheMipselTarget;
return TheMipselTarget;
}
Target &llvm::getTheMips64Target() {
static Target TheMips64Target;
return TheMips64Target;
}
Target &llvm::getTheMips64elTarget() {
static Target TheMips64elTarget;
return TheMips64elTarget;
}
extern "C" void LLVMInitializeMipsTargetInfo() { extern "C" void LLVMInitializeMipsTargetInfo() {
RegisterTarget<Triple::mips, RegisterTarget<Triple::mips,
/*HasJIT=*/true> X(TheMipsTarget, "mips", "Mips"); /*HasJIT=*/true>
X(getTheMipsTarget(), "mips", "Mips");
RegisterTarget<Triple::mipsel, RegisterTarget<Triple::mipsel,
/*HasJIT=*/true> Y(TheMipselTarget, "mipsel", "Mipsel"); /*HasJIT=*/true>
Y(getTheMipselTarget(), "mipsel", "Mipsel");
RegisterTarget<Triple::mips64, RegisterTarget<Triple::mips64,
/*HasJIT=*/true> A(TheMips64Target, "mips64", "Mips64 [experimental]"); /*HasJIT=*/true>
A(getTheMips64Target(), "mips64", "Mips64 [experimental]");
RegisterTarget<Triple::mips64el, RegisterTarget<Triple::mips64el,
/*HasJIT=*/true> B(TheMips64elTarget, /*HasJIT=*/true>
"mips64el", "Mips64el [experimental]"); B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]");
} }

lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h

Show All 13 Lines
#ifndef LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCTARGETDESC_H #ifndef LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCTARGETDESC_H
#define LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCTARGETDESC_H #define LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXMCTARGETDESC_H
#include <stdint.h> #include <stdint.h>
namespace llvm { namespace llvm {
class Target; class Target;
extern Target TheNVPTXTarget32; Target &getTheNVPTXTarget32();
extern Target TheNVPTXTarget64; Target &getTheNVPTXTarget64();
} // End llvm namespace } // End llvm namespace
// Defines symbolic names for PTX registers. // Defines symbolic names for PTX registers.
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
#include "NVPTXGenRegisterInfo.inc" #include "NVPTXGenRegisterInfo.inc"
// Defines symbolic names for the PTX instructions. // Defines symbolic names for the PTX instructions.
#define GET_INSTRINFO_ENUM #define GET_INSTRINFO_ENUM
#include "NVPTXGenInstrInfo.inc" #include "NVPTXGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_ENUM
#include "NVPTXGenSubtargetInfo.inc" #include "NVPTXGenSubtargetInfo.inc"
#endif #endif

lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Linesstatic MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new NVPTXInstPrinter(MAI, MII, MRI); return new NVPTXInstPrinter(MAI, MII, MRI);
return nullptr; return nullptr;
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeNVPTXTargetMC() { extern "C" void LLVMInitializeNVPTXTargetMC() {
for (Target *T : {&TheNVPTXTarget32, &TheNVPTXTarget64}) { for (Target *T : {&getTheNVPTXTarget32(), &getTheNVPTXTarget64()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfo<NVPTXMCAsmInfo> X(*T); RegisterMCAsmInfo<NVPTXMCAsmInfo> X(*T);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createNVPTXMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createNVPTXMCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(*T, createNVPTXMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(*T, createNVPTXMCRegisterInfo);
// Register the MC subtarget info. // Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(*T, createNVPTXMCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(*T, createNVPTXMCSubtargetInfo);
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(*T, createNVPTXMCInstPrinter); TargetRegistry::RegisterMCInstPrinter(*T, createNVPTXMCInstPrinter);
} }
} }

lib/Target/NVPTX/NVPTX.h

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FunctionPass *createNVVMReflectPass(const StringMap<int> &Mapping); FunctionPass *createNVVMReflectPass(const StringMap<int> &Mapping);
MachineFunctionPass *createNVPTXPrologEpilogPass(); MachineFunctionPass *createNVPTXPrologEpilogPass();
MachineFunctionPass *createNVPTXReplaceImageHandlesPass(); MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
FunctionPass *createNVPTXImageOptimizerPass(); FunctionPass *createNVPTXImageOptimizerPass();
FunctionPass *createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM); FunctionPass *createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM);
BasicBlockPass *createNVPTXLowerAllocaPass(); BasicBlockPass *createNVPTXLowerAllocaPass();
MachineFunctionPass *createNVPTXPeephole(); MachineFunctionPass *createNVPTXPeephole();
extern Target TheNVPTXTarget32; Target &getTheNVPTXTarget32();
extern Target TheNVPTXTarget64; Target &getTheNVPTXTarget64();
namespace NVPTX { namespace NVPTX {
enum DrvInterface { enum DrvInterface {
NVCL, NVCL,
CUDA CUDA
}; };
// A field inside TSFlags needs a shift and a mask. The usage is // A field inside TSFlags needs a shift and a mask. The usage is
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lib/Target/NVPTX/NVPTXAsmPrinter.cpp

Show First 20 Lines • Show All 2,374 Lines • ▼ Show 20 Lines while (theCurLine < lineNum) {
fstr.getline(buff, 500); fstr.getline(buff, 500);
theCurLine++; theCurLine++;
} }
return buff; return buff;
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeNVPTXAsmPrinter() { extern "C" void LLVMInitializeNVPTXAsmPrinter() {
RegisterAsmPrinter<NVPTXAsmPrinter> X(TheNVPTXTarget32); RegisterAsmPrinter<NVPTXAsmPrinter> X(getTheNVPTXTarget32());
RegisterAsmPrinter<NVPTXAsmPrinter> Y(TheNVPTXTarget64); RegisterAsmPrinter<NVPTXAsmPrinter> Y(getTheNVPTXTarget64());
} }

lib/Target/NVPTX/NVPTXTargetMachine.cpp

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
void initializeNVPTXInferAddressSpacesPass(PassRegistry &); void initializeNVPTXInferAddressSpacesPass(PassRegistry &);
void initializeNVPTXLowerAggrCopiesPass(PassRegistry &); void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
void initializeNVPTXLowerArgsPass(PassRegistry &); void initializeNVPTXLowerArgsPass(PassRegistry &);
void initializeNVPTXLowerAllocaPass(PassRegistry &); void initializeNVPTXLowerAllocaPass(PassRegistry &);
} }
extern "C" void LLVMInitializeNVPTXTarget() { extern "C" void LLVMInitializeNVPTXTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32); RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32());
RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64); RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64());
// FIXME: This pass is really intended to be invoked during IR optimization, // FIXME: This pass is really intended to be invoked during IR optimization,
// but it's very NVPTX-specific. // but it's very NVPTX-specific.
PassRegistry &PR = *PassRegistry::getPassRegistry(); PassRegistry &PR = *PassRegistry::getPassRegistry();
initializeNVVMReflectPass(PR); initializeNVVMReflectPass(PR);
initializeNVVMIntrRangePass(PR); initializeNVVMIntrRangePass(PR);
initializeGenericToNVVMPass(PR); initializeGenericToNVVMPass(PR);
initializeNVPTXAllocaHoistingPass(PR); initializeNVPTXAllocaHoistingPass(PR);
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lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp

//===-- NVPTXTargetInfo.cpp - NVPTX Target Implementation -----------------===// //===-- NVPTXTargetInfo.cpp - NVPTX Target Implementation -----------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "NVPTX.h" #include "NVPTX.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::TheNVPTXTarget32; Target &llvm::getTheNVPTXTarget32() {
Target llvm::TheNVPTXTarget64; static Target TheNVPTXTarget32;
return TheNVPTXTarget32;
}
Target &llvm::getTheNVPTXTarget64() {
static Target TheNVPTXTarget64;
return TheNVPTXTarget64;
}
extern "C" void LLVMInitializeNVPTXTargetInfo() { extern "C" void LLVMInitializeNVPTXTargetInfo() {
RegisterTarget<Triple::nvptx> X(TheNVPTXTarget32, "nvptx", RegisterTarget<Triple::nvptx> X(getTheNVPTXTarget32(), "nvptx",
"NVIDIA PTX 32-bit"); "NVIDIA PTX 32-bit");
RegisterTarget<Triple::nvptx64> Y(TheNVPTXTarget64, "nvptx64", RegisterTarget<Triple::nvptx64> Y(getTheNVPTXTarget64(), "nvptx64",
"NVIDIA PTX 64-bit"); "NVIDIA PTX 64-bit");
} }

lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

Show First 20 Lines • Show All 1,974 Lines • ▼ Show 20 Linesbool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
return false; return false;
} }
/// Force static initialization. /// Force static initialization.
extern "C" void LLVMInitializePowerPCAsmParser() { extern "C" void LLVMInitializePowerPCAsmParser() {
RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target); RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target());
RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target); RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target());
RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget); RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget());
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#include "PPCGenAsmMatcher.inc" #include "PPCGenAsmMatcher.inc"
// Define this matcher function after the auto-generated include so we // Define this matcher function after the auto-generated include so we
// have the match class enum definitions. // have the match class enum definitions.
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lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
static MCDisassembler *createPPCLEDisassembler(const Target &T, static MCDisassembler *createPPCLEDisassembler(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
} }
extern "C" void LLVMInitializePowerPCDisassembler() { extern "C" void LLVMInitializePowerPCDisassembler() {
// Register the disassembler for each target. // Register the disassembler for each target.
TargetRegistry::RegisterMCDisassembler(ThePPC32Target, TargetRegistry::RegisterMCDisassembler(getThePPC32Target(),
createPPCDisassembler); createPPCDisassembler);
TargetRegistry::RegisterMCDisassembler(ThePPC64Target, TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),
createPPCDisassembler); createPPCDisassembler);
TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget, TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),
createPPCLEDisassembler); createPPCLEDisassembler);
} }
// FIXME: These can be generated by TableGen from the existing register // FIXME: These can be generated by TableGen from the existing register
// encoding values! // encoding values!
static const unsigned CRRegs[] = { static const unsigned CRRegs[] = {
PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
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lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

Show All 29 Lines
class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
class Triple; class Triple;
class StringRef; class StringRef;
class raw_pwrite_stream; class raw_pwrite_stream;
class raw_ostream; class raw_ostream;
extern Target ThePPC32Target; Target &getThePPC32Target();
extern Target ThePPC64Target; Target &getThePPC64Target();
extern Target ThePPC64LETarget; Target &getThePPC64LETarget();
MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU, const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
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lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

Show First 20 Lines • Show All 222 Lines • ▼ Show 20 Linesstatic MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MRI) {
return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin()); return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin());
} }
extern "C" void LLVMInitializePowerPCTargetMC() { extern "C" void LLVMInitializePowerPCTargetMC() {
for (Target *T : {&ThePPC32Target, &ThePPC64Target, &ThePPC64LETarget}) { for (Target *T :
{&getThePPC32Target(), &getThePPC64Target(), &getThePPC64LETarget()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo); RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
// Register the MC codegen info. // Register the MC codegen info.
TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts); TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo);
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lib/Target/PowerPC/PPCAsmPrinter.cpp

Show First 20 Lines • Show All 1,441 Lines • ▼ Show 20 LinescreatePPCAsmPrinterPass(TargetMachine &tm,
std::unique_ptr<MCStreamer> &&Streamer) { std::unique_ptr<MCStreamer> &&Streamer) {
if (tm.getTargetTriple().isMacOSX()) if (tm.getTargetTriple().isMacOSX())
return new PPCDarwinAsmPrinter(tm, std::move(Streamer)); return new PPCDarwinAsmPrinter(tm, std::move(Streamer));
return new PPCLinuxAsmPrinter(tm, std::move(Streamer)); return new PPCLinuxAsmPrinter(tm, std::move(Streamer));
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializePowerPCAsmPrinter() { extern "C" void LLVMInitializePowerPCAsmPrinter() {
TargetRegistry::RegisterAsmPrinter(ThePPC32Target, createPPCAsmPrinterPass); TargetRegistry::RegisterAsmPrinter(getThePPC32Target(),
TargetRegistry::RegisterAsmPrinter(ThePPC64Target, createPPCAsmPrinterPass); createPPCAsmPrinterPass);
TargetRegistry::RegisterAsmPrinter(ThePPC64LETarget, createPPCAsmPrinterPass); TargetRegistry::RegisterAsmPrinter(getThePPC64Target(),
createPPCAsmPrinterPass);
TargetRegistry::RegisterAsmPrinter(getThePPC64LETarget(),
createPPCAsmPrinterPass);
} }

lib/Target/PowerPC/PPCTargetMachine.cpp

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
static cl::opt<bool> static cl::opt<bool>
EnableMachineCombinerPass("ppc-machine-combiner", EnableMachineCombinerPass("ppc-machine-combiner",
cl::desc("Enable the machine combiner pass"), cl::desc("Enable the machine combiner pass"),
cl::init(true), cl::Hidden); cl::init(true), cl::Hidden);
extern "C" void LLVMInitializePowerPCTarget() { extern "C" void LLVMInitializePowerPCTarget() {
// Register the targets // Register the targets
RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target); RegisterTargetMachine<PPC32TargetMachine> A(getThePPC32Target());
RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target); RegisterTargetMachine<PPC64TargetMachine> B(getThePPC64Target());
RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget); RegisterTargetMachine<PPC64TargetMachine> C(getThePPC64LETarget());
PassRegistry &PR = *PassRegistry::getPassRegistry(); PassRegistry &PR = *PassRegistry::getPassRegistry();
initializePPCBoolRetToIntPass(PR); initializePPCBoolRetToIntPass(PR);
} }
/// Return the datalayout string of a subtarget. /// Return the datalayout string of a subtarget.
static std::string getDataLayoutString(const Triple &T) { static std::string getDataLayoutString(const Triple &T) {
bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le; bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
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lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp

//===-- PowerPCTargetInfo.cpp - PowerPC Target Implementation -------------===// //===-- PowerPCTargetInfo.cpp - PowerPC Target Implementation -------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "PPC.h" #include "PPC.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::ThePPC32Target, llvm::ThePPC64Target, llvm::ThePPC64LETarget; Target &llvm::getThePPC32Target() {
static Target ThePPC32Target;
return ThePPC32Target;
}
Target &llvm::getThePPC64Target() {
static Target ThePPC64Target;
return ThePPC64Target;
}
Target &llvm::getThePPC64LETarget() {
static Target ThePPC64LETarget;
return ThePPC64LETarget;
}
extern "C" void LLVMInitializePowerPCTargetInfo() { extern "C" void LLVMInitializePowerPCTargetInfo() {
RegisterTarget<Triple::ppc, /*HasJIT=*/true> RegisterTarget<Triple::ppc, /*HasJIT=*/true> X(getThePPC32Target(), "ppc32",
X(ThePPC32Target, "ppc32", "PowerPC 32"); "PowerPC 32");
RegisterTarget<Triple::ppc64, /*HasJIT=*/true> RegisterTarget<Triple::ppc64, /*HasJIT=*/true> Y(getThePPC64Target(), "ppc64",
Y(ThePPC64Target, "ppc64", "PowerPC 64"); "PowerPC 64");
RegisterTarget<Triple::ppc64le, /*HasJIT=*/true> RegisterTarget<Triple::ppc64le, /*HasJIT=*/true> Z(
Z(ThePPC64LETarget, "ppc64le", "PowerPC 64 LE"); getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE");
} }

lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

Show First 20 Lines • Show All 1,257 Lines • ▼ Show 20 Linesbool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
if (Parser.parseParenExpression(subExpr, EndLoc)) if (Parser.parseParenExpression(subExpr, EndLoc))
return false; return false;
EVal = adjustPICRelocation(VK, subExpr); EVal = adjustPICRelocation(VK, subExpr);
return true; return true;
} }
extern "C" void LLVMInitializeSparcAsmParser() { extern "C" void LLVMInitializeSparcAsmParser() {
RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget); RegisterMCAsmParser<SparcAsmParser> A(getTheSparcTarget());
RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target); RegisterMCAsmParser<SparcAsmParser> B(getTheSparcV9Target());
RegisterMCAsmParser<SparcAsmParser> C(TheSparcelTarget); RegisterMCAsmParser<SparcAsmParser> C(getTheSparcelTarget());
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#include "SparcGenAsmMatcher.inc" #include "SparcGenAsmMatcher.inc"
unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp, unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
unsigned Kind) { unsigned Kind) {
Show All 24 Lines

lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

Show All 38 Linespublic:
DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address, ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &VStream, raw_ostream &VStream,
raw_ostream &CStream) const override; raw_ostream &CStream) const override;
}; };
} }
namespace llvm { namespace llvm {
extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget; Target &getTheSparcTarget();
Target &getTheSparcV9Target();
Target &getTheSparcelTarget();
} }
static MCDisassembler *createSparcDisassembler(const Target &T, static MCDisassembler *createSparcDisassembler(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new SparcDisassembler(STI, Ctx); return new SparcDisassembler(STI, Ctx);
} }
extern "C" void LLVMInitializeSparcDisassembler() { extern "C" void LLVMInitializeSparcDisassembler() {
// Register the disassembler. // Register the disassembler.
TargetRegistry::RegisterMCDisassembler(TheSparcTarget, TargetRegistry::RegisterMCDisassembler(getTheSparcTarget(),
createSparcDisassembler); createSparcDisassembler);
TargetRegistry::RegisterMCDisassembler(TheSparcV9Target, TargetRegistry::RegisterMCDisassembler(getTheSparcV9Target(),
createSparcDisassembler); createSparcDisassembler);
TargetRegistry::RegisterMCDisassembler(TheSparcelTarget, TargetRegistry::RegisterMCDisassembler(getTheSparcelTarget(),
createSparcDisassembler); createSparcDisassembler);
} }
static const unsigned IntRegDecoderTable[] = { static const unsigned IntRegDecoderTable[] = {
SP::G0, SP::G1, SP::G2, SP::G3, SP::G0, SP::G1, SP::G2, SP::G3,
SP::G4, SP::G5, SP::G6, SP::G7, SP::G4, SP::G5, SP::G6, SP::G7,
SP::O0, SP::O1, SP::O2, SP::O3, SP::O0, SP::O1, SP::O2, SP::O3,
SP::O4, SP::O5, SP::O6, SP::O7, SP::O4, SP::O5, SP::O6, SP::O7,
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lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h

Show All 25 Lines
class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
class Triple; class Triple;
class StringRef; class StringRef;
class raw_pwrite_stream; class raw_pwrite_stream;
class raw_ostream; class raw_ostream;
extern Target TheSparcTarget; Target &getTheSparcTarget();
extern Target TheSparcV9Target; Target &getTheSparcV9Target();
extern Target TheSparcelTarget; Target &getTheSparcelTarget();
MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU, const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
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lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Linesstatic MCInstPrinter *createSparcMCInstPrinter(const Triple &T,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MRI) {
return new SparcInstPrinter(MAI, MII, MRI); return new SparcInstPrinter(MAI, MII, MRI);
} }
extern "C" void LLVMInitializeSparcTargetMC() { extern "C" void LLVMInitializeSparcTargetMC() {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo); RegisterMCAsmInfoFn X(getTheSparcTarget(), createSparcMCAsmInfo);
RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo); RegisterMCAsmInfoFn Y(getTheSparcV9Target(), createSparcV9MCAsmInfo);
RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo); RegisterMCAsmInfoFn Z(getTheSparcelTarget(), createSparcMCAsmInfo);
for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) { for (Target *T :
{&getTheSparcTarget(), &getTheSparcV9Target(), &getTheSparcelTarget()}) {
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo);
// Register the MC register info. // Register the MC register info.
TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo);
// Register the MC subtarget info. // Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo);
Show All 11 Lines for (Target *T :
// Register the asm streamer. // Register the asm streamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer); TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer);
// Register the MCInstPrinter // Register the MCInstPrinter
TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter); TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter);
} }
// Register the MC codegen info. // Register the MC codegen info.
TargetRegistry::registerMCAdjustCodeGenOpts(TheSparcTarget, TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcTarget(),
adjustCodeGenOpts); adjustCodeGenOpts);
TargetRegistry::registerMCAdjustCodeGenOpts(TheSparcV9Target, TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcV9Target(),
adjustCodeGenOptsV9); adjustCodeGenOptsV9);
TargetRegistry::registerMCAdjustCodeGenOpts(TheSparcelTarget, TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcelTarget(),
adjustCodeGenOpts); adjustCodeGenOpts);
} }

lib/Target/Sparc/SparcAsmPrinter.cpp

Show First 20 Lines • Show All 437 Lines • ▼ Show 20 Linesbool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
printMemOperand(MI, OpNo, O); printMemOperand(MI, OpNo, O);
O << ']'; O << ']';
return false; return false;
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeSparcAsmPrinter() { extern "C" void LLVMInitializeSparcAsmPrinter() {
RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget); RegisterAsmPrinter<SparcAsmPrinter> X(getTheSparcTarget());
RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target); RegisterAsmPrinter<SparcAsmPrinter> Y(getTheSparcV9Target());
RegisterAsmPrinter<SparcAsmPrinter> Z(TheSparcelTarget); RegisterAsmPrinter<SparcAsmPrinter> Z(getTheSparcelTarget());
} }

lib/Target/Sparc/SparcTargetMachine.cpp

Show All 16 Lines
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/LegacyPassManager.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
extern "C" void LLVMInitializeSparcTarget() { extern "C" void LLVMInitializeSparcTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
RegisterTargetMachine<SparcelTargetMachine> Z(TheSparcelTarget); RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
} }
static std::string computeDataLayout(const Triple &T, bool is64Bit) { static std::string computeDataLayout(const Triple &T, bool is64Bit) {
// Sparc is typically big endian, but some are little. // Sparc is typically big endian, but some are little.
std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E"; std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
Ret += "-m:e"; Ret += "-m:e";
// Some ABIs have 32bit pointers. // Some ABIs have 32bit pointers.
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lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp

//===-- SparcTargetInfo.cpp - Sparc Target Implementation -----------------===// //===-- SparcTargetInfo.cpp - Sparc Target Implementation -----------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "Sparc.h" #include "Sparc.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::TheSparcTarget; Target &llvm::getTheSparcTarget() {
Target llvm::TheSparcV9Target; static Target TheSparcTarget;
Target llvm::TheSparcelTarget; return TheSparcTarget;
}
Target &llvm::getTheSparcV9Target() {
static Target TheSparcV9Target;
return TheSparcV9Target;
}
Target &llvm::getTheSparcelTarget() {
static Target TheSparcelTarget;
return TheSparcelTarget;
}
extern "C" void LLVMInitializeSparcTargetInfo() { extern "C" void LLVMInitializeSparcTargetInfo() {
RegisterTarget<Triple::sparc, /*HasJIT=*/true> X(TheSparcTarget, "sparc", RegisterTarget<Triple::sparc, /*HasJIT=*/true> X(getTheSparcTarget(), "sparc",
"Sparc"); "Sparc");
RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(TheSparcV9Target, RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(getTheSparcV9Target(),
"sparcv9", "Sparc V9"); "sparcv9", "Sparc V9");
RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(TheSparcelTarget, RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(getTheSparcelTarget(),
"sparcel", "Sparc LE"); "sparcel", "Sparc LE");
} }

lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

Show First 20 Lines • Show All 1,165 Lines • ▼ Show 20 LinesSystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
else else
Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
return MatchOperand_Success; return MatchOperand_Success;
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeSystemZAsmParser() { extern "C" void LLVMInitializeSystemZAsmParser() {
RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget); RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
} }

lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp

Show All 36 Lines
static MCDisassembler *createSystemZDisassembler(const Target &T, static MCDisassembler *createSystemZDisassembler(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
return new SystemZDisassembler(STI, Ctx); return new SystemZDisassembler(STI, Ctx);
} }
extern "C" void LLVMInitializeSystemZDisassembler() { extern "C" void LLVMInitializeSystemZDisassembler() {
// Register the disassembler. // Register the disassembler.
TargetRegistry::RegisterMCDisassembler(TheSystemZTarget, TargetRegistry::RegisterMCDisassembler(getTheSystemZTarget(),
createSystemZDisassembler); createSystemZDisassembler);
} }
/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
/// immediate Value in the MCInst. /// immediate Value in the MCInst.
/// ///
/// @param Value - The immediate Value, has had any PC adjustment made by /// @param Value - The immediate Value, has had any PC adjustment made by
/// the caller. /// the caller.
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lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h

Show All 22 Lines
class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class StringRef; class StringRef;
class Target; class Target;
class Triple; class Triple;
class raw_pwrite_stream; class raw_pwrite_stream;
class raw_ostream; class raw_ostream;
extern Target TheSystemZTarget; Target &getTheSystemZTarget();
namespace SystemZMC { namespace SystemZMC {
// How many bytes are in the ABI-defined, caller-allocated part of // How many bytes are in the ABI-defined, caller-allocated part of
// a stack frame. // a stack frame.
const int64_t CallFrameSize = 160; const int64_t CallFrameSize = 160;
// The offset of the DWARF CFA from the incoming stack pointer. // The offset of the DWARF CFA from the incoming stack pointer.
const int64_t CFAOffsetFromInitialSP = CallFrameSize; const int64_t CFAOffsetFromInitialSP = CallFrameSize;
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lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Linesstatic MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MRI) {
return new SystemZInstPrinter(MAI, MII, MRI); return new SystemZInstPrinter(MAI, MII, MRI);
} }
extern "C" void LLVMInitializeSystemZTargetMC() { extern "C" void LLVMInitializeSystemZTargetMC() {
// Register the MCAsmInfo. // Register the MCAsmInfo.
TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget, TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(),
createSystemZMCAsmInfo); createSystemZMCAsmInfo);
// Register the adjustCodeGenOpts. // Register the adjustCodeGenOpts.
TargetRegistry::registerMCAdjustCodeGenOpts(TheSystemZTarget, TargetRegistry::registerMCAdjustCodeGenOpts(getTheSystemZTarget(),
adjustCodeGenOpts); adjustCodeGenOpts);
// Register the MCCodeEmitter. // Register the MCCodeEmitter.
TargetRegistry::RegisterMCCodeEmitter(TheSystemZTarget, TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(),
createSystemZMCCodeEmitter); createSystemZMCCodeEmitter);
// Register the MCInstrInfo. // Register the MCInstrInfo.
TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget, TargetRegistry::RegisterMCInstrInfo(getTheSystemZTarget(),
createSystemZMCInstrInfo); createSystemZMCInstrInfo);
// Register the MCRegisterInfo. // Register the MCRegisterInfo.
TargetRegistry::RegisterMCRegInfo(TheSystemZTarget, TargetRegistry::RegisterMCRegInfo(getTheSystemZTarget(),
createSystemZMCRegisterInfo); createSystemZMCRegisterInfo);
// Register the MCSubtargetInfo. // Register the MCSubtargetInfo.
TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget, TargetRegistry::RegisterMCSubtargetInfo(getTheSystemZTarget(),
createSystemZMCSubtargetInfo); createSystemZMCSubtargetInfo);
// Register the MCAsmBackend. // Register the MCAsmBackend.
TargetRegistry::RegisterMCAsmBackend(TheSystemZTarget, TargetRegistry::RegisterMCAsmBackend(getTheSystemZTarget(),
createSystemZMCAsmBackend); createSystemZMCAsmBackend);
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(TheSystemZTarget, TargetRegistry::RegisterMCInstPrinter(getTheSystemZTarget(),
createSystemZMCInstPrinter); createSystemZMCInstPrinter);
} }

lib/Target/SystemZ/SystemZAsmPrinter.cpp

Show First 20 Lines • Show All 517 Lines • ▼ Show 20 Linesbool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(), SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),
MI->getOperand(OpNo + 1).getImm(), MI->getOperand(OpNo + 1).getImm(),
MI->getOperand(OpNo + 2).getReg(), OS); MI->getOperand(OpNo + 2).getReg(), OS);
return false; return false;
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeSystemZAsmPrinter() { extern "C" void LLVMInitializeSystemZAsmPrinter() {
RegisterAsmPrinter<SystemZAsmPrinter> X(TheSystemZTarget); RegisterAsmPrinter<SystemZAsmPrinter> X(getTheSystemZTarget());
} }

lib/Target/SystemZ/SystemZTargetMachine.cpp

Show All 14 Lines
#include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
using namespace llvm; using namespace llvm;
extern cl::opt<bool> MISchedPostRA; extern cl::opt<bool> MISchedPostRA;
extern "C" void LLVMInitializeSystemZTarget() { extern "C" void LLVMInitializeSystemZTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<SystemZTargetMachine> X(TheSystemZTarget); RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget());
} }
// Determine whether we use the vector ABI. // Determine whether we use the vector ABI.
static bool UsesVectorABI(StringRef CPU, StringRef FS) { static bool UsesVectorABI(StringRef CPU, StringRef FS) {
// We use the vector ABI whenever the vector facility is avaiable. // We use the vector ABI whenever the vector facility is avaiable.
// This is the case by default if CPU is z13 or later, and can be // This is the case by default if CPU is z13 or later, and can be
// overridden via "[+-]vector" feature string elements. // overridden via "[+-]vector" feature string elements.
bool VectorABI = true; bool VectorABI = true;
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lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp

//===-- SystemZTargetInfo.cpp - SystemZ target implementation -------------===// //===-- SystemZTargetInfo.cpp - SystemZ target implementation -------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "SystemZ.h" #include "SystemZ.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::TheSystemZTarget; Target &llvm::getTheSystemZTarget() {
static Target TheSystemZTarget;
return TheSystemZTarget;
}
extern "C" void LLVMInitializeSystemZTargetInfo() { extern "C" void LLVMInitializeSystemZTargetInfo() {
RegisterTarget<Triple::systemz, /*HasJIT=*/true> RegisterTarget<Triple::systemz, /*HasJIT=*/true> X(getTheSystemZTarget(),
X(TheSystemZTarget, "systemz", "SystemZ"); "systemz", "SystemZ");
} }

lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesstatic MCDisassembler *createWebAssemblyDisassembler(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo()); std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo());
return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII)); return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII));
} }
extern "C" void LLVMInitializeWebAssemblyDisassembler() { extern "C" void LLVMInitializeWebAssemblyDisassembler() {
// Register the disassembler for each target. // Register the disassembler for each target.
TargetRegistry::RegisterMCDisassembler(TheWebAssemblyTarget32, TargetRegistry::RegisterMCDisassembler(getTheWebAssemblyTarget32(),
createWebAssemblyDisassembler); createWebAssemblyDisassembler);
TargetRegistry::RegisterMCDisassembler(TheWebAssemblyTarget64, TargetRegistry::RegisterMCDisassembler(getTheWebAssemblyTarget64(),
createWebAssemblyDisassembler); createWebAssemblyDisassembler);
} }
MCDisassembler::DecodeStatus WebAssemblyDisassembler::getInstruction( MCDisassembler::DecodeStatus WebAssemblyDisassembler::getInstruction(
MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t /*Address*/, MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t /*Address*/,
raw_ostream &OS, raw_ostream &CS) const { raw_ostream &OS, raw_ostream &CS) const {
Size = 0; Size = 0;
uint64_t Pos = 0; uint64_t Pos = 0;
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lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

Show All 24 Lines
class MCContext; class MCContext;
class MCInstrInfo; class MCInstrInfo;
class MCObjectWriter; class MCObjectWriter;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
class Triple; class Triple;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheWebAssemblyTarget32; Target &getTheWebAssemblyTarget32();
extern Target TheWebAssemblyTarget64; Target &getTheWebAssemblyTarget64();
MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII); MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT); MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
MCObjectWriter *createWebAssemblyELFObjectWriter(raw_pwrite_stream &OS, MCObjectWriter *createWebAssemblyELFObjectWriter(raw_pwrite_stream &OS,
bool Is64Bit, uint8_t OSABI); bool Is64Bit, uint8_t OSABI);
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lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Linesstatic MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
formatted_raw_ostream &OS, formatted_raw_ostream &OS,
MCInstPrinter * /*InstPrint*/, MCInstPrinter * /*InstPrint*/,
bool /*isVerboseAsm*/) { bool /*isVerboseAsm*/) {
return new WebAssemblyTargetAsmStreamer(S, OS); return new WebAssemblyTargetAsmStreamer(S, OS);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeWebAssemblyTargetMC() { extern "C" void LLVMInitializeWebAssemblyTargetMC() {
for (Target *T : {&TheWebAssemblyTarget32, &TheWebAssemblyTarget64}) { for (Target *T :
{&getTheWebAssemblyTarget32(), &getTheWebAssemblyTarget64()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createMCAsmInfo); RegisterMCAsmInfoFn X(*T, createMCAsmInfo);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createMCInstrInfo);
// Register the MC codegen info. // Register the MC codegen info.
TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts); TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts);
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lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.cpp

Show All 13 Lines
#include "MCTargetDesc/WebAssemblyMCTargetDesc.h" #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "llvm/ADT/Triple.h" #include "llvm/ADT/Triple.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "wasm-target-info" #define DEBUG_TYPE "wasm-target-info"
Target llvm::TheWebAssemblyTarget32; Target llvm::getTheWebAssemblyTarget32();
Target llvm::TheWebAssemblyTarget64; Target llvm::getTheWebAssemblyTarget64();
extern "C" void LLVMInitializeWebAssemblyTargetInfo() { extern "C" void LLVMInitializeWebAssemblyTargetInfo() {
RegisterTarget<Triple::wasm32> X(TheWebAssemblyTarget32, "wasm32", RegisterTarget<Triple::wasm32> X(getTheWebAssemblyTarget32(), "wasm32",
"WebAssembly 32-bit"); "WebAssembly 32-bit");
RegisterTarget<Triple::wasm64> Y(TheWebAssemblyTarget64, "wasm64", RegisterTarget<Triple::wasm64> Y(getTheWebAssemblyTarget64(), "wasm64",
"WebAssembly 64-bit"); "WebAssembly 64-bit");
} }

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

Show First 20 Lines • Show All 307 Lines • ▼ Show 20 Lines if (!ExtraCode) {
return false; return false;
} }
return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, AsmVariant, ExtraCode, OS); return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, AsmVariant, ExtraCode, OS);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeWebAssemblyAsmPrinter() { extern "C" void LLVMInitializeWebAssemblyAsmPrinter() {
RegisterAsmPrinter<WebAssemblyAsmPrinter> X(TheWebAssemblyTarget32); RegisterAsmPrinter<WebAssemblyAsmPrinter> X(getTheWebAssemblyTarget32());
RegisterAsmPrinter<WebAssemblyAsmPrinter> Y(TheWebAssemblyTarget64); RegisterAsmPrinter<WebAssemblyAsmPrinter> Y(getTheWebAssemblyTarget64());
} }

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

Show All 37 Lines
// Emscripten's asm.js-style setjmp/longjmp handling // Emscripten's asm.js-style setjmp/longjmp handling
static cl::opt<bool> EnableEmSjLj( static cl::opt<bool> EnableEmSjLj(
"enable-emscripten-sjlj", "enable-emscripten-sjlj",
cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"), cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
cl::init(false)); cl::init(false));
extern "C" void LLVMInitializeWebAssemblyTarget() { extern "C" void LLVMInitializeWebAssemblyTarget() {
// Register the target. // Register the target.
RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32); RegisterTargetMachine<WebAssemblyTargetMachine> X(
RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64); getTheWebAssemblyTarget32());
RegisterTargetMachine<WebAssemblyTargetMachine> Y(
getTheWebAssemblyTarget64());
// Register exception handling pass to opt // Register exception handling pass to opt
initializeWebAssemblyLowerEmscriptenEHSjLjPass( initializeWebAssemblyLowerEmscriptenEHSjLjPass(
*PassRegistry::getPassRegistry()); *PassRegistry::getPassRegistry());
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// WebAssembly Lowering public interface. // WebAssembly Lowering public interface.
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lib/Target/X86/AsmParser/X86AsmParser.cpp

Show First 20 Lines • Show All 3,059 Lines • ▼ Show 20 Lines if (IDVal == ".code16") {
return false; return false;
} }
return false; return false;
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeX86AsmParser() { extern "C" void LLVMInitializeX86AsmParser() {
RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target); RegisterMCAsmParser<X86AsmParser> X(getTheX86_32Target());
RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target); RegisterMCAsmParser<X86AsmParser> Y(getTheX86_64Target());
} }
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#define GET_SUBTARGET_FEATURE_NAME #define GET_SUBTARGET_FEATURE_NAME
#include "X86GenAsmMatcher.inc" #include "X86GenAsmMatcher.inc"

lib/Target/X86/Disassembler/X86Disassembler.cpp

Show First 20 Lines • Show All 1,060 Lines • ▼ Show 20 Linesstatic MCDisassembler *createX86Disassembler(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx) { MCContext &Ctx) {
std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo()); std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
return new X86GenericDisassembler(STI, Ctx, std::move(MII)); return new X86GenericDisassembler(STI, Ctx, std::move(MII));
} }
extern "C" void LLVMInitializeX86Disassembler() { extern "C" void LLVMInitializeX86Disassembler() {
// Register the disassembler. // Register the disassembler.
TargetRegistry::RegisterMCDisassembler(TheX86_32Target, TargetRegistry::RegisterMCDisassembler(getTheX86_32Target(),
createX86Disassembler); createX86Disassembler);
TargetRegistry::RegisterMCDisassembler(TheX86_64Target, TargetRegistry::RegisterMCDisassembler(getTheX86_64Target(),
createX86Disassembler); createX86Disassembler);
} }

lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h

Show All 28 Lines
class MCRelocationInfo; class MCRelocationInfo;
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
class Triple; class Triple;
class StringRef; class StringRef;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheX86_32Target, TheX86_64Target; Target &getTheX86_32Target();
Target &getTheX86_64Target();
/// Flavour of dwarf regnumbers /// Flavour of dwarf regnumbers
/// ///
namespace DWARFFlavour { namespace DWARFFlavour {
enum { enum {
X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
}; };
} }
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lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
} }
static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
return new MCInstrAnalysis(Info); return new MCInstrAnalysis(Info);
} }
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeX86TargetMC() { extern "C" void LLVMInitializeX86TargetMC() {
for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
// Register the MC codegen info. // Register the MC codegen info.
RegisterMCAdjustCodeGenOptsFn Y(*T, adjustCodeGenOpts); RegisterMCAdjustCodeGenOptsFn Y(*T, adjustCodeGenOpts);
// Register the MC instruction info. // Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
Show All 17 Lines for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
// Register the MCInstPrinter. // Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
// Register the MC relocation info. // Register the MC relocation info.
TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
} }
// Register the asm backend. // Register the asm backend.
TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(),
createX86_32AsmBackend); createX86_32AsmBackend);
TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(),
createX86_64AsmBackend); createX86_64AsmBackend);
} }
unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
bool High) { bool High) {
switch (Size) { switch (Size) {
default: return 0; default: return 0;
case 8: case 8:
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lib/Target/X86/TargetInfo/X86TargetInfo.cpp

//===-- X86TargetInfo.cpp - X86 Target Implementation ---------------------===// //===-- X86TargetInfo.cpp - X86 Target Implementation ---------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MCTargetDesc/X86MCTargetDesc.h" #include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
using namespace llvm; using namespace llvm;
Target llvm::TheX86_32Target, llvm::TheX86_64Target; Target &llvm::getTheX86_32Target() {
static Target TheX86_32Target;
return TheX86_32Target;
}
Target &llvm::getTheX86_64Target() {
static Target TheX86_64Target;
return TheX86_64Target;
}
extern "C" void LLVMInitializeX86TargetInfo() { extern "C" void LLVMInitializeX86TargetInfo() {
RegisterTarget<Triple::x86, /*HasJIT=*/true> RegisterTarget<Triple::x86, /*HasJIT=*/true> X(
X(TheX86_32Target, "x86", "32-bit X86: Pentium-Pro and above"); getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above");
RegisterTarget<Triple::x86_64, /*HasJIT=*/true> RegisterTarget<Triple::x86_64, /*HasJIT=*/true> Y(
Y(TheX86_64Target, "x86-64", "64-bit X86: EM64T and AMD64"); getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64");
} }

lib/Target/X86/X86AsmPrinter.cpp

Show First 20 Lines • Show All 650 Lines • ▼ Show 20 Lines
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Target Registry Stuff // Target Registry Stuff
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Force static initialization. // Force static initialization.
extern "C" void LLVMInitializeX86AsmPrinter() { extern "C" void LLVMInitializeX86AsmPrinter() {
RegisterAsmPrinter<X86AsmPrinter> X(TheX86_32Target); RegisterAsmPrinter<X86AsmPrinter> X(getTheX86_32Target());
RegisterAsmPrinter<X86AsmPrinter> Y(TheX86_64Target); RegisterAsmPrinter<X86AsmPrinter> Y(getTheX86_64Target());
} }

lib/Target/X86/X86TargetMachine.cpp

Show All 29 Linesstatic cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
cl::init(true), cl::Hidden); cl::init(true), cl::Hidden);
namespace llvm { namespace llvm {
void initializeWinEHStatePassPass(PassRegistry &); void initializeWinEHStatePassPass(PassRegistry &);
} }
extern "C" void LLVMInitializeX86Target() { extern "C" void LLVMInitializeX86Target() {
// Register the target. // Register the target.
RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target); RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target); RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
PassRegistry &PR = *PassRegistry::getPassRegistry(); PassRegistry &PR = *PassRegistry::getPassRegistry();
initializeWinEHStatePassPass(PR); initializeWinEHStatePassPass(PR);
initializeFixupBWInstPassPass(PR); initializeFixupBWInstPassPass(PR);
} }
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
if (TT.isOSBinFormatMachO()) { if (TT.isOSBinFormatMachO()) {
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