[AArch64] Registering default MCInstrAnalysis

[aizatsky]

Summary

Even in this form it is useful: it can detect branch instructions.

https://github.com/google/sanitizers/issues/706

[t.p.northover]

I just added llvm-commits to the subscribers, otherwise the mailing list won't see the patch.

[t.p.northover]

It looks like this ought to be testable from llvm-objdump (it seems to ise the MCInstrAnalysis to produce better output for branches).

[aizatsky]

In D23426#513089, @t.p.northover wrote:

It looks like this ought to be testable from llvm-objdump (it seems to ise the MCInstrAnalysis to produce better output for branches).

No, not yet. It requires evaluateBranch to work. And that one doesn't work for AArch64 because offset arguments are not correctly annotated in assembly. (https://github.com/google/sanitizers/issues/706)

I was going to try to address the second issue in the next change. BTW if you have any pointers towards what needs to be changed, I would be grateful for any help/pointers.

[t.p.northover]

And that one doesn't work for AArch64 because offset arguments are not correctly annotated in assembly. (https://github.com/google/sanitizers/issues/706).

Looking at the default implementation my best guess is that MI.getOperand(0).getImm() actually returns Offset / 4 for branches on AArch64 (because instructions must always be 4-byte aligned).

But I could be wrong, because I don't know exactly how it's failing.

Tim.

[t.p.northover]

Depending on how you implement the AArch64 override you may want to set the branch operands to OPERAND_PCREL in the AArch64InstrInfo.td files to. Checking the opcodes directly is probably fine too though (you've got to know about them anyway to find the offset operand).

[aizatsky]

In D23426#513137, @t.p.northover wrote:

Depending on how you implement the AArch64 override you may want to set the branch operands to OPERAND_PCREL in the AArch64InstrInfo.td files to. Checking the opcodes directly is probably fine too though (you've got to know about them anyway to find the offset operand).

You are right, OperandType != MCOI::OPERAND_PCREL is never successful. Didn't look into getImm yet.

[aizatsky]

added test.

[aizatsky]

I managed to test this with my sancov tool. It can't print addresses yet, but at least it can initialize the instruction analysis.

[aizatsky]

rebase

[t.p.northover]

Oh good! This looks fine, thanks for adding the test.

Tim.

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

 // This file provides AArch64 specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64MCTargetDesc.h"
 #include "AArch64ELFStreamer.h"
 #include "AArch64MCAsmInfo.h"
 #include "InstPrinter/AArch64InstPrinter.h"
+#include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
static MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
                                        raw_pwrite_stream &OS,
                                        MCCodeEmitter *Emitter, bool RelaxAll,
                                        bool DWARFMustBeAtTheEnd) {
   return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
                              DWARFMustBeAtTheEnd,
                              /*LabelSections*/ true);
 }
 
+static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
+  return new MCInstrAnalysis(Info);
+}
+
 // Force static initialization.
 extern "C" void LLVMInitializeAArch64TargetMC() {
   for (Target *T :
        {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) {
     // Register the MC asm info.
     RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
 
     // Register the MC codegen info.
     TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts);
 
     // Register the MC instruction info.
     TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
 
     // Register the MC register info.
     TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
 
     // Register the MC subtarget info.
     TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
 
+    // Register the MC instruction analyzer.
+    TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis);
+
     // Register the MC Code Emitter
     TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
 
     // Register the obj streamers.
     TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
     TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
 
     // Register the obj target streamer.

llvm/trunk/test/tools/sancov/print_coverage_pcs.test

 REQUIRES: x86-registered-target
 RUN: sancov -print-coverage-pcs %p/Inputs/test-linux_x86_64 | FileCheck %s --check-prefix=LINUX
 RUN: llvm-objdump -d %p/Inputs/test-windows_x86_64 | FileCheck %s --check-prefix=DISAS_WIN
 RUN: sancov -print-coverage-pcs %p/Inputs/test-windows_x86_64 | FileCheck %s --check-prefix=WINDOWS
 RUN: sancov -print-coverage-pcs %p/Inputs/test-darwin_x86_64 | FileCheck %s --check-prefix=DARWIN
+RUN: not sancov -print-coverage-pcs %p/Inputs/test-linux_android_aarch64 2>&1 | FileCheck %s --check-prefix=AARCH64
 
 LINUX: 0x4e132b
 LINUX: 0x4e1472
 LINUX: 0x4e14c2
 LINUX: 0x4e1520
 LINUX: 0x4e1553
 LINUX: 0x4e1586
 LINUX: 0x4e1635

 DARWIN: 0x1000016dd
 DARWIN: 0x10000179d
 DARWIN: 0x1000017cc
 DARWIN: 0x10000189d
 DARWIN: 0x1000018e0
 DARWIN: 0x100001906
 DARWIN: 0x1000019dc
 DARWIN: 0x100001a28
+
+AARCH64: Error: __sanitizer_cov* functions not found
+