We already have a combine for this pattern when the input to shl
is add, so we just need to enable the transformation with the input
is or.
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Needs a test for the multiple use case. Tests separate from the ds_permute would also be good
The pattern was matching correctly but always emitting add in the output dag,
even when int he input was or. This was fixed and I added a test case for this
behavior.
Rebaing - this is part of constant canonicalizations to try and combine MUL/SHL ops separated by ADD/OR ops.
If an AMDGPU expert can check the test changes, that'd be great.
test/CodeGen/AMDGPU/fneg-fabs.f16.ll | ||
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90–91 | Does this test generate extra shl instructions now, or did it generate those before the patch and there just weren't any check lines for it? |
Sorry for the late reply - this fell to the bottom of my todo pile for a while
test/CodeGen/AMDGPU/fneg-fabs.f16.ll | ||
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90–91 | To confirm, the shifts were always there but the test didn't check for them |
For reference, instcombine does the same transform in InstCombiner::tryFactorization.
I can't really check the AMDGPU tests; otherwise LGTM.
Does this test generate extra shl instructions now, or did it generate those before the patch and there just weren't any check lines for it?