[WIP] MachineFunction Properties

[dschuff]

Summary

This is a strawman design for a set of "properties" that a
MachineFunction can have at particular points in time. Currently we have
MachineRegisterInfo::isSSA() and MachineRegisterInfo::tracksLiveness()
and we are also discussing the "post-RA" property (i.e. there are no
virtual register operands). We want an easy way for MachineFunctions to
declare that they require a particular property to hold, and that they
set or clear a particular property. This facility is somewhat similar to
the way passes can declare their required analysis passes, inviting a
comparison of the requirements/use cases:

1. Like analysis passes, passes can require that property hold.
2. Unlike analysis, all possible properties can be listed in one place as an enum (as opposed to an arbitrary pass ID)
3. Properties can be set by a pass (unlike analysis where the anlysis is provided by a special kind of pass and managed by a pass manager)
4. Properties may be conditionally cleared (e.g. BranchFolder conditionally invalidates liveness)

This design just represents the properties as a bit vector stored on the
MachineFunctionObject, and the pass requirements and modifications as
objects on the MachineFunctionPass. Passes can declare that they
require, or unconditionally set or clear properties by setting these
objects in their constructor, (which results in automatic checking) or
they can query or modify the MachineFunction's properties when the pass
is run.

Currently it just implements the "post-RA" property as
AllVRegsAllocated, for X86. It still needs a few fixes and name bikeshedding.

Possible alternative design features/constraints:

• Allow passes to require that a property is clear (instead of just set)
• Make all passes require a particular property unless they clear the requirement themselves
• Allow targets to extend the list

Possible alternative implementations:

• Return set of set/cleared properties from a query function (similar to getAnalysisUsage) instead of keeping a static data structure set in the constructor

[qcolombet]

Hi Derek,

I like the direction of your patch. I would go one step further and have the pass manager checks that required properties are set before running a pass (and error out if this is false).

I could see value in having the properties extendable by the target, in particular if the pass manager checks the dependencies for us.

Couple of comments inlined.

Thanks,
-Quentin

include/llvm/CodeGen/MachineFunction.h

95

I think it would be nice to have this extendable by the target, especially if the properties are checked and/or give some control over the compilation pipeline.
E.g., On ARM, passes could set a property has load/store and the load/store optimizer would be only run if such property is true. The example is a bit lame, but you get the idea.

Obviously, this can already be achieved by querying within the passes the MachineFunctionInfo instances, but it sounds reasonable to have this kind of broad mechanism.

108

I think this does not follow the coding standard:
Enumerators (e.g. enum { Foo, Bar }) [...] should start with an upper-case letter, just like types.

http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

include/llvm/CodeGen/MachineFunctionPass.h

68

We may allow to return nullptr. Not all passes have properties.
Another other would be to have a static const empty set MachineFunctionProperties, used when those pointers are null.

76

If you go that way, I would make them lazily allocated.
I.e., mutable should be in order :).

lib/CodeGen/FuncletLayout.cpp

29

My 2c; I would find it more natural to define this kind of dependencies in something like getAnalysisUsage, possibly something new.

The value, I see out of this, is the pass manager could check this kind of dependencies for us and error out is something is not correct.

lib/Target/NVPTX/NVPTXTargetMachine.cpp

229

This is an unrelated change, right?

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

110

Ditto.

186

Ditto.

214

Ditto.

222

Ditto.

[• tstellarAMD]

include/llvm/CodeGen/MachineFunction.h

107

You may want to clarify what kAllVRegsAllocated means, because targets are allowed to introduce new virtual registers after register allocation in TargetInstrInfo::eliminateFrameIndex(). These are eliminated by PEI using the register scavenger.

[dschuff]

• Change interface to be more like getAnalysisUsage

include/llvm/CodeGen/MachineFunction.h

95

This kind of use does seem reasonable; that kind of thing would have the caveat that in order to use it, any pass or function that added load or store instructions would have to remember to set the property. I'll have to think a bit more about what the extension mechanism would look like. A lot of the simplicity of this current form is owed to the fact that all of the bits are specified in one place.

107

Yes; although notably this all happens within the run of the PEI pass. So while it has a transient state, it does preserve the invariant.
But yes, the exact meaning of these should be clarified, and we should probably revisit the naming of things.

include/llvm/CodeGen/MachineFunctionPass.h

68

(addressed with a diferent interface style; see below)

76

(ditto)

lib/CodeGen/FuncletLayout.cpp

29

I originally did it this way to avoid having to call getRequiredProperties (and thus construct the required, set, and cleared properties on every function). However I found another way around that, so I change it to be more like getAnalysisUsage, which I agree is nicer (and now has the added benefit that e.g. the required properties can't accidentally get modified during runtime).

Because these properties only apply to MachineFunctionPasses, and because Pass managers only deal with FunctionPasses, I still think it's cleaner to do the checking in MachineFunctionPass::runOnFunction() instead of propagating all of this stuff out to the pass manager via public interfaces. Note that as it is right now, it still has the nice property that the dependencies are automatically checked for us (where "us" is the authors of machine function passes).

lib/Target/NVPTX/NVPTXTargetMachine.cpp

229

Actually, it's not; these are all passes that are running today in NVPTX and WebAssembly that were originally written as post-RA passes, but have no particular assertions or dependencies on the lack of virtual registers, and so were not explicitly disabled. (They mostly do nothing for virtual architectures). But since I've now added this requiredProperty mechanism, they now have to be disabled, or else they will fail the check.

So basically this is exactly the effect that you wanted all along; these passes can't be run for virtual targets now (until and unless someone ensures that they support virtual registers and changes the requirement).

[qcolombet]

Hi Derek,

Simple and efficiency, nice :).

LGTM.

I agree that, as it is, the checks are enough, we do not need to expose this to the pass manager.

Couple of nits inlined.

Cheers,
-Quentin

include/llvm/CodeGen/MachineFunction.h

95

“Promote” the comment to doxygen style (///).

98

Just a remark: if we want to give more control to the targets with possible properties, we can make the universe of the BitVector an argument of the constructor and just assert that the universe supports at least LastProperty elements.

215

Add a comment.

lib/CodeGen/MachineFunctionPass.cpp

47

Add a message in the assert.

lib/Target/NVPTX/NVPTXTargetMachine.cpp

229

Great!
It means it already pays off by simplifying some compilation pipelines :).

[dschuff]

• Change interface to be more like getAnalysisUsage
• Address comments
• Add AllVRegsAllocated to MIR and convert one test

[dschuff]

Thanks for the reviews!
There's one more thing this change needs before it can land, and that's a representation in MIR for the properties. Conveniently, my reviewer is an expert on the subject :)

Here's one possible MIR representation, which just adds allVRegsAllocated as another optional top-level tag for the function for each property (and which would also retain compatibility with MIR for e.g. isSSA). Do you think it should also have its own namespace like frameInfo, or maybe its own initialization routine like MIRParserImpl::initializeRegisterInfo?

include/llvm/CodeGen/MachineFunction.h

98

Sounds good, I added possible future TODOs in a comment.

[dschuff]

• Change interface to be more like getAnalysisUsage
• Address comments
• Add AllVRegsAllocated to MIR and convert one test
• Update the remaining MIR tests

include/llvm/CodeGen/MIRYamlMapping.h

template <> struct MappingTraits<MachineFrameInfo> {
   }
 };
 
 struct MachineFunction {
   StringRef Name;
   unsigned Alignment = 0;
   bool ExposesReturnsTwice = false;
   bool HasInlineAsm = false;
+  // MachineFunctionProperties
+  bool AllVRegsAllocated = false;
   // Register information
   bool IsSSA = false;
   bool TracksRegLiveness = false;
   bool TracksSubRegLiveness = false;
   std::vector<VirtualRegisterDefinition> VirtualRegisters;
   std::vector<MachineFunctionLiveIn> LiveIns;
   Optional<std::vector<FlowStringValue>> CalleeSavedRegisters;
   // TODO: Serialize the various register masks.
   // Frame information
   MachineFrameInfo FrameInfo;
   std::vector<FixedMachineStackObject> FixedStackObjects;
   std::vector<MachineStackObject> StackObjects;
   std::vector<MachineConstantPoolValue> Constants; /// Constant pool.
   MachineJumpTable JumpTableInfo;
   BlockStringValue Body;
 };
 
 template <> struct MappingTraits<MachineFunction> {
   static void mapping(IO &YamlIO, MachineFunction &MF) {
     YamlIO.mapRequired("name", MF.Name);
     YamlIO.mapOptional("alignment", MF.Alignment);
     YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
     YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
+    YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
     YamlIO.mapOptional("isSSA", MF.IsSSA);
     YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
     YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
     YamlIO.mapOptional("registers", MF.VirtualRegisters);
     YamlIO.mapOptional("liveins", MF.LiveIns);
     YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);
     YamlIO.mapOptional("frameInfo", MF.FrameInfo);
     YamlIO.mapOptional("fixedStack", MF.FixedStackObjects);

include/llvm/CodeGen/MachineFunction.h

 // This class also contains pointers to various classes which hold
 // target-specific information about the generated code.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_MACHINEFUNCTION_H
 #define LLVM_CODEGEN_MACHINEFUNCTION_H
 
+#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/ilist.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/Metadata.h"
 #include "llvm/Support/Allocator.h"
 #include "llvm/Support/ArrayRecycler.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Recycler.h"
struct MachineFunctionInfo {
   ///
   /// This function can be overridden in a derive class.
   template<typename Ty>
   static Ty *create(BumpPtrAllocator &Allocator, MachineFunction &MF) {
     return new (Allocator.Allocate<Ty>()) Ty(MF);
   }
 };
 
+/// Properties which a MachineFunction may have at a given point in time.
+/// Each of these has checking code in the MachineVerifier, and passes can
+/// require that a property be set.
+class MachineFunctionProperties {
+  // TODO: Add MachineVerifier checks for AllVRegsAllocated
+  // TODO: Add a way to print the properties and make more useful error messages
+  // Possible TODO: Allow targets to extend this (perhaps by allowing the
+  // constructor to specify the size of the bit vector)
+  // Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be
+  // stated as the negative of "has vregs"
+
+  // Stated in "positive" form; i.e. a pass could require that the property
+  // hold, but not that it does not hold.
+  BitVector Properties =
+      BitVector(static_cast<unsigned>(Property::LastProperty));
+
+ public:
+  // Property descriptions:
+  // IsSSA (currently unused, intended to eventually replace
+  // MachineRegisterInfo::isSSA())
+  // TracksLiveness: (currently unsued, intended to eventually replace
+  // MachineRegisterInfo::tracksLiveness())
+  // AllVRegsAllocated: All virtual registers have been allocated; i.e. all
+  // register operands are physical registers.
+  enum class Property : unsigned {
+    IsSSA,
+    TracksLiveness,
+    AllVRegsAllocated,
+    LastProperty,
+  };
+
+  bool hasProperty(Property P) const {
+    return Properties[static_cast<unsigned>(P)];
+  }
+  MachineFunctionProperties &set(Property P) {
+    Properties.set(static_cast<unsigned>(P));
+    return *this;
+  }
+  MachineFunctionProperties &clear(Property P) {
+    Properties.reset(static_cast<unsigned>(P));
+    return *this;
+  }
+  MachineFunctionProperties &set(const MachineFunctionProperties &MFP) {
+    Properties |= MFP.Properties;
+    return *this;
+  }
+  MachineFunctionProperties &clear(const MachineFunctionProperties &MFP) {
+    Properties.reset(MFP.Properties);
+    return *this;
+  }
+  // Returns true if all properties set in V (i.e. required by a pass) are set
+  // in this.
+  bool verifyRequiredProperties(const MachineFunctionProperties &V) const {
+    return !V.Properties.test(Properties);
+  }
+};
+
 class MachineFunction {
   const Function *Fn;
   const TargetMachine &Target;
   const TargetSubtargetInfo *STI;
   MCContext &Ctx;
   MachineModuleInfo &MMI;
 
   // RegInfo - Information about each register in use in the function.
class MachineFunction {
   /// the attribute itself.
   /// This is used to limit optimizations which cannot reason
   /// about the control flow of such functions.
   bool ExposesReturnsTwice = false;
 
   /// True if the function includes any inline assembly.
   bool HasInlineAsm = false;
 
+  /// Current high-level properties of the IR of the function (e.g. is in SSA
+  /// form or whether registers have been allocated)
+  MachineFunctionProperties Properties;
+
   // Allocation management for pseudo source values.
   std::unique_ptr<PseudoSourceValueManager> PSVManager;
 
   MachineFunction(const MachineFunction &) = delete;
   void operator=(const MachineFunction&) = delete;
 public:
   MachineFunction(const Function *Fn, const TargetMachine &TM,
                   unsigned FunctionNum, MachineModuleInfo &MMI);
bool hasInlineAsm() const {
     return HasInlineAsm;
   }
 
   /// Set a flag that indicates that the function contains inline assembly.
   void setHasInlineAsm(bool B) {
     HasInlineAsm = B;
   }
 
+  /// Get the function properties
+  const MachineFunctionProperties &getProperties() const { return Properties; }
+  MachineFunctionProperties &getProperties() { return Properties; }
+
   /// getInfo - Keep track of various per-function pieces of information for
   /// backends that would like to do so.
   ///
   template<typename Ty>
   Ty *getInfo() {
     if (!MFInfo)
       MFInfo = Ty::template create<Ty>(Allocator, *this);
     return static_cast<Ty*>(MFInfo);

include/llvm/CodeGen/MachineFunctionPass.h

 // care of declaring that no LLVM passes are invalidated.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_MACHINEFUNCTIONPASS_H
 #define LLVM_CODEGEN_MACHINEFUNCTIONPASS_H
 
 #include "llvm/Pass.h"
+#include "llvm/CodeGen/MachineFunction.h"
 
 namespace llvm {
 
-class MachineFunction;
-
 /// MachineFunctionPass - This class adapts the FunctionPass interface to
 /// allow convenient creation of passes that operate on the MachineFunction
 /// representation. Instead of overriding runOnFunction, subclasses
 /// override runOnMachineFunction.
 class MachineFunctionPass : public FunctionPass {
+public:
+  bool doInitialization(Module&) override {
+    // Cache the properties info at module-init time so we don't have to
+    // construct them for every function.
+    RequiredProperties = getRequiredProperties();
+    SetProperties = getSetProperties();
+    ClearedProperties = getClearedProperties();
+    return false;
+  }
 protected:
   explicit MachineFunctionPass(char &ID) : FunctionPass(ID) {}
 
   /// runOnMachineFunction - This method must be overloaded to perform the
   /// desired machine code transformation or analysis.
   ///
   virtual bool runOnMachineFunction(MachineFunction &MF) = 0;
 
   /// getAnalysisUsage - Subclasses that override getAnalysisUsage
   /// must call this.
   ///
   /// For MachineFunctionPasses, calling AU.preservesCFG() indicates that
   /// the pass does not modify the MachineBasicBlock CFG.
   ///
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
+  virtual MachineFunctionProperties getRequiredProperties() const {
+    return MachineFunctionProperties();
+  }
+  virtual MachineFunctionProperties getSetProperties() const {
+    return MachineFunctionProperties();
+  }
+  virtual MachineFunctionProperties getClearedProperties() const {
+    return MachineFunctionProperties();
+  }
+
 private:
+  MachineFunctionProperties RequiredProperties;
+  MachineFunctionProperties SetProperties;
+  MachineFunctionProperties ClearedProperties;
+
   /// createPrinterPass - Get a machine function printer pass.
   Pass *createPrinterPass(raw_ostream &O,
                           const std::string &Banner) const override;
 
   bool runOnFunction(Function &F) override;
 };
 
 } // End llvm namespace
 
 #endif

lib/CodeGen/FuncletLayout.cpp

 
 namespace {
 class FuncletLayout : public MachineFunctionPass {
 public:
   static char ID; // Pass identification, replacement for typeid
   FuncletLayout() : MachineFunctionPass(ID) {
     initializeFuncletLayoutPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
 };
 }
 
 char FuncletLayout::ID = 0;
 char &llvm::FuncletLayoutID = FuncletLayout::ID;
 INITIALIZE_PASS(FuncletLayout, "funclet-layout",
                 "Contiguously Lay Out Funclets", false, false)
 

lib/CodeGen/ImplicitNullChecks.cpp

 public:
   static char ID;
 
   ImplicitNullChecks() : MachineFunctionPass(ID) {
     initializeImplicitNullChecksPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
+
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
 };
 
 /// \brief Detect re-ordering hazards and dependencies.
 ///
 /// This class keeps track of defs and uses, and can be queried if a given
 /// machine instruction can be re-ordered from after the machine instructions
 /// seen so far to before them.
 class HazardDetector {

lib/CodeGen/LiveDebugValues.cpp

public:
 
   /// Default construct and initialize the pass.
   LiveDebugValues();
 
   /// Tell the pass manager which passes we depend on and what
   /// information we preserve.
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   /// Print to ostream with a message.
   void printVarLocInMBB(const VarLocInMBB &V, const char *msg,
                         raw_ostream &Out) const;
 
   /// Calculate the liveness information for the given machine function.
   bool runOnMachineFunction(MachineFunction &MF) override;
 };
 } // namespace

lib/CodeGen/MIRParser/MIRParser.cpp

if (It == Functions.end())
     return error(Twine("no machine function information for function '") +
                  MF.getName() + "' in the MIR file");
   // TODO: Recreate the machine function.
   const yaml::MachineFunction &YamlMF = *It->getValue();
   if (YamlMF.Alignment)
     MF.setAlignment(YamlMF.Alignment);
   MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
   MF.setHasInlineAsm(YamlMF.HasInlineAsm);
+  if (YamlMF.AllVRegsAllocated)
+    MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated);
   PerFunctionMIParsingState PFS;
   if (initializeRegisterInfo(MF, YamlMF, PFS))
     return true;
   if (!YamlMF.Constants.empty()) {
     auto *ConstantPool = MF.getConstantPool();
     assert(ConstantPool && "Constant pool must be created");
     if (initializeConstantPool(*ConstantPool, YamlMF, MF,
                                PFS.ConstantPoolSlots))

lib/CodeGen/MIRPrinter.cpp

 void MIRPrinter::print(const MachineFunction &MF) {
   initRegisterMaskIds(MF);
 
   yaml::MachineFunction YamlMF;
   YamlMF.Name = MF.getName();
   YamlMF.Alignment = MF.getAlignment();
   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
   YamlMF.HasInlineAsm = MF.hasInlineAsm();
+  YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::AllVRegsAllocated);
+
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   ModuleSlotTracker MST(MF.getFunction()->getParent());
   MST.incorporateFunction(*MF.getFunction());
   convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
   convertStackObjects(YamlMF, *MF.getFrameInfo(), MF.getMMI(), MST,
                       MF.getSubtarget().getRegisterInfo());
   if (const auto *ConstantPool = MF.getConstantPool())
     convert(YamlMF, *ConstantPool);

lib/CodeGen/MachineCopyPropagation.cpp

namespace {
   public:
     static char ID; // Pass identification, replacement for typeid
     MachineCopyPropagation() : MachineFunctionPass(ID) {
       initializeMachineCopyPropagationPass(*PassRegistry::getPassRegistry());
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
   private:
     void ClobberRegister(unsigned Reg);
     void CopyPropagateBlock(MachineBasicBlock &MBB);
     bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
 
     /// Candidates for deletion.
     SmallSetVector<MachineInstr*, 8> MaybeDeadCopies;
     /// Def -> available copies map.

lib/CodeGen/MachineFunctionPass.cpp

 #include "llvm/Analysis/BasicAliasAnalysis.h"
 #include "llvm/Analysis/DominanceFrontier.h"
 #include "llvm/Analysis/GlobalsModRef.h"
 #include "llvm/Analysis/IVUsers.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/MemoryDependenceAnalysis.h"
 #include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/StackProtector.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/Function.h"
+
 using namespace llvm;
 
 Pass *MachineFunctionPass::createPrinterPass(raw_ostream &O,
                                              const std::string &Banner) const {
   return createMachineFunctionPrinterPass(O, Banner);
 }
 
 bool MachineFunctionPass::runOnFunction(Function &F) {
   // Do not codegen any 'available_externally' functions at all, they have
   // definitions outside the translation unit.
   if (F.hasAvailableExternallyLinkage())
     return false;
 
   MachineFunction &MF = getAnalysis<MachineFunctionAnalysis>().getMF();
-  return runOnMachineFunction(MF);
+  MachineFunctionProperties &MFProps = MF.getProperties();
+
+  assert(MFProps.verifyRequiredProperties(RequiredProperties) &&
+         "Properties required by the pass are not met by the function");
+
+  bool RV = runOnMachineFunction(MF);
+
+  MFProps.set(SetProperties);
+  MFProps.clear(ClearedProperties);
+  return RV;
 }
 
 void MachineFunctionPass::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequired<MachineFunctionAnalysis>();
   AU.addPreserved<MachineFunctionAnalysis>();
 
   // MachineFunctionPass preserves all LLVM IR passes, but there's no
   // high-level way to express this. Instead, just list a bunch of

lib/CodeGen/PostRASchedulerList.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<TargetPassConfig>();
       AU.addRequired<MachineDominatorTree>();
       AU.addPreserved<MachineDominatorTree>();
       AU.addRequired<MachineLoopInfo>();
       AU.addPreserved<MachineLoopInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
     bool enablePostRAScheduler(
         const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
         TargetSubtargetInfo::AntiDepBreakMode &Mode,
         TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
   };
   char PostRAScheduler::ID = 0;

lib/CodeGen/PrologEpilogInserter.cpp

 public:
   static char ID;
   PEI() : MachineFunctionPass(ID) {
     initializePEIPass(*PassRegistry::getPassRegistry());
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
   /// frame indexes with appropriate references.
   ///
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
 private:
   RegScavenger *RS;
 

lib/CodeGen/RegAllocBasic.cpp

public:
   /// Return the pass name.
   const char* getPassName() const override {
     return "Basic Register Allocator";
   }
 
   /// RABasic analysis usage.
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
+  MachineFunctionProperties getSetProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   void releaseMemory() override;
 
   Spiller &spiller() override { return *SpillerInstance; }
 
   void enqueue(LiveInterval *LI) override {
     Queue.push(LI);
   }
 

lib/CodeGen/RegAllocFast.cpp

static RegisterRegAlloc
   fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
 
 namespace {
   class RAFast : public MachineFunctionPass {
   public:
     static char ID;
     RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
                isBulkSpilling(false) {}
+
   private:
     MachineFunction *MF;
     MachineRegisterInfo *MRI;
     const TargetRegisterInfo *TRI;
     const TargetInstrInfo *TII;
     RegisterClassInfo RegClassInfo;
 
     // Basic block currently being allocated.
const char *getPassName() const override {
       return "Fast Register Allocator";
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
+    MachineFunctionProperties getSetProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
   private:
     bool runOnMachineFunction(MachineFunction &Fn) override;
     void AllocateBasicBlock();
     void handleThroughOperands(MachineInstr *MI,
                                SmallVectorImpl<unsigned> &VirtDead);
     int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
     bool isLastUseOfLocalReg(MachineOperand&);
 

lib/CodeGen/RegAllocGreedy.cpp

public:
 
   /// Return the pass name.
   const char* getPassName() const override {
     return "Greedy Register Allocator";
   }
 
   /// RAGreedy analysis usage.
   void getAnalysisUsage(AnalysisUsage &AU) const override;
+  MachineFunctionProperties getSetProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
   void releaseMemory() override;
   Spiller &spiller() override { return *SpillerInstance; }
   void enqueue(LiveInterval *LI) override;
   LiveInterval *dequeue() override;
   unsigned selectOrSplit(LiveInterval&, SmallVectorImpl<unsigned>&) override;
   void aboutToRemoveInterval(LiveInterval &) override;
 
   /// Perform register allocation.

lib/CodeGen/RegAllocPBQP.cpp

public:
   /// Return the pass name.
   const char* getPassName() const override {
     return "PBQP Register Allocator";
   }
 
   /// PBQP analysis usage.
   void getAnalysisUsage(AnalysisUsage &au) const override;
 
+  MachineFunctionProperties getSetProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   /// Perform register allocation
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 private:
 
   typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
   typedef std::vector<const LiveInterval*> Node2LIMap;
   typedef std::vector<unsigned> AllowedSet;

lib/CodeGen/StackMapLivenessAnalysis.cpp

public:
 
   /// \brief Default construct and initialize the pass.
   StackMapLiveness();
 
   /// \brief Tell the pass manager which passes we depend on and what
   /// information we preserve.
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   /// \brief Calculate the liveness information for the given machine function.
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 private:
   /// \brief Performs the actual liveness calculation for the function.
   bool calculateLiveness(MachineFunction &MF);
 
   /// \brief Add the current register live set to the instruction.

lib/Target/NVPTX/NVPTXTargetMachine.cpp

void NVPTXPassConfig::addIRPasses() {
   // The following passes are known to not play well with virtual regs hanging
   // around after register allocation (which in our case, is *all* registers).
   // We explicitly disable them here.  We do, however, need some functionality
   // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
   // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
   disablePass(&PrologEpilogCodeInserterID);
   disablePass(&MachineCopyPropagationID);
   disablePass(&TailDuplicateID);
+  disablePass(&StackMapLivenessID);
+  disablePass(&LiveDebugValuesID);
+  disablePass(&PostRASchedulerID);
+  disablePass(&FuncletLayoutID);
 
   addPass(createNVVMReflectPass());
   if (getOptLevel() != CodeGenOpt::None)
     addPass(createNVPTXImageOptimizerPass());
   addPass(createNVPTXAssignValidGlobalNamesPass());
   addPass(createGenericToNVVMPass());
 
   if (getOptLevel() != CodeGenOpt::None) {

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

public:
 
   FunctionPass *createTargetRegisterAllocator(bool) override;
 
   void addIRPasses() override;
   bool addInstSelector() override;
   bool addILPOpts() override;
   void addPreRegAlloc() override;
   void addPostRegAlloc() override;
+  void addMachineLateOptimization() override;
+  bool addGCPasses() override { return false; }
   void addPreEmitPass() override;
 };
 } // end anonymous namespace
 
 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
   return TargetIRAnalysis([this](const Function &F) {
     return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
   });
if (getOptLevel() != CodeGenOpt::None)
     addPass(createWebAssemblyStoreResults());
 }
 
 void WebAssemblyPassConfig::addPostRegAlloc() {
   // TODO: The following CodeGen passes don't currently support code containing
   // virtual registers. Consider removing their restrictions and re-enabling
   // them.
   //
+
+  // Has no asserts of its own, but was not written to handle virtual regs.
+  disablePass(&ShrinkWrapID);
   // We use our own PrologEpilogInserter which is very slightly modified to
   // tolerate virtual registers.
   disablePass(&PrologEpilogCodeInserterID);
   // Fails with: should be run after register allocation.
   disablePass(&MachineCopyPropagationID);
 
   if (getOptLevel() != CodeGenOpt::None) {
     // Mark registers as representing wasm's expression stack.
     addPass(createWebAssemblyRegStackify());
 
     // Run the register coloring pass to reduce the total number of registers.
     addPass(createWebAssemblyRegColoring());
   }
 
   TargetPassConfig::addPostRegAlloc();
 
   // Run WebAssembly's version of the PrologEpilogInserter. Target-independent
   // PEI runs after PostRegAlloc and after ShrinkWrap. Putting it here will run
   // PEI before ShrinkWrap but otherwise in the same position in the order.
   addPass(createWebAssemblyPEI());
 }
 
+void WebAssemblyPassConfig::addMachineLateOptimization() {
+  disablePass(&MachineCopyPropagationID);
+  disablePass(&PostRASchedulerID);
+  TargetPassConfig::addMachineLateOptimization();
+}
+
 void WebAssemblyPassConfig::addPreEmitPass() {
   TargetPassConfig::addPreEmitPass();
 
   // Eliminate multiple-entry loops.
   addPass(createWebAssemblyFixIrreducibleControlFlow());
+  disablePass(&FuncletLayoutID);
+  disablePass(&StackMapLivenessID);
+  disablePass(&LiveDebugValuesID);
 
   // Put the CFG in structured form; insert BLOCK and LOOP markers.
   addPass(createWebAssemblyCFGStackify());
 
   // Lower br_unless into br_if.
   addPass(createWebAssemblyLowerBrUnless());
 
   // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
   addPass(createWebAssemblyRegNumbering());
 
   // Perform the very last peephole optimizations on the code.
   if (getOptLevel() != CodeGenOpt::None)
     addPass(createWebAssemblyPeephole());
 }

test/CodeGen/MIR/AArch64/machine-dead-copy.mir

 
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp  -verify-machineinstrs  -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
   define i32 @copyprop1(i32 %a, i32 %b) { ret i32 %a }
   define i32 @copyprop2(i32 %a, i32 %b) { ret i32 %a }
   define i32 @copyprop3(i32 %a, i32 %b) { ret i32 %a }
   define i32 @copyprop4(i32 %a, i32 %b) { ret i32 %a }
   declare i32 @foo(i32)
 ...
 ---
 # The first copy is dead copy which is not used.
 # CHECK-LABEL: name: copyprop1
 # CHECK: bb.0:
 # CHECK-NOT: %w20 = COPY
 name:            copyprop1
+allVRegsAllocated: true
 body:             |
   bb.0:
     liveins: %w0,  %w1
     %w20 = COPY %w1
     BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
     RET_ReallyLR implicit %w0
 ...
 ---
 # The first copy is not a dead copy which is used in the second copy after the
 # call.
 # CHECK-LABEL: name: copyprop2
 # CHECK: bb.0:
 # CHECK: %w20 = COPY
 name:            copyprop2
+allVRegsAllocated: true
 body:             |
   bb.0:
     liveins: %w0,  %w1
     %w20 = COPY %w1
     BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
     %w0 = COPY %w20
     RET_ReallyLR implicit %w0
 ...
 ---
 # Both the first and second copy are dead copies which are not used.
 # CHECK-LABEL: name: copyprop3
 # CHECK: bb.0:
 # CHECK-NOT: COPY
 name:            copyprop3
+allVRegsAllocated: true
 body:             |
   bb.0:
     liveins: %w0,  %w1
     %w20 = COPY %w1
     BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
     %w20 = COPY %w0
     RET_ReallyLR implicit %w0
 ...
 # The second copy is removed as a NOP copy, after then the first copy become
 # dead which should be removed as well.
 # CHECK-LABEL: name: copyprop4
 # CHECK: bb.0:
 # CHECK-NOT: COPY
 name:            copyprop4
+allVRegsAllocated: true
 body:             |
   bb.0:
     liveins: %w0,  %w1
     %w20 = COPY %w0
     %w0 = COPY %w20
     BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
     RET_ReallyLR implicit %w0
 ...
 

test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir

--- |
   !34 = !DILocation(line: 15, scope: !4)
 
 ...
 ---
 name:            f
 alignment:       1
 exposesReturnsTwice: false
 hasInlineAsm:    false
+allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%r0' }
   - { reg: '%r2' }
   - { reg: '%r3' }
 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', 

test/CodeGen/X86/machine-copy-prop.mir

 # the kill flag of intermediate instructions.
 # CHECK-LABEL: name: copyprop_remove_kill0
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %rdi
 # CHECK-NOT: COPY
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop_remove_kill0
+allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     NOOP implicit killed %rdi
     %rdi = COPY %rax
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The second copy is redundant and will be removed, check that we also remove
 # the kill flag of intermediate instructions.
 # CHECK-LABEL: name: copyprop_remove_kill1
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %edi
 # CHECK-NOT: COPY
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop_remove_kill1
+allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     NOOP implicit killed %edi
     %rdi = COPY %rax
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The second copy is redundant and will be removed, check that we also remove
 # the kill flag of intermediate instructions.
 # CHECK-LABEL: name: copyprop_remove_kill2
 # CHECK: bb.0:
 # CHECK-NEXT: %ax = COPY %di
 # CHECK-NEXT: NOOP implicit %rdi
 # CHECK-NOT: COPY
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop_remove_kill2
+allVRegsAllocated: true
 body: |
   bb.0:
     %ax = COPY %di
     NOOP implicit killed %rdi
     %di = COPY %ax
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The second copy is redundant; the call preserves the source and dest register.
 # CHECK-LABEL: name: copyprop0
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64_rt_mostregs
 # CHECK-NEXT: NOOP implicit %edi
 # CHECK-NOT: COPY
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop0
+allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     CALL64pcrel32 @foo, csr_64_rt_mostregs
     NOOP implicit killed %edi
     %rdi = COPY %rax
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The 2nd copy is redundant; The call preserves the source and dest register.
 # CHECK-LABEL: name: copyprop1
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %rax
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop1
+allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     NOOP implicit killed %rax
     %rax = COPY %rdi
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # CHECK-LABEL: name: copyprop2
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %ax
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64_rt_mostregs
 # CHECK-NOT: %rax = COPY %rdi
 # CHECK-NEXT: NOOP implicit %rax, implicit %rdi
 name: copyprop2
+allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rdi
     NOOP implicit killed %ax
     CALL64pcrel32 @foo, csr_64_rt_mostregs
     %rax = COPY %rdi
     NOOP implicit %rax, implicit %rdi
 ...
 ---
 # The second copy is not redundant if the source register (%rax) is clobbered
 # even if the dest (%rbp) is not.
 # CHECK-LABEL: name: nocopyprop0
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rbp
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
 # CHECK-NEXT: %rbp = COPY %rax
 # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
 name: nocopyprop0
+allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rbp
     CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
     %rbp = COPY %rax
     NOOP implicit %rax, implicit %rbp
 ...
 ---
 # The second copy is not redundant if the dest register (%rax) is clobbered
 # even if the source (%rbp) is not.
 # CHECK-LABEL: name: nocopyprop1
 # CHECK: bb.0:
 # CHECK-NEXT: %rbp = COPY %rax
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
 # CHECK-NEXT: %rax = COPY %rbp
 # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
 name: nocopyprop1
+allVRegsAllocated: true
 body: |
   bb.0:
     %rbp = COPY %rax
     CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
     %rax = COPY %rbp
     NOOP implicit %rax, implicit %rbp
 ...
 ---
 # The second copy is not redundant if the source register (%rax) is clobbered
 # even if the dest (%rbp) is not.
 # CHECK-LABEL: name: nocopyprop2
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rbp
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
 # CHECK-NEXT: %rax = COPY %rbp
 # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
 name: nocopyprop2
+allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rbp
     CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
     %rax = COPY %rbp
     NOOP implicit %rax, implicit %rbp
 ...
 ---
 # The second copy is not redundant if the dest register (%rax) is clobbered
 # even if the source (%rbp) is not.
 # CHECK-LABEL: name: nocopyprop3
 # CHECK: bb.0:
 # CHECK-NEXT: %rbp = COPY %rax
 # CHECK-NEXT: CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
 # CHECK-NEXT: %rbp = COPY %rax
 # CHECK-NEXT: NOOP implicit %rax, implicit %rbp
 name: nocopyprop3
+allVRegsAllocated: true
 body: |
   bb.0:
     %rbp = COPY %rax
     CALL64pcrel32 @foo, csr_64, implicit %rax, implicit %rbp
     %rbp = COPY %rax
     NOOP implicit %rax, implicit %rbp
 ...
 ---
 # A reserved register may change its value so the 2nd copy is not redundant.
 # CHECK-LABEL: name: nocopyprop4
 # CHECK: bb.0:
 # CHECK-NEXT: %rax = COPY %rip
 # CHECK-NEXT: NOOP implicit %rax
 # CHECK-NEXT: %rax = COPY %rip
 # CHECK-NEXT: NOOP implicit %rax
 name: nocopyprop4
+allVRegsAllocated: true
 body: |
   bb.0:
     %rax = COPY %rip
     NOOP implicit %rax
     %rax = COPY %rip
     NOOP implicit %rax
 ...
 ---
 # Writing to a reserved register may have additional effects (slightly illegal
 # testcase because writing to %rip like this should make the instruction a jump)
 # CHECK-LABEL: name: nocopyprop5
 # CHECK: bb.0:
 # CHECK-NEXT: %rip = COPY %rax
 # CHECK-NEXT: %rip = COPY %rax
 name: nocopyprop5
+allVRegsAllocated: true
 body: |
   bb.0:
     %rip = COPY %rax
     %rip = COPY %rax
 ...

test/DebugInfo/MIR/X86/live-debug-values-3preds.mir

--- |
   !50 = !DILocation(line: 17, column: 3, scope: !4)
 
 ...
 ---
 name:            add
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    false
+allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%edi' }
   - { reg: '%esi' }
   - { reg: '%edx' }
   - { reg: '%ecx' }

test/DebugInfo/MIR/X86/live-debug-values.mir

--- |
   !47 = !DILocation(line: 20, column: 3, scope: !4)
 
 ...
 ---
 name:            main
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    false
+allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%edi' }
   - { reg: '%rsi' }
 calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx', 
                         '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',