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Differential D16888

[mips] Addition of a third operand to the instructions [d]div, [d]divu
ClosedPublic

Authored by obucina on Feb 4 2016, 8:20 AM.

Details

Reviewers
dsanders
vkalintiris
zoran.jovanovic
Commits
rL269636: [mips] Addition of a third operand to the instructions [d]div, [d]divu
Summary

Related to http://reviews.llvm.org/D15772

Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register.

Diff Detail

Event Timeline

obucina updated this revision to Diff 46921.Feb 4 2016, 8:20 AM
obucina retitled this revision from to [mips] Addition of a third operand to the instructions [d]div, [d]divu .
obucina updated this object.
obucina added reviewers: dsanders, zoran.jovanovic.
obucina added a subscriber: llvm-commits.
Herald added a reviewer: vkalintiris. · View Herald TranscriptFeb 4 2016, 8:20 AM
Herald added a subscriber: dsanders. · View Herald Transcript
dsanders requested changes to this revision.Feb 12 2016, 9:27 AM
dsanders edited edge metadata.

Could you make the summary more like a commit message?

I don't see any code to handle things like 'ddiv $zero, $4, $5' but it's possible that the real instruction has priority over the macro because $zero is more specific. Could you add tests for 'ddiv $zero, $4, $5' and check that it only expands to a single 'ddiv $zero, $4, $5' instruction? Similarly for ddivu/dmod/dmodu

This revision now requires changes to proceed.Feb 12 2016, 9:27 AM
dsanders mentioned this in D16889: [mips] Addition of the immediate cases for the instructions [d]div, [d]divu.Feb 12 2016, 9:31 AM
obucina updated this revision to Diff 48932.Feb 24 2016, 7:10 AM
obucina updated this object.
obucina edited edge metadata.

Review changes applied. Added additional test for case when destination register is zero register.

obucina updated this revision to Diff 49172.Feb 26 2016, 4:44 AM
obucina edited edge metadata.
obucina added a comment.Mar 15 2016, 8:08 AM

Ping... We need review on this, since it is prerequisite for http://reviews.llvm.org/D16889

obucina mentioned this in D17036: [mips] Addition of the [d]rem and [d]remu instructions.Mar 15 2016, 9:03 AM
dsanders accepted this revision.Mar 15 2016, 9:17 AM
dsanders edited edge metadata.

With the indentation and missing predicates fixed it will LGTM

lib/Target/Mips/MipsInstrInfo.td
2062–2063

Indentation is off by one. There are similar cases below.

2069

The MipsInstAlias's need predicates too. Without them, the alias is still available for all targets.

Likewise below

2070

Indentation. The operand should align to the first one on the previous line:

(SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
           GPR32Opnd:$rs)

There are similar cases below.

This revision is now accepted and ready to land.Mar 15 2016, 9:17 AM
obucina updated this revision to Diff 52042.Mar 30 2016, 6:11 AM
obucina edited edge metadata.

We fixed indentation and we added predicates to the MipsInstAlias's.
This led to changes in the macro-div-bad.s, macro-divu-bad.s, macro-ddiv-bad.s and macro-ddivu-bad.s test cases.

Herald added a subscriber: sdardis. · View Herald TranscriptMar 30 2016, 6:11 AM
obucina marked 3 inline comments as done.Mar 30 2016, 6:12 AM
Closed by commit rL269636: [mips] Addition of a third operand to the instructions [d]div, [d]divu (authored by zjovanovic). · Explain WhyMay 16 2016, 2:04 AM
This revision was automatically updated to reflect the committed changes.
Eugene.Zelenko added a child revision: D16889: [mips] Addition of the immediate cases for the instructions [d]div, [d]divu.Sep 26 2016, 2:10 PM

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
17 lines
39 lines
test/
MC/
Mips/
22 lines
41 lines
16 lines
39 lines
2 lines
39 lines
2 lines
65 lines

Diff 52042

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 992 Lines • ▼ Show 20 Lines
ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
Instructions); Instructions);
return false; return false;
} }
bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions, SmallVectorImpl<MCInst> &Instructions,
const bool IsMips64, const bool Signed) { const bool IsMips64, const bool Signed) {
if (hasMips32r6()) {
Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
return false;
}
warnIfNoMacro(IDLoc); warnIfNoMacro(IDLoc);
const MCOperand &RsRegOp = Inst.getOperand(0); const MCOperand &RdRegOp = Inst.getOperand(0);
assert(RdRegOp.isReg() && "expected register operand kind");
unsigned RdReg = RdRegOp.getReg();
const MCOperand &RsRegOp = Inst.getOperand(1);
assert(RsRegOp.isReg() && "expected register operand kind"); assert(RsRegOp.isReg() && "expected register operand kind");
unsigned RsReg = RsRegOp.getReg(); unsigned RsReg = RsRegOp.getReg();
const MCOperand &RtRegOp = Inst.getOperand(1); const MCOperand &RtRegOp = Inst.getOperand(2);
assert(RtRegOp.isReg() && "expected register operand kind"); assert(RtRegOp.isReg() && "expected register operand kind");
unsigned RtReg = RtRegOp.getReg(); unsigned RtReg = RtRegOp.getReg();
unsigned DivOp; unsigned DivOp;
unsigned ZeroReg; unsigned ZeroReg;
if (IsMips64) { if (IsMips64) {
DivOp = Signed ? Mips::DSDIV : Mips::DUDIV; DivOp = Signed ? Mips::DSDIV : Mips::DUDIV;
ZeroReg = Mips::ZERO_64; ZeroReg = Mips::ZERO_64;
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
} }
emitRR(DivOp, RsReg, RtReg, IDLoc, Instructions); emitRR(DivOp, RsReg, RtReg, IDLoc, Instructions);
if (!UseTraps) if (!UseTraps)
emitII(Mips::BREAK, 0x7, 0, IDLoc, Instructions); emitII(Mips::BREAK, 0x7, 0, IDLoc, Instructions);
if (!Signed) { if (!Signed) {
emitR(Mips::MFLO, RsReg, IDLoc, Instructions); emitR(Mips::MFLO, RdReg, IDLoc, Instructions);
return false; return false;
} }
unsigned ATReg = getATReg(IDLoc); unsigned ATReg = getATReg(IDLoc);
if (!ATReg) if (!ATReg)
return true; return true;
emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, Instructions); emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, Instructions);
Show All 11 Lines
if (UseTraps) if (UseTraps)
emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, Instructions); emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, Instructions);
else { else {
// Branch to the mflo instruction. // Branch to the mflo instruction.
emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Instructions); emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Instructions);
emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Instructions); emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Instructions);
emitII(Mips::BREAK, 0x6, 0, IDLoc, Instructions); emitII(Mips::BREAK, 0x6, 0, IDLoc, Instructions);
} }
emitR(Mips::MFLO, RsReg, IDLoc, Instructions); emitR(Mips::MFLO, RdReg, IDLoc, Instructions);
return false; return false;
} }
bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
SMLoc IDLoc, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) { SmallVectorImpl<MCInst> &Instructions) {
assert(Inst.getNumOperands() == 3 && "Invalid operand count"); assert(Inst.getNumOperands() == 3 && "Invalid operand count");
▲ Show 20 Lines • Show All 992 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 992 Lines • ▼ Show 20 Lines
def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6; def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
// FIXME: Predicates are removed because instructions are matched regardless of // FIXME: Predicates are removed because instructions are matched regardless of
// predicates, because PredicateControl was not in the hierarchy. This was // predicates, because PredicateControl was not in the hierarchy. This was
// done to emit more precise error message from expansion function. // done to emit more precise error message from expansion function.
// Once the tablegen-erated errors are made better, this needs to be fixed and // Once the tablegen-erated errors are made better, this needs to be fixed and
// predicates needs to be restored. // predicates needs to be restored.
def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), def SDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
"div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6; (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
"div\t$rd, $rs, $rt">,
dsandersUnsubmitted
Done
ReplyInline Actions

Indentation is off by one. There are similar cases below.

dsanders: Indentation is off by one. There are similar cases below.
def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), ISA_MIPS1_NOT_32R6_64R6;
"divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6; def UDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), "divu\t$rd, $rs, $rt">,
"ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6; ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"div $rt, $rs", (SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
dsandersUnsubmitted
Done
ReplyInline Actions

The MipsInstAlias's need predicates too. Without them, the alias is still available for all targets.

Likewise below

dsanders: The MipsInstAlias's need predicates too. Without them, the alias is still available for all…
def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), GPR32Opnd:$rs), 0>,
dsandersUnsubmitted
Done
ReplyInline Actions

Indentation. The operand should align to the first one on the previous line:

(SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
           GPR32Opnd:$rs)

There are similar cases below.

dsanders: Indentation. The operand should align to the first one on the previous line: (SDivMacro…
"ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6; ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
GPR32Opnd:$rs), 0>,
ISA_MIPS1_NOT_32R6_64R6;
def DSDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
"ddiv\t$rd, $rs, $rt">,
ISA_MIPS64_NOT_64R6;
def DUDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
"ddivu\t$rd, $rs, $rt">,
ISA_MIPS64_NOT_64R6;
def : MipsInstAlias<"ddiv $rt, $rs", (DSDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
GPR32Opnd:$rs), 0>,
ISA_MIPS64_NOT_64R6;
def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
GPR32Opnd:$rs), 0>,
ISA_MIPS64_NOT_64R6;
def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
"ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
"ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
▲ Show 20 Lines • Show All 269 Lines • Show Last 20 Lines

test/MC/Mips/macro-ddiv-bad.s

# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \ # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \ # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6 # RUN: FileCheck %s --check-prefix=MIPS64-NOT-R6
.text .text
ddiv $25, $11 ddivu $25, $11
# R6: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ddiv $25, $0 ddivu $25, $0
# NOT-R6: :[[@LINE-1]]:3: warning: division by zero # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: division by zero
ddiv $0,$0 ddivu $0,$0
# NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero

test/MC/Mips/macro-ddiv.s

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# CHECK-NOTRAP: bne $zero, $1, 8 # encoding: [0x14,0x01,0x00,0x02] # CHECK-NOTRAP: bne $zero, $1, 8 # encoding: [0x14,0x01,0x00,0x02]
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00] # CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d] # CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
# CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12] # CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
ddiv $0,$0 ddiv $0,$0
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d] # CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
ddiv $4,$5,$6
# CHECK-NOTRAP: bne $6, $zero, 8 # encoding: [0x14,0xc0,0x00,0x02]
# CHECK-NOTRAP: ddiv $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1e]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
# CHECK-NOTRAP: bne $6, $1, 20 # encoding: [0x14,0xc1,0x00,0x05]
# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
# CHECK-NOTRAP: bne $5, $1, 8 # encoding: [0x14,0xa1,0x00,0x02]
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
ddiv $4,$5,$0
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
ddiv $4,$0,$0
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
ddiv $0, $4, $5
# CHECK-NOTRAP: ddiv $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1e]
ddiv $25,$11 ddiv $25,$11
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4] # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
# CHECK-TRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e] # CHECK-TRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff] # CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
# CHECK-TRAP: bne $11, $1, 12 # encoding: [0x15,0x61,0x00,0x03] # CHECK-TRAP: bne $11, $1, 12 # encoding: [0x15,0x61,0x00,0x03]
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] # CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc] # CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
# CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4] # CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
Show All 19 Lines
# CHECK-TRAP: bne $9, $1, 12 # encoding: [0x15,0x21,0x00,0x03] # CHECK-TRAP: bne $9, $1, 12 # encoding: [0x15,0x21,0x00,0x03]
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] # CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc] # CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
# CHECK-TRAP: teq $zero, $1, 6 # encoding: [0x00,0x01,0x01,0xb4] # CHECK-TRAP: teq $zero, $1, 6 # encoding: [0x00,0x01,0x01,0xb4]
# CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12] # CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
ddiv $0,$0 ddiv $0,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4] # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
ddiv $4,$5,$6
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
# CHECK-TRAP: ddiv $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1e]
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
# CHECK-TRAP: bne $6, $1, 12 # encoding: [0x14,0xc1,0x00,0x03]
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
# CHECK-TRAP: teq $5, $1, 6 # encoding: [0x00,0xa1,0x01,0xb4]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
ddiv $4,$5,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
ddiv $4,$0,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
ddiv $0, $4, $5
# CHECK-TRAP: ddiv $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1e]

test/MC/Mips/macro-ddivu-bad.s

# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \ # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \ # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6 # RUN: FileCheck %s --check-prefix=MIPS64-NOT-R6
.text .text
ddivu $25, $11 ddivu $25, $11
# R6: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ddivu $25, $0 ddivu $25, $0
# NOT-R6: :[[@LINE-1]]:3: warning: division by zero # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: division by zero
ddivu $0,$0 ddivu $0,$0
# NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero

test/MC/Mips/macro-ddivu.s

Show All 27 Lines
# CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12] # CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
ddivu $0,$0 ddivu $0,$0
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02] # CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
# CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f] # CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d] # CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12] # CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
ddivu $4,$5,$6
# CHECK-NOTRAP: bne $6, $zero, 8 # encoding: [0x14,0xc0,0x00,0x02]
# CHECK-NOTRAP: ddivu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1f]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
ddivu $4,$5,$0
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
# CHECK-NOTRAP: ddivu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1f]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
ddivu $4,$0,$0
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
# CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
ddivu $0, $4, $5
# CHECK-NOTRAP: ddivu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1f]
ddivu $25, $11 ddivu $25, $11
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4] # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
# CHECK-TRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f] # CHECK-TRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12] # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
ddivu $24,$12 ddivu $24,$12
# CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4] # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
# CHECK-TRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f] # CHECK-TRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12] # CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
ddivu $25,$0 ddivu $25,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4] # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f] # CHECK-TRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f]
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12] # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
ddivu $0,$9 ddivu $0,$9
# CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4] # CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4]
# CHECK-TRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f] # CHECK-TRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
# CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12] # CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
ddivu $0,$0 ddivu $0,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4] # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f] # CHECK-TRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
# CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12] # CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
ddivu $4,$5,$6
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
# CHECK-TRAP: ddivu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1f]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
ddivu $4,$5,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: ddivu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1f]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
ddivu $4,$0,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
ddivu $0, $4, $5
# CHECK-TRAP: ddivu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1f]

test/MC/Mips/macro-div-bad.s

# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \ # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6 # RUN: FileCheck %s --check-prefix=R6
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \ # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6 # RUN: FileCheck %s --check-prefix=R6
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6 # RUN: FileCheck %s --check-prefix=NOT-R6
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6 # RUN: FileCheck %s --check-prefix=NOT-R6
.text .text
div $25, $11 div $25, $11
# R6: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
div $25, $0 div $25, $0
# NOT-R6: :[[@LINE-1]]:3: warning: division by zero # NOT-R6: :[[@LINE-1]]:3: warning: division by zero
div $0,$0 div $0,$0
# NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero # NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero

test/MC/Mips/macro-div.s

Show All 30 Lines
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d] # CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
div $0,$9 div $0,$9
# CHECK-NOTRAP: div $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1a] # CHECK-NOTRAP: div $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1a]
div $0,$0 div $0,$0
# CHECK-NOTRAP: div $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1a] # CHECK-NOTRAP: div $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1a]
div $4,$5,$6
# CHECK-NOTRAP: bnez $6, 8 # encoding: [0x14,0xc0,0x00,0x02]
# CHECK-NOTRAP: div $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1a]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
# CHECK-NOTRAP: bne $6, $1, 16 # encoding: [0x14,0xc1,0x00,0x04]
# CHECK-NOTRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
# CHECK-NOTRAP: bne $5, $1, 8 # encoding: [0x14,0xa1,0x00,0x02]
# CHECK-NOTRAP: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
div $4,$5,$0
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
div $4,$0,$0
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
div $0, $4, $5
# CHECK-NOTRAP: div $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1a]
div $25, $11 div $25, $11
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4] # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
# CHECK-TRAP: div $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1a] # CHECK-TRAP: div $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1a]
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff] # CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
# CHECK-TRAP: bne $11, $1, 8 # encoding: [0x15,0x61,0x00,0x02] # CHECK-TRAP: bne $11, $1, 8 # encoding: [0x15,0x61,0x00,0x02]
# CHECK-TRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00] # CHECK-TRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
# CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4] # CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12] # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
Show All 10 Lines# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
div $25,$0 div $25,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4] # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
div $0,$9 div $0,$9
# CHECK-TRAP: div $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1a] # CHECK-TRAP: div $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1a]
div $0,$0 div $0,$0
# CHECK-TRAP: div $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1a] # CHECK-TRAP: div $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1a]
div $4,$5,$6
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
# CHECK-TRAP: div $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1a]
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
# CHECK-TRAP: bne $6, $1, 8 # encoding: [0x14,0xc1,0x00,0x02]
# CHECK-TRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
# CHECK-TRAP: teq $5, $1, 6 # encoding: [0x00,0xa1,0x01,0xb4]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
div $4,$5,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
div $4,$0,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
div $0, $4, $5
# CHECK-TRAP: div $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1a]
No newline at end of file

test/MC/Mips/macro-divu-bad.s

# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \ # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6 # RUN: FileCheck %s --check-prefix=R6
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \ # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6 # RUN: FileCheck %s --check-prefix=R6
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6 # RUN: FileCheck %s --check-prefix=NOT-R6
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6 # RUN: FileCheck %s --check-prefix=NOT-R6
.text .text
divu $25, $11 divu $25, $11
# R6: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
divu $25, $0 divu $25, $0
# NOT-R6: :[[@LINE-1]]:3: warning: division by zero # NOT-R6: :[[@LINE-1]]:3: warning: division by zero
divu $0,$0 divu $0,$0
# NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero # NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero

test/MC/Mips/macro-divu.s

Show All 21 Lines
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12] # CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
divu $0,$9 divu $0,$9
# CHECK-NOTRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b] # CHECK-NOTRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
divu $0,$0 divu $0,$0
# CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b] # CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
divu $4,$5,$6
# CHECK-NOTRAP: bnez $6, 8 # encoding: [0x14,0xc0,0x00,0x02]
# CHECK-NOTRAP: divu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1b]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $4,$5,$0
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
# CHECK-NOTRAP: divu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1b]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $4,$0,$0
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
# CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $0, $4, $5
# CHECK-NOTRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]
divu $25, $11 divu $25, $11
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4] # CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
# CHECK-TRAP: divu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1b] # CHECK-TRAP: divu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1b]
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12] # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
divu $24,$12 divu $24,$12
# CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4] # CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
# CHECK-TRAP: divu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1b] # CHECK-TRAP: divu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1b]
# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12] # CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
divu $25,$0 divu $25,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4] # CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b] # CHECK-TRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b]
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12] # CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
divu $0,$9 divu $0,$9
# CHECK-TRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b] # CHECK-TRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
divu $0,$0 divu $0,$0
# CHECK-TRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b] # CHECK-TRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
divu $4,$5,$6
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
# CHECK-TRAP: divu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1b]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $4,$5,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: divu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1b]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $4,$0,$0
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
# CHECK-TRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
divu $0, $4, $5
# CHECK-TRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]
No newline at end of file