[mips] Addition of a third operand to the instructions [d]div, [d]divu

[obucina]

Summary

Related to http://reviews.llvm.org/D15772

Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register.

[dsanders]

Could you make the summary more like a commit message?

I don't see any code to handle things like 'ddiv $zero, $4, $5' but it's possible that the real instruction has priority over the macro because $zero is more specific. Could you add tests for 'ddiv $zero, $4, $5' and check that it only expands to a single 'ddiv $zero, $4, $5' instruction? Similarly for ddivu/dmod/dmodu

[obucina]

Review changes applied. Added additional test for case when destination register is zero register.

[obucina]

Ping... We need review on this, since it is prerequisite for http://reviews.llvm.org/D16889

[dsanders]

With the indentation and missing predicates fixed it will LGTM

lib/Target/Mips/MipsInstrInfo.td

2062–2063

Indentation is off by one. There are similar cases below.

2069

The MipsInstAlias's need predicates too. Without them, the alias is still available for all targets.

Likewise below

2070

Indentation. The operand should align to the first one on the previous line:

(SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
           GPR32Opnd:$rs)

There are similar cases below.

[obucina]

We fixed indentation and we added predicates to the MipsInstAlias's.
This led to changes in the macro-div-bad.s, macro-divu-bad.s, macro-ddiv-bad.s and macro-ddivu-bad.s test cases.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

                               const bool IsMips64, const bool Signed) {
   if (hasMips32r6()) {
     Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
     return false;
   }
 
   warnIfNoMacro(IDLoc);
 
-  const MCOperand &RsRegOp = Inst.getOperand(0);
+  const MCOperand &RdRegOp = Inst.getOperand(0);
+  assert(RdRegOp.isReg() && "expected register operand kind");
+  unsigned RdReg = RdRegOp.getReg();
+
+  const MCOperand &RsRegOp = Inst.getOperand(1);
   assert(RsRegOp.isReg() && "expected register operand kind");
   unsigned RsReg = RsRegOp.getReg();
 
-  const MCOperand &RtRegOp = Inst.getOperand(1);
+  const MCOperand &RtRegOp = Inst.getOperand(2);
   assert(RtRegOp.isReg() && "expected register operand kind");
   unsigned RtReg = RtRegOp.getReg();
   unsigned DivOp;
   unsigned ZeroReg;
 
   if (IsMips64) {
     DivOp = Signed ? Mips::DSDIV : Mips::DUDIV;
     ZeroReg = Mips::ZERO_64;

   }
 
   emitRR(DivOp, RsReg, RtReg, IDLoc, Instructions);
 
   if (!UseTraps)
     emitII(Mips::BREAK, 0x7, 0, IDLoc, Instructions);
 
   if (!Signed) {
-    emitR(Mips::MFLO, RsReg, IDLoc, Instructions);
+    emitR(Mips::MFLO, RdReg, IDLoc, Instructions);
     return false;
   }
 
   unsigned ATReg = getATReg(IDLoc);
   if (!ATReg)
     return true;
 
   emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, Instructions);

   if (UseTraps)
     emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, Instructions);
   else {
     // Branch to the mflo instruction.
     emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Instructions);
     emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Instructions);
     emitII(Mips::BREAK, 0x6, 0, IDLoc, Instructions);
   }
-  emitR(Mips::MFLO, RsReg, IDLoc, Instructions);
+  emitR(Mips::MFLO, RdReg, IDLoc, Instructions);
   return false;
 }
 
 bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
                                 SMLoc IDLoc,
                                 SmallVectorImpl<MCInst> &Instructions) {
 
   assert(Inst.getNumOperands() == 3 && "Invalid operand count");

lib/Target/Mips/MipsInstrInfo.td

 def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
 
 // FIXME: Predicates are removed because instructions are matched regardless of
 // predicates, because PredicateControl was not in the hierarchy. This was
 // done to emit more precise error message from expansion function.
 // Once the tablegen-erated errors are made better, this needs to be fixed and
 // predicates needs to be restored.
 
-def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                  "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
-
-def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                  "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
-
-def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                   "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
-
-def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                   "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
+def SDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                   (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                   "div\t$rd, $rs, $rt">,
+                ISA_MIPS1_NOT_32R6_64R6;
+def UDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                   (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                   "divu\t$rd, $rs, $rt">,
+                ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"div $rt, $rs", (SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                     GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                      GPR32Opnd:$rs), 0>;
+
+def DSDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                    (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                    "ddiv\t$rd, $rs, $rt">,
+                 ISA_MIPS64_NOT_64R6;
+def DUDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                    (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                    "ddivu\t$rd, $rs, $rt">,
+                 ISA_MIPS64_NOT_64R6;
+def : MipsInstAlias<"ddiv $rt, $rs", (DSDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                      GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                       GPR32Opnd:$rs), 0>;
 
 def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
                             "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 
 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
                              "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 
 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),

test/MC/Mips/macro-ddiv.s

 # CHECK-NOTRAP: bne $zero, $1, 8          # encoding: [0x14,0x01,0x00,0x02]
 # CHECK-NOTRAP: sll $zero, $zero, 0       # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-NOTRAP: break 6                   # encoding: [0x00,0x06,0x00,0x0d]
 # CHECK-NOTRAP: mflo $zero                # encoding: [0x00,0x00,0x00,0x12]
 
   ddiv $0,$0
 # CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
 
+  ddiv  $4,$5,$6
+# CHECK-NOTRAP: bne $6, $zero, 8          # encoding: [0x14,0xc0,0x00,0x02]
+# CHECK-NOTRAP: ddiv $zero, $5, $6        # encoding: [0x00,0xa6,0x00,0x1e]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: addiu $1, $zero, -1       # encoding: [0x24,0x01,0xff,0xff]
+# CHECK-NOTRAP: bne $6, $1, 20            # encoding: [0x14,0xc1,0x00,0x05]
+# CHECK-NOTRAP: addiu $1, $zero, 1        # encoding: [0x24,0x01,0x00,0x01]
+# CHECK-NOTRAP: dsll32 $1, $1, 31         # encoding: [0x00,0x01,0x0f,0xfc]
+# CHECK-NOTRAP: bne $5, $1, 8             # encoding: [0x14,0xa1,0x00,0x02]
+# CHECK-NOTRAP: sll $zero, $zero, 0       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-NOTRAP: break 6                   # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  ddiv  $4,$5,$0
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+
+  ddiv  $4,$0,$0
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+
+  ddiv $0, $4, $5
+# CHECK-NOTRAP: ddiv $zero, $4, $5        # encoding: [0x00,0x85,0x00,0x1e]
+
   ddiv $25,$11
 # CHECK-TRAP: teq $11, $zero, 7           # encoding: [0x01,0x60,0x01,0xf4]
 # CHECK-TRAP: ddiv $zero, $25, $11        # encoding: [0x03,0x2b,0x00,0x1e]
 # CHECK-TRAP: addiu $1, $zero, -1         # encoding: [0x24,0x01,0xff,0xff]
 # CHECK-TRAP: bne $11, $1, 12             # encoding: [0x15,0x61,0x00,0x03]
 # CHECK-TRAP: addiu $1, $zero, 1          # encoding: [0x24,0x01,0x00,0x01]
 # CHECK-TRAP: dsll32 $1, $1, 31           # encoding: [0x00,0x01,0x0f,0xfc]
 # CHECK-TRAP: teq $25, $1, 6              # encoding: [0x03,0x21,0x01,0xb4]

 # CHECK-TRAP: bne $9, $1, 12              # encoding: [0x15,0x21,0x00,0x03]
 # CHECK-TRAP: addiu $1, $zero, 1          # encoding: [0x24,0x01,0x00,0x01]
 # CHECK-TRAP: dsll32 $1, $1, 31           # encoding: [0x00,0x01,0x0f,0xfc]
 # CHECK-TRAP: teq $zero, $1, 6            # encoding: [0x00,0x01,0x01,0xb4]
 # CHECK-TRAP: mflo $zero                  # encoding: [0x00,0x00,0x00,0x12]
 
   ddiv $0,$0
 # CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  ddiv  $4,$5,$6
+# CHECK-TRAP: teq $6, $zero, 7            # encoding: [0x00,0xc0,0x01,0xf4]
+# CHECK-TRAP: ddiv $zero, $5, $6          # encoding: [0x00,0xa6,0x00,0x1e]
+# CHECK-TRAP: addiu $1, $zero, -1         # encoding: [0x24,0x01,0xff,0xff]
+# CHECK-TRAP: bne $6, $1, 12              # encoding: [0x14,0xc1,0x00,0x03]
+# CHECK-TRAP: addiu $1, $zero, 1          # encoding: [0x24,0x01,0x00,0x01]
+# CHECK-TRAP: dsll32 $1, $1, 31           # encoding: [0x00,0x01,0x0f,0xfc]
+# CHECK-TRAP: teq $5, $1, 6               # encoding: [0x00,0xa1,0x01,0xb4]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  ddiv  $4,$5,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  ddiv  $4,$0,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  ddiv $0, $4, $5
+# CHECK-TRAP: ddiv $zero, $4, $5          # encoding: [0x00,0x85,0x00,0x1e]

test/MC/Mips/macro-ddivu.s

 # CHECK-NOTRAP: mflo $zero                # encoding: [0x00,0x00,0x00,0x12]
 
   ddivu $0,$0
 # CHECK-NOTRAP: bne $zero, $zero, 8       # encoding: [0x14,0x00,0x00,0x02]
 # CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
 # CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
 # CHECK-NOTRAP: mflo $zero                # encoding: [0x00,0x00,0x00,0x12]
 
+  ddivu  $4,$5,$6
+# CHECK-NOTRAP: bne $6, $zero, 8          # encoding: [0x14,0xc0,0x00,0x02]
+# CHECK-NOTRAP: ddivu $zero, $5, $6       # encoding: [0x00,0xa6,0x00,0x1f]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $4,$5,$0
+# CHECK-NOTRAP: bne $zero, $zero, 8       # encoding: [0x14,0x00,0x00,0x02]
+# CHECK-NOTRAP: ddivu $zero, $5, $zero    # encoding: [0x00,0xa0,0x00,0x1f]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $4,$0,$0
+# CHECK-NOTRAP: bne $zero, $zero, 8       # encoding: [0x14,0x00,0x00,0x02]
+# CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $0, $4, $5
+# CHECK-NOTRAP: ddivu $zero, $4, $5       # encoding: [0x00,0x85,0x00,0x1f]
+
   ddivu $25, $11
 # CHECK-TRAP: teq $11, $zero, 7           # encoding: [0x01,0x60,0x01,0xf4]
 # CHECK-TRAP: ddivu $zero, $25, $11       # encoding: [0x03,0x2b,0x00,0x1f]
 # CHECK-TRAP: mflo $25                    # encoding: [0x00,0x00,0xc8,0x12]
 
   ddivu $24,$12
 # CHECK-TRAP: teq $12, $zero, 7           # encoding: [0x01,0x80,0x01,0xf4]
 # CHECK-TRAP: ddivu $zero, $24, $12       # encoding: [0x03,0x0c,0x00,0x1f]
 # CHECK-TRAP: mflo $24                    # encoding: [0x00,0x00,0xc0,0x12]
 
   ddivu $25,$0
 # CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
 # CHECK-TRAP: ddivu $zero, $25, $zero     # encoding: [0x03,0x20,0x00,0x1f]
 # CHECK-TRAP: mflo $25                    # encoding: [0x00,0x00,0xc8,0x12]
 
   ddivu $0,$9
 # CHECK-TRAP: teq $9, $zero, 7            # encoding: [0x01,0x20,0x01,0xf4]
 # CHECK-TRAP: ddivu $zero, $zero, $9      # encoding: [0x00,0x09,0x00,0x1f]
 # CHECK-TRAP: mflo $zero                  # encoding: [0x00,0x00,0x00,0x12]
 
   ddivu $0,$0
 # CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
 # CHECK-TRAP: ddivu $zero, $zero, $zero   # encoding: [0x00,0x00,0x00,0x1f]
 # CHECK-TRAP: mflo $zero                  # encoding: [0x00,0x00,0x00,0x12]
+
+  ddivu  $4,$5,$6
+# CHECK-TRAP: teq $6, $zero, 7            # encoding: [0x00,0xc0,0x01,0xf4]
+# CHECK-TRAP: ddivu $zero, $5, $6         # encoding: [0x00,0xa6,0x00,0x1f]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $4,$5,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+# CHECK-TRAP: ddivu $zero, $5, $zero      # encoding: [0x00,0xa0,0x00,0x1f]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $4,$0,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+# CHECK-TRAP: ddivu $zero, $zero, $zero   # encoding: [0x00,0x00,0x00,0x1f]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $0, $4, $5
+# CHECK-TRAP: ddivu $zero, $4, $5         # encoding: [0x00,0x85,0x00,0x1f]

test/MC/Mips/macro-div.s

 # CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
 
   div $0,$9
 # CHECK-NOTRAP: div $zero, $zero, $9      # encoding: [0x00,0x09,0x00,0x1a]
 
   div $0,$0
 # CHECK-NOTRAP: div $zero, $zero, $zero   # encoding: [0x00,0x00,0x00,0x1a]
 
+  div  $4,$5,$6
+# CHECK-NOTRAP: bnez $6, 8                # encoding: [0x14,0xc0,0x00,0x02]
+# CHECK-NOTRAP: div $zero, $5, $6         # encoding: [0x00,0xa6,0x00,0x1a]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: addiu $1, $zero, -1       # encoding: [0x24,0x01,0xff,0xff]
+# CHECK-NOTRAP: bne $6, $1, 16            # encoding: [0x14,0xc1,0x00,0x04]
+# CHECK-NOTRAP: lui $1, 32768             # encoding: [0x3c,0x01,0x80,0x00]
+# CHECK-NOTRAP: bne $5, $1, 8             # encoding: [0x14,0xa1,0x00,0x02]
+# CHECK-NOTRAP: nop                       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-NOTRAP: break 6                   # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  div  $4,$5,$0
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+
+  div  $4,$0,$0
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+
+  div $0, $4, $5
+# CHECK-NOTRAP: div $zero, $4, $5         # encoding: [0x00,0x85,0x00,0x1a]
+
   div $25, $11
 # CHECK-TRAP: teq $11, $zero, 7           # encoding: [0x01,0x60,0x01,0xf4]
 # CHECK-TRAP: div $zero, $25, $11         # encoding: [0x03,0x2b,0x00,0x1a]
 # CHECK-TRAP: addiu $1, $zero, -1         # encoding: [0x24,0x01,0xff,0xff]
 # CHECK-TRAP: bne $11, $1, 8              # encoding: [0x15,0x61,0x00,0x02]
 # CHECK-TRAP: lui $1, 32768               # encoding: [0x3c,0x01,0x80,0x00]
 # CHECK-TRAP: teq $25, $1, 6              # encoding: [0x03,0x21,0x01,0xb4]
 # CHECK-TRAP: mflo $25                    # encoding: [0x00,0x00,0xc8,0x12]
# CHECK-TRAP: mflo $24                    # encoding: [0x00,0x00,0xc0,0x12]
   div $25,$0
 # CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
 
   div $0,$9
 # CHECK-TRAP: div $zero, $zero, $9        # encoding: [0x00,0x09,0x00,0x1a]
 
   div $0,$0
 # CHECK-TRAP: div $zero, $zero, $zero     # encoding: [0x00,0x00,0x00,0x1a]
+
+  div  $4,$5,$6
+# CHECK-TRAP: teq $6, $zero, 7            # encoding: [0x00,0xc0,0x01,0xf4]
+# CHECK-TRAP: div $zero, $5, $6           # encoding: [0x00,0xa6,0x00,0x1a]
+# CHECK-TRAP: addiu $1, $zero, -1         # encoding: [0x24,0x01,0xff,0xff]
+# CHECK-TRAP: bne $6, $1, 8               # encoding: [0x14,0xc1,0x00,0x02]
+# CHECK-TRAP: lui $1, 32768               # encoding: [0x3c,0x01,0x80,0x00]
+# CHECK-TRAP: teq $5, $1, 6               # encoding: [0x00,0xa1,0x01,0xb4]
+# CHECK-TRAP: mflo  $4                    # encoding: [0x00,0x00,0x20,0x12]
+
+  div  $4,$5,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  div  $4,$0,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  div $0, $4, $5
+# CHECK-TRAP: div $zero, $4, $5           # encoding: [0x00,0x85,0x00,0x1a]
 No newline at end of file

test/MC/Mips/macro-divu.s

 # CHECK-NOTRAP: mflo $25                  # encoding: [0x00,0x00,0xc8,0x12]
 
   divu $0,$9
 # CHECK-NOTRAP: divu $zero, $zero, $9     # encoding: [0x00,0x09,0x00,0x1b]
 
   divu $0,$0
 # CHECK-NOTRAP: divu $zero, $zero, $zero  # encoding: [0x00,0x00,0x00,0x1b]
 
+   divu $4,$5,$6
+# CHECK-NOTRAP: bnez $6, 8                # encoding: [0x14,0xc0,0x00,0x02]
+# CHECK-NOTRAP: divu $zero, $5, $6        # encoding: [0x00,0xa6,0x00,0x1b]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+   divu $4,$5,$0
+# CHECK-NOTRAP: bnez $zero, 8             # encoding: [0x14,0x00,0x00,0x02]
+# CHECK-NOTRAP: divu $zero, $5, $zero     # encoding: [0x00,0xa0,0x00,0x1b]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+   divu $4,$0,$0
+# CHECK-NOTRAP: bnez $zero, 8             # encoding: [0x14,0x00,0x00,0x02]
+# CHECK-NOTRAP: divu $zero, $zero, $zero  # encoding: [0x00,0x00,0x00,0x1b]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  divu $0, $4, $5
+# CHECK-NOTRAP: divu $zero, $4, $5        # encoding: [0x00,0x85,0x00,0x1b]
+
    divu $25, $11
-# CHECK-TRAP: teq $11, $zero, 7           # encoding: [0x01,0x60,0x01,0xf4]
+# CHECK-TRAP: teq $11, $zero, 7           # encoding: [0x01,0x60,0x01,0xf4]
 # CHECK-TRAP: divu $zero, $25, $11        # encoding: [0x03,0x2b,0x00,0x1b]
 # CHECK-TRAP: mflo $25                    # encoding: [0x00,0x00,0xc8,0x12]
 
    divu $24,$12
 # CHECK-TRAP: teq $12, $zero, 7           # encoding: [0x01,0x80,0x01,0xf4]
 # CHECK-TRAP: divu $zero, $24, $12        # encoding: [0x03,0x0c,0x00,0x1b]
 # CHECK-TRAP: mflo $24                    # encoding: [0x00,0x00,0xc0,0x12]
 
   divu $25,$0
 # CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
 # CHECK-TRAP: divu $zero, $25, $zero      # encoding: [0x03,0x20,0x00,0x1b]
 # CHECK-TRAP: mflo $25                    # encoding: [0x00,0x00,0xc8,0x12]
 
   divu $0,$9
 # CHECK-TRAP: divu $zero, $zero, $9       # encoding: [0x00,0x09,0x00,0x1b]
 
   divu $0,$0
 # CHECK-TRAP: divu $zero, $zero, $zero    # encoding: [0x00,0x00,0x00,0x1b]
+
+  divu $4,$5,$6
+# CHECK-TRAP: teq $6, $zero, 7            # encoding: [0x00,0xc0,0x01,0xf4]
+# CHECK-TRAP: divu $zero, $5, $6          # encoding: [0x00,0xa6,0x00,0x1b]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  divu $4,$5,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+# CHECK-TRAP: divu $zero, $5, $zero       # encoding: [0x00,0xa0,0x00,0x1b]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  divu $4,$0,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+# CHECK-TRAP: divu $zero, $zero, $zero    # encoding: [0x00,0x00,0x00,0x1b]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  divu $0, $4, $5
+# CHECK-TRAP: divu $zero, $4, $5          # encoding: [0x00,0x85,0x00,0x1b]