[RISCV] Remove XLen field from RISCVSubtarget [nfc]

[reames]

Summary

We also have IsRV64 which, unless I'm missing something, contains the same information. I did add an assert to catch the case where the triple and cpu are out of sync. I haven't checked, but I assume a more useful error is reported by clang. Or at least, I can't think of a configuration where a rv32 triple and a rv64 cpu definition (and thus ISEL) make sense. Posting this for review mostly to make sure I'm not missing something on that point.

[craig.topper]

There's a CPU check in llvm/lib/Target/RISCV/MCTargetDesc//RISCVBaseInfo.cpp in the validate function

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVSubtarget.h

private:
   virtual void anchor();
 
   RISCVProcFamilyEnum RISCVProcFamily = Others;
 
 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
   bool ATTRIBUTE = DEFAULT;
 #include "RISCVGenSubtargetInfo.inc"
 
-  unsigned XLen = 32;
   unsigned ZvlLen = 0;
   unsigned RVVVectorBitsMin;
   unsigned RVVVectorBitsMax;
   uint8_t MaxInterleaveFactor = 2;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
   Align PrefFunctionAlignment;
   Align PrefLoopAlignment;
#include "RISCVGenSubtargetInfo.inc"
   bool hasStdExtZfhOrZfhminOrZhinxOrZhinxmin() const {
     return hasStdExtZfhOrZfhmin() || hasStdExtZhinxOrZhinxmin();
   }
   bool hasHalfFPLoadStoreMove() const {
     return hasStdExtZfhOrZfhmin() || HasStdExtZfbfmin;
   }
   bool is64Bit() const { return IsRV64; }
   MVT getXLenVT() const {
-    return MVT::getIntegerVT(getXLen());
+    return is64Bit() ? MVT::i64 : MVT::i32;
   }
   unsigned getXLen() const {
-    assert((XLen == 32 || XLen == 64) &&
-           "unexpected xlen");
-    return XLen;
+    return is64Bit() ? 64 : 32;
   }
   unsigned getFLen() const {
     if (HasStdExtD)
       return 64;
 
     if (HasStdExtF)
       return 32;
 

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
   bool Is64Bit = TT.isArch64Bit();
   if (CPU.empty() || CPU == "generic")
     CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
 
   if (TuneCPU.empty())
     TuneCPU = CPU;
 
   ParseSubtargetFeatures(CPU, TuneCPU, FS);
-  if (Is64Bit)
-    XLen = 64;
+  assert(Is64Bit == IsRV64 && "unexpected triple/cpu mismatch");
 
   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
   RISCVFeatures::validate(TT, getFeatureBits());
   return *this;
 }
 
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
                                StringRef TuneCPU, StringRef FS,