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[RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.
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Authored by craig.topper on Aug 28 2023, 3:45 PM.

Details

Summary

The 'let' with the Latency and Cycles from the previous defm should
apply to this one as well. Introduce a scope around the two defms.

Diff Detail

Unit TestsFailed

Event Timeline

craig.topper created this revision.Aug 28 2023, 3:45 PM
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craig.topper requested review of this revision.Aug 28 2023, 3:45 PM
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I remember that the reasom why we added separate Scheds for min/max reductions is that your downstream needs to give different scheduling for min/max from other reductions in D155108.
Is it right for this processor?

I remember that the reasom why we added separate Scheds for min/max reductions is that your downstream needs to give different scheduling for min/max from other reductions in D155108.
Is it right for this processor?

Yes. For this processor min/max is the same as add/and/or/xor. We need it split for a processor we haven't upstreamed yet.

wangpc accepted this revision.Aug 28 2023, 7:51 PM

LGTM.

This revision is now accepted and ready to land.Aug 28 2023, 7:51 PM
This revision was landed with ongoing or failed builds.Aug 28 2023, 10:47 PM
This revision was automatically updated to reflect the committed changes.