[RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.

[craig.topper]

Summary

The 'let' with the Latency and Cycles from the previous defm should
apply to this one as well. Introduce a scope around the two defms.

[wangpc]

I remember that the reasom why we added separate Scheds for min/max reductions is that your downstream needs to give different scheduling for min/max from other reductions in D155108.
Is it right for this processor?

[craig.topper]

In D159029#4623433, @wangpc wrote:

I remember that the reasom why we added separate Scheds for min/max reductions is that your downstream needs to give different scheduling for min/max from other reductions in D155108.
Is it right for this processor?

Yes. For this processor min/max is the same as add/and/or/xor. We need it split for a processor we haven't upstreamed yet.

[wangpc]

LGTM.

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

foreach mx = SchedMxListFW in {
   }
 }
 
 // 14. Vector Reduction Operations
 foreach mx = SchedMxList in {
   foreach sew = SchedSEWSet<mx>.val in {
     defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
-    let Latency = Cycles, ReleaseAtCycles = [Cycles] in
+    let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
       defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
                                      mx, sew, IsWorstCase>;
       defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
                                      mx, sew, IsWorstCase>;
     }
   }
+}
 
 foreach mx = SchedMxListWRed in {
   foreach sew = SchedSEWSet<mx, 0, 1>.val in {
     defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
     let Latency = Cycles, ReleaseAtCycles = [Cycles] in
     defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFive7VA],
                                    mx, sew, IsWorstCase>;