[PowerPC] Try to use less instructions to materialize 64-bit constant when High32=Low32

[Esme]

Summary

Materialization a 64-bit constant with High32=Low32 only requires 2 instructions instead of 3 when Low32 can be materialized in 1 instruction.

[qiucf]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1182–1188

Can we remove this part? I think it's already been handled.

[lkail]

llvm/test/CodeGen/PowerPC/constants-i64.ll

427

Please pre-commit these test cases.

[Esme]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1182–1188

Do you mean the case where 3 instructions are needed?
If we remove it, we will use 4 instructions for constants like 0xFFF7C000FFF7C000.

[Esme]

Address comments.

[Esme]

Gentle ping

[qiucf]

LGTM, thanks.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
   if ((Shift = findContiguousZerosAtLeast(Imm, 49)) ||
       (Shift = findContiguousZerosAtLeast(~Imm, 49))) {
     uint64_t RotImm = APInt(64, Imm).rotr(Shift).getZExtValue();
     Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64,
                                     getI32Imm(RotImm & 0xffff));
     return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, SDValue(Result, 0),
                                   getI32Imm(Shift), getI32Imm(0));
   }
+  // 2-7) Patterns : High word == Low word
+  // This may require 2 to 3 instructions, depending on whether Lo32 can be
+  // materialized in 1 instruction.
+  if (Hi32 == Lo32) {
+    // Handle the first 32 bits.
+    uint64_t ImmHi16 = (Lo32 >> 16) & 0xffff;
+    uint64_t ImmLo16 = Lo32 & 0xffff;
+    if (isInt<16>(Lo32))
+      Result =
+          CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(ImmLo16));
+    else if (!ImmLo16)
+      Result =
+          CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(ImmHi16));
+    else {
+      InstCnt = 3;
+      Result =
+          CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(ImmHi16));
+      Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
+                                      SDValue(Result, 0), getI32Imm(ImmLo16));
+    }
+    // Use rldimi to insert the Low word into High word.
+    SDValue Ops[] = {SDValue(Result, 0), SDValue(Result, 0), getI32Imm(32),
+                     getI32Imm(0)};
+    return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
+  }
 
   // Following patterns use 3 instructions to materialize the Imm.
   InstCnt = 3;
   // 3-1) Patterns : {zeros}{ones}{31-bit value}{zeros}
   //                 {zeros}{31-bit value}{zeros}
   //                 {zeros}{ones}{31-bit value}
   //                 {ones}{31-bit value}{zeros}
   // We can take advantage of LIS's sign-extension semantics to generate leading
static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
   if ((LZ + FO + TO) > 32) {
     Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64,
                                     getI32Imm((Imm >> (TO + 16)) & 0xffff));
     Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
                                     getI32Imm((Imm >> TO) & 0xffff));
     return CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, SDValue(Result, 0),
                                   getI32Imm(TO), getI32Imm(LZ));
   }
-  // 3-4) Patterns : High word == Low word
-  if (Hi32 == Lo32) {
-    // Handle the first 32 bits.
-    uint64_t ImmHi16 = (Lo32 >> 16) & 0xffff;
-    unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
-    Result = CurDAG->getMachineNode(Opcode, dl, MVT::i64, getI32Imm(ImmHi16));
-    Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0),
-                                    getI32Imm(Lo32 & 0xffff));
-    // Use rldimi to insert the Low word into High word.
-    SDValue Ops[] = {SDValue(Result, 0), SDValue(Result, 0), getI32Imm(32),
-                     getI32Imm(0)};
-    return CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops);
-  }
-  // 3-5) Patterns : {******}{33 zeros}{******}
+  // 3-4) Patterns : {******}{33 zeros}{******}
   //                 {******}{33 ones}{******}
   // If the Imm contains 33 consecutive zeros/ones, it means that a total of 31
   // bits remain on both sides. Rotate right the Imm to construct an int<32>
   // value, use LIS + ORI for int<32> value and then use RLDICL without mask to
   // rotate it back.
   // This is similar to Pattern 2-6, please refer to the diagram there.
   if ((Shift = findContiguousZerosAtLeast(Imm, 33)) ||
       (Shift = findContiguousZerosAtLeast(~Imm, 33))) {

llvm/test/CodeGen/PowerPC/constants-i64.ll

 ; CHECK-NEXT:    ori 3, 3, 52479
 ; CHECK-NEXT:    rldimi 3, 3, 32, 0
 ; CHECK-NEXT:    rlwimi 3, 3, 16, 0, 15
 ; CHECK-NEXT:    blr
 entry:
   ret i64 82134617250843903 ;0x0123CCFFCCFFCCFF
 }
 
 define i64 @imm23() {
 ; CHECK-LABEL: imm23:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lis 3, -2
-; CHECK-NEXT:    ori 3, 3, 0
-; CHECK-NEXT:    rldicl 3, 3, 15, 17
+; CHECK-NEXT:    li 3, 32767
+; CHECK-NEXT:    rldimi 3, 3, 32, 0
 ; CHECK-NEXT:    blr
 entry:
   ret i64 140733193420799 ;0x00007FFF00007FFF
 }
 
 define i64 @imm24() {
 ; CHECK-LABEL: imm24:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis 3, -9
-; CHECK-NEXT:    ori 3, 3, 0
 ; CHECK-NEXT:    rldimi 3, 3, 32, 0
 ; CHECK-NEXT:    blr
 entry:
   ret i64 18444210803213533184 ;0xFFF70000FFF70000
 }
 
 attributes #0 = { nounwind readnone }