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Differential D158350

[RISCV][GISel] Make G_SEXT_INREG with source size of 32 legal for RV64.
ClosedPublic

Authored by craig.topper on Aug 19 2023, 2:37 PM.

Details

Reviewers
arsenm
nitinjohnraj
asb
reames
Commits
rG479716d95431: [RISCV][GISel] Make G_SEXT_INREG with source size of 32 legal for RV64.
Summary

This maps to the sext.w instruction.

As far as I could tell this needs custom lowering to check the immediate.

Diff Detail

Event Timeline

craig.topper created this revision.Aug 19 2023, 2:37 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 19 2023, 2:37 PM
Herald added subscribers: jobnoorman, luke, sunshaoce and 28 others. · View Herald Transcript
craig.topper requested review of this revision.Aug 19 2023, 2:37 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 19 2023, 2:37 PM
Herald added subscribers: wangpc, eopXD, MaskRay, wdng. · View Herald Transcript
Harbormaster completed remote builds in B253688: Diff 551790.Aug 19 2023, 3:10 PM
nitinjohnraj accepted this revision.Aug 21 2023, 10:01 AM

LGTM

This revision is now accepted and ready to land.Aug 21 2023, 10:01 AM
This revision was landed with ongoing or failed builds.Aug 21 2023, 10:43 AM
Closed by commit rG479716d95431: [RISCV][GISel] Make G_SEXT_INREG with source size of 32 legal for RV64. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG479716d95431: [RISCV][GISel] Make G_SEXT_INREG with source size of 32 legal for RV64..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
GISel/
2 lines
37 lines
test/
CodeGen/
RISCV/
GlobalISel/
legalizer/
rv64/
12 lines
40 lines
12 lines

Diff 552079

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h

Show All 17 Lines
namespace llvm { namespace llvm {
class RISCVSubtarget; class RISCVSubtarget;
/// This class provides the information for the target register banks. /// This class provides the information for the target register banks.
class RISCVLegalizerInfo : public LegalizerInfo { class RISCVLegalizerInfo : public LegalizerInfo {
public: public:
RISCVLegalizerInfo(const RISCVSubtarget &ST); RISCVLegalizerInfo(const RISCVSubtarget &ST);
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

//===-- RISCVLegalizerInfo.cpp ----------------------------------*- C++ -*-===// //===-- RISCVLegalizerInfo.cpp ----------------------------------*- C++ -*-===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// \file /// \file
/// This file implements the targeting of the Machinelegalizer class for RISC-V. /// This file implements the targeting of the Machinelegalizer class for RISC-V.
/// \todo This should be generated by TableGen. /// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "RISCVLegalizerInfo.h" #include "RISCVLegalizerInfo.h"
#include "RISCVSubtarget.h" #include "RISCVSubtarget.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h" #include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
using namespace llvm; using namespace llvm;
RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) { RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
Show All 23 Lines getActionDefinitionsBuilder(
.lowerFor({{XLenLLT, s1}}); .lowerFor({{XLenLLT, s1}});
getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
.legalFor({{s32, s32}, {s32, XLenLLT}, {XLenLLT, XLenLLT}}) .legalFor({{s32, s32}, {s32, XLenLLT}, {XLenLLT, XLenLLT}})
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.clampScalar(1, s32, XLenLLT) .clampScalar(1, s32, XLenLLT)
.clampScalar(0, s32, XLenLLT); .clampScalar(0, s32, XLenLLT);
if (ST.is64Bit()) if (ST.is64Bit()) {
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
.legalFor({{XLenLLT, s32}}) .legalFor({{XLenLLT, s32}})
.maxScalar(0, XLenLLT); .maxScalar(0, XLenLLT);
else
getActionDefinitionsBuilder(G_SEXT_INREG)
.customFor({XLenLLT})
.maxScalar(0, XLenLLT)
.lower();
} else {
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
.maxScalar(0, XLenLLT); .maxScalar(0, XLenLLT);
getActionDefinitionsBuilder(G_SEXT_INREG) getActionDefinitionsBuilder(G_SEXT_INREG)
.maxScalar(0, XLenLLT) .maxScalar(0, XLenLLT)
.lower(); .lower();
}
// Merge/Unmerge // Merge/Unmerge
for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) { for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1; unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0; unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
getActionDefinitionsBuilder(Op) getActionDefinitionsBuilder(Op)
.widenScalarToNextPow2(LitTyIdx, XLen) .widenScalarToNextPow2(LitTyIdx, XLen)
.widenScalarToNextPow2(BigTyIdx, XLen) .widenScalarToNextPow2(BigTyIdx, XLen)
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines if (ST.hasStdExtM()) {
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM}) getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM})
.libcallFor({XLenLLT, DoubleXLenLLT}) .libcallFor({XLenLLT, DoubleXLenLLT})
.clampScalar(0, XLenLLT, DoubleXLenLLT) .clampScalar(0, XLenLLT, DoubleXLenLLT)
.widenScalarToNextPow2(0); .widenScalarToNextPow2(0);
} }
getLegacyLegalizerInfo().computeTables(); getLegacyLegalizerInfo().computeTables();
} }
bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
// No idea what to do.
return false;
case TargetOpcode::G_SEXT_INREG: {
// Source size of 32 is sext.w.
int64_t SizeInBits = MI.getOperand(2).getImm();
if (SizeInBits == 32)
return true;
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
LegalizerHelper::Legalized;
}
}
llvm_unreachable("expected switch to return");
}

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-div.mir

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... ...
--- ---
name: sdiv_i32 name: sdiv_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-I-LABEL: name: sdiv_i32 ; CHECK-I-LABEL: name: sdiv_i32
; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) ; CHECK-I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) ; CHECK-I-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; CHECK-I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-I-NEXT: $x11 = COPY [[SEXT_INREG1]](s64)
; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__divdi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10 ; CHECK-I-NEXT: PseudoRET implicit $x10
; ;
; CHECK-M-LABEL: name: sdiv_i32 ; CHECK-M-LABEL: name: sdiv_i32
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir

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... ...
--- ---
name: cmp_sgt_i32 name: cmp_sgt_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_sgt_i32 ; CHECK-LABEL: name: cmp_sgt_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64) %2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64) %3:_(s32) = G_TRUNC %1(s64)
%4:_(s1) = G_ICMP intpred(sgt), %2(s32), %3 %4:_(s1) = G_ICMP intpred(sgt), %2(s32), %3
%5:_(s64) = G_ANYEXT %4(s1) %5:_(s64) = G_ANYEXT %4(s1)
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... ...
--- ---
name: cmp_slt_i32 name: cmp_slt_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_slt_i32 ; CHECK-LABEL: name: cmp_slt_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64) %2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64) %3:_(s32) = G_TRUNC %1(s64)
%4:_(s1) = G_ICMP intpred(slt), %2(s32), %3 %4:_(s1) = G_ICMP intpred(slt), %2(s32), %3
%5:_(s64) = G_ANYEXT %4(s1) %5:_(s64) = G_ANYEXT %4(s1)
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... ...
--- ---
name: cmp_sge_i32 name: cmp_sge_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_sge_i32 ; CHECK-LABEL: name: cmp_sge_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64) %2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64) %3:_(s32) = G_TRUNC %1(s64)
%4:_(s1) = G_ICMP intpred(sge), %2(s32), %3 %4:_(s1) = G_ICMP intpred(sge), %2(s32), %3
%5:_(s64) = G_ANYEXT %4(s1) %5:_(s64) = G_ANYEXT %4(s1)
▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines
... ...
--- ---
name: cmp_sle_i32 name: cmp_sle_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_sle_i32 ; CHECK-LABEL: name: cmp_sle_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: $x10 = COPY [[ICMP]](s64) ; CHECK-NEXT: $x10 = COPY [[ICMP]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64) %2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64) %3:_(s32) = G_TRUNC %1(s64)
%4:_(s1) = G_ICMP intpred(sle), %2(s32), %3 %4:_(s1) = G_ICMP intpred(sle), %2(s32), %3
%5:_(s64) = G_ANYEXT %4(s1) %5:_(s64) = G_ANYEXT %4(s1)
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llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-rem.mir

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... ...
--- ---
name: srem_i32 name: srem_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-I-LABEL: name: srem_i32 ; CHECK-I-LABEL: name: srem_i32
; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64) ; CHECK-I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64) ; CHECK-I-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; CHECK-I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK-I-NEXT: $x11 = COPY [[SEXT_INREG1]](s64)
; CHECK-I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
; CHECK-I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 ; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64) ; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
; CHECK-I-NEXT: PseudoRET implicit $x10 ; CHECK-I-NEXT: PseudoRET implicit $x10
; ;
; CHECK-M-LABEL: name: srem_i32 ; CHECK-M-LABEL: name: srem_i32
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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