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Differential D158160

[RISCV] Add test case showing vmerge fold miscompile with tail policy
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Authored by luke on Aug 17 2023, 2:57 AM.

Details

Reviewers
craig.topper
reames
Commits
rG6e532f94eb0e: [RISCV] Add test case showing vmerge fold miscompile with tail policy

Diff Detail

Event Timeline

luke created this revision.Aug 17 2023, 2:57 AM
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luke requested review of this revision.Aug 17 2023, 2:57 AM
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luke added a child revision: D158161: [RISCV] Don't relax policy to ta when vmerge's VL shrinks during folding.Aug 17 2023, 2:57 AM
luke updated this revision to Diff 551062.Aug 17 2023, 2:59 AM

Use poison instead of undef

Harbormaster completed remote builds in B253166: Diff 551062.Aug 17 2023, 3:39 AM
reames accepted this revision.Aug 17 2023, 11:38 AM

LGTM

This revision is now accepted and ready to land.Aug 17 2023, 11:38 AM
This revision was landed with ongoing or failed builds.Aug 22 2023, 2:39 AM
Closed by commit rG6e532f94eb0e: [RISCV] Add test case showing vmerge fold miscompile with tail policy (authored by luke). · Explain Why
This revision was automatically updated to reflect the committed changes.
luke added a commit: rG6e532f94eb0e: [RISCV] Add test case showing vmerge fold miscompile with tail policy.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
12 lines

Diff 552273

llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

Show First 20 Lines • Show All 1,059 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 2) %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 2)
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 3) %b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 3)
ret <vscale x 2 x i32> %b ret <vscale x 2 x i32> %b
} }
; FIXME: The vadd's new policy should be tail undisturbed since the false op of
; the vmerge moves from the the body to the tail, and we need to preserve it.
define <vscale x 2 x i32> @vmerge_larger_vl_false_becomes_tail(<vscale x 2 x i32> %false, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: vmerge_larger_vl_false_becomes_tail:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 2)
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %false, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 3)
ret <vscale x 2 x i32> %b
}