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Differential D157940

AMDGPU: Fix fast f32 log/log10
ClosedPublic

Authored by arsenm on Aug 14 2023, 5:45 PM.

Details

Reviewers
foad
rampitec
Pierre-vh
cdevadas
Group Reviewers
Restricted Project
Summary

OpenCL conformance didn't like interpreting afn as ignore the denormal
handling.

Diff Detail

Unit TestsFailed

TimeTest
60,030 msx64 debian > MLIR.Examples/standalone::test.toy

Event Timeline

arsenm created this revision.Aug 14 2023, 5:45 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 14 2023, 5:45 PM
Herald added subscribers: StephenFan, kerbowa, hiraditya and 6 others. · View Herald Transcript
arsenm requested review of this revision.Aug 14 2023, 5:45 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 14 2023, 5:45 PM
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arsenm added a parent revision: D157936: AMDGPU: Fix fast math log2 f32.Aug 14 2023, 5:45 PM
Harbormaster completed remote builds in B252510: Diff 550157.Aug 14 2023, 11:12 PM
rampitec accepted this revision.Aug 15 2023, 12:20 AM
This revision is now accepted and ready to land.Aug 15 2023, 12:20 AM
arsenm mentioned this in rG4b7b4b945856: AMDGPU: Fix fast f32 log/log10.Aug 15 2023, 7:49 AM
arsenm closed this revision.Aug 15 2023, 10:47 AM

4b7b4b945856c46b91ade7b6c4264fe8e258367e

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
33 lines
2 lines
37 lines
test/
CodeGen/
AMDGPU/
703 lines
703 lines

Diff 550157

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Linesprotected:
std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG, std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG,
const SDLoc SL, SDValue Op, const SDLoc SL, SDValue Op,
SDNodeFlags Flags) const; SDNodeFlags Flags) const;
SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
double Log2BaseInverted, SDNodeFlags Flags) const; bool IsLog10, SDNodeFlags Flags) const;
SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
SDNodeFlags Flags) const; SDNodeFlags Flags) const;
SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
▲ Show 20 Lines • Show All 512 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 2,604 Lines • ▼ Show 20 LinesSDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op,
if (VT == MVT::f16 || Flags.hasApproximateFuncs() || if (VT == MVT::f16 || Flags.hasApproximateFuncs() ||
Options.ApproxFuncFPMath || Options.UnsafeFPMath) { Options.ApproxFuncFPMath || Options.UnsafeFPMath) {
if (VT == MVT::f16 && !Subtarget->has16BitInsts()) { if (VT == MVT::f16 && !Subtarget->has16BitInsts()) {
// Log and multiply in f32 is good enough for f16. // Log and multiply in f32 is good enough for f16.
X = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, X, Flags); X = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, X, Flags);
} }
SDValue Lowered = LowerFLOGUnsafe( SDValue Lowered = LowerFLOGUnsafe(X, DL, DAG, IsLog10, Flags);
X, DL, DAG, IsLog10 ? numbers::ln2 / numbers::ln10 : numbers::ln2,
Flags);
if (VT == MVT::f16 && !Subtarget->has16BitInsts()) { if (VT == MVT::f16 && !Subtarget->has16BitInsts()) {
return DAG.getNode(ISD::FP_ROUND, DL, VT, Lowered, return DAG.getNode(ISD::FP_ROUND, DL, VT, Lowered,
DAG.getTargetConstant(0, DL, MVT::i32), Flags); DAG.getTargetConstant(0, DL, MVT::i32), Flags);
} }
return Lowered; return Lowered;
} }
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
SDValue AMDGPUTargetLowering::LowerFLOG10(SDValue Op, SelectionDAG &DAG) const { SDValue AMDGPUTargetLowering::LowerFLOG10(SDValue Op, SelectionDAG &DAG) const {
return LowerFLOGCommon(Op, DAG); return LowerFLOGCommon(Op, DAG);
} }
// Do f32 fast math expansion for flog2 or flog10. This is accurate enough for a // Do f32 fast math expansion for flog2 or flog10. This is accurate enough for a
// promote f16 operation. // promote f16 operation.
SDValue AMDGPUTargetLowering::LowerFLOGUnsafe(SDValue Src, const SDLoc &SL, SDValue AMDGPUTargetLowering::LowerFLOGUnsafe(SDValue Src, const SDLoc &SL,
SelectionDAG &DAG, SelectionDAG &DAG, bool IsLog10,
double Log2BaseInverted,
SDNodeFlags Flags) const { SDNodeFlags Flags) const {
EVT VT = Src.getValueType(); EVT VT = Src.getValueType();
unsigned LogOp = VT == MVT::f32 ? AMDGPUISD::LOG : ISD::FLOG2; unsigned LogOp = VT == MVT::f32 ? AMDGPUISD::LOG : ISD::FLOG2;
double Log2BaseInverted =
IsLog10 ? numbers::ln2 / numbers::ln10 : numbers::ln2;
if (VT == MVT::f32) {
auto [ScaledInput, IsScaled] = getScaledLogInput(DAG, SL, Src, Flags);
if (ScaledInput) {
SDValue LogSrc = DAG.getNode(AMDGPUISD::LOG, SL, VT, ScaledInput, Flags);
SDValue ScaledResultOffset =
DAG.getConstantFP(-32.0 * Log2BaseInverted, SL, VT);
SDValue Zero = DAG.getConstantFP(0.0f, SL, VT);
SDValue ResultOffset = DAG.getNode(ISD::SELECT, SL, VT, IsScaled,
ScaledResultOffset, Zero, Flags);
SDValue Log2Inv = DAG.getConstantFP(Log2BaseInverted, SL, VT);
if (Subtarget->hasFastFMAF32())
return DAG.getNode(ISD::FMA, SL, VT, LogSrc, Log2Inv, ResultOffset,
Flags);
SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, LogSrc, Log2Inv, Flags);
return DAG.getNode(ISD::FADD, SL, VT, Mul, ResultOffset);
}
}
SDValue Log2Operand = DAG.getNode(LogOp, SL, VT, Src, Flags); SDValue Log2Operand = DAG.getNode(LogOp, SL, VT, Src, Flags);
SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT); SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand, return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand,
Flags); Flags);
} }
SDValue AMDGPUTargetLowering::lowerFEXP2(SDValue Op, SelectionDAG &DAG) const { SDValue AMDGPUTargetLowering::lowerFEXP2(SDValue Op, SelectionDAG &DAG) const {
▲ Show 20 Lines • Show All 3,053 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const; MachineIRBuilder &B) const;
std::pair<Register, Register> std::pair<Register, Register>
getScaledLogInput(MachineIRBuilder &B, Register Src, unsigned Flags) const; getScaledLogInput(MachineIRBuilder &B, Register Src, unsigned Flags) const;
bool legalizeFlog2(MachineInstr &MI, MachineIRBuilder &B) const; bool legalizeFlog2(MachineInstr &MI, MachineIRBuilder &B) const;
bool legalizeFlogCommon(MachineInstr &MI, MachineIRBuilder &B) const; bool legalizeFlogCommon(MachineInstr &MI, MachineIRBuilder &B) const;
bool legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst, Register Src, bool legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
double Log2BaseInverted, unsigned Flags) const; bool IsLog10, unsigned Flags) const;
bool legalizeFExp2(MachineInstr &MI, MachineIRBuilder &B) const; bool legalizeFExp2(MachineInstr &MI, MachineIRBuilder &B) const;
bool legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst, Register Src, bool legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
unsigned Flags) const; unsigned Flags) const;
bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const; bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const; bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const; MachineIRBuilder &B) const;
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 3,131 Lines • ▼ Show 20 Linesbool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI,
const LLT F32 = LLT::scalar(32); const LLT F32 = LLT::scalar(32);
const LLT F16 = LLT::scalar(16); const LLT F16 = LLT::scalar(16);
const AMDGPUTargetMachine &TM = const AMDGPUTargetMachine &TM =
static_cast<const AMDGPUTargetMachine &>(MF.getTarget()); static_cast<const AMDGPUTargetMachine &>(MF.getTarget());
if (Ty == F16 || MI.getFlag(MachineInstr::FmAfn) || if (Ty == F16 || MI.getFlag(MachineInstr::FmAfn) ||
TM.Options.ApproxFuncFPMath || TM.Options.UnsafeFPMath) { TM.Options.ApproxFuncFPMath || TM.Options.UnsafeFPMath) {
const double Log2BaseInv =
IsLog10 ? numbers::ln2 / numbers::ln10 : numbers::ln2;
if (Ty == F16 && !ST.has16BitInsts()) { if (Ty == F16 && !ST.has16BitInsts()) {
Register LogVal = MRI.createGenericVirtualRegister(F32); Register LogVal = MRI.createGenericVirtualRegister(F32);
auto PromoteSrc = B.buildFPExt(F32, X); auto PromoteSrc = B.buildFPExt(F32, X);
legalizeFlogUnsafe(B, LogVal, PromoteSrc.getReg(0), Log2BaseInv, Flags); legalizeFlogUnsafe(B, LogVal, PromoteSrc.getReg(0), IsLog10, Flags);
B.buildFPTrunc(Dst, LogVal); B.buildFPTrunc(Dst, LogVal);
} else { } else {
legalizeFlogUnsafe(B, Dst, X, Log2BaseInv, Flags); legalizeFlogUnsafe(B, Dst, X, IsLog10, Flags);
} }
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
auto [ScaledInput, IsScaled] = getScaledLogInput(B, X, Flags); auto [ScaledInput, IsScaled] = getScaledLogInput(B, X, Flags);
if (ScaledInput) if (ScaledInput)
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines if (ScaledInput) {
B.buildCopy(Dst, R); B.buildCopy(Dst, R);
} }
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
bool AMDGPULegalizerInfo::legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst, bool AMDGPULegalizerInfo::legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst,
Register Src, Register Src, bool IsLog10,
double Log2BaseInverted,
unsigned Flags) const { unsigned Flags) const {
const double Log2BaseInverted =
IsLog10 ? numbers::ln2 / numbers::ln10 : numbers::ln2;
LLT Ty = B.getMRI()->getType(Dst); LLT Ty = B.getMRI()->getType(Dst);
if (Ty == LLT::scalar(32)) {
auto [ScaledInput, IsScaled] = getScaledLogInput(B, Src, Flags);
if (ScaledInput) {
auto LogSrc = B.buildIntrinsic(Intrinsic::amdgcn_log, {Ty})
.addUse(Src)
.setMIFlags(Flags);
auto ScaledResultOffset = B.buildFConstant(Ty, -32.0 * Log2BaseInverted);
auto Zero = B.buildFConstant(Ty, 0.0);
auto ResultOffset =
B.buildSelect(Ty, IsScaled, ScaledResultOffset, Zero, Flags);
auto Log2Inv = B.buildFConstant(Ty, Log2BaseInverted);
if (ST.hasFastFMAF32())
B.buildFMA(Dst, LogSrc, Log2Inv, ResultOffset, Flags);
else {
auto Mul = B.buildFMul(Ty, LogSrc, Log2Inv, Flags);
B.buildFAdd(Dst, Mul, ResultOffset, Flags);
}
return true;
}
}
auto Log2Operand = Ty == LLT::scalar(16) auto Log2Operand = Ty == LLT::scalar(16)
? B.buildFLog2(Ty, Src, Flags) ? B.buildFLog2(Ty, Src, Flags)
: B.buildIntrinsic(Intrinsic::amdgcn_log, {Ty}) : B.buildIntrinsic(Intrinsic::amdgcn_log, {Ty})
.addUse(Src) .addUse(Src)
.setMIFlags(Flags); .setMIFlags(Flags);
auto Log2BaseInvertedOperand = B.buildFConstant(Ty, Log2BaseInverted); auto Log2BaseInvertedOperand = B.buildFConstant(Ty, Log2BaseInverted);
B.buildFMul(Dst, Log2Operand, Log2BaseInvertedOperand, Flags); B.buildFMul(Dst, Log2Operand, Log2BaseInvertedOperand, Flags);
return true; return true;
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llvm/test/CodeGen/AMDGPU/llvm.log.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,918 Lines • ▼ Show 20 Lines
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fneg = fneg float %in %fneg = fneg float %in
%result = call float @llvm.log.f32(float %fneg) %result = call float @llvm.log.f32(float %fneg)
ret float %result ret float %result
} }
define float @v_log_f32_fast(float %in) { define float @v_log_f32_fast(float %in) {
; GFX689-LABEL: v_log_f32_fast: ; SI-SDAG-LABEL: v_log_f32_fast:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_f32_fast: ; SI-GISEL-LABEL: v_log_f32_fast:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log_f32_fast:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log_f32_fast:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_fast:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log_f32_fast:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_fast:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc1b17218, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3f317218, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_f32_fast:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_fast: ; R600-LABEL: v_log_f32_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_fast: ; CM-LABEL: v_log_f32_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call fast float @llvm.log.f32(float %in) %result = call fast float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { define float @v_log_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
; GFX689-LABEL: v_log_f32_unsafe_math_attr: ; SI-SDAG-LABEL: v_log_f32_unsafe_math_attr:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_f32_unsafe_math_attr: ; SI-GISEL-LABEL: v_log_f32_unsafe_math_attr:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log_f32_unsafe_math_attr:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log_f32_unsafe_math_attr:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_unsafe_math_attr:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log_f32_unsafe_math_attr:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_unsafe_math_attr:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc1b17218, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3f317218, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_f32_unsafe_math_attr:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_unsafe_math_attr: ; R600-LABEL: v_log_f32_unsafe_math_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_unsafe_math_attr: ; CM-LABEL: v_log_f32_unsafe_math_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log.f32(float %in) %result = call float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" { define float @v_log_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
; GFX689-LABEL: v_log_f32_approx_fn_attr: ; SI-SDAG-LABEL: v_log_f32_approx_fn_attr:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_f32_approx_fn_attr: ; SI-GISEL-LABEL: v_log_f32_approx_fn_attr:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log_f32_approx_fn_attr:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log_f32_approx_fn_attr:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_approx_fn_attr:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log_f32_approx_fn_attr:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_approx_fn_attr:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc1b17218, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3f317218, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_f32_approx_fn_attr:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_approx_fn_attr: ; R600-LABEL: v_log_f32_approx_fn_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_approx_fn_attr: ; CM-LABEL: v_log_f32_approx_fn_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log.f32(float %in) %result = call ninf float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_afn(float %in) { define float @v_log_f32_afn(float %in) {
; GFX689-LABEL: v_log_f32_afn: ; SI-SDAG-LABEL: v_log_f32_afn:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_f32_afn: ; SI-GISEL-LABEL: v_log_f32_afn:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log_f32_afn:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_afn:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log_f32_afn:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_afn:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc1b17218, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3f317218, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_f32_afn:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_afn: ; R600-LABEL: v_log_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_afn: ; CM-LABEL: v_log_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
Show All 28 Lines
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log.f32(float %in) %result = call afn float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_afn_dynamic(float %in) #1 { define float @v_log_f32_afn_dynamic(float %in) #1 {
; GFX689-LABEL: v_log_f32_afn_dynamic: ; SI-SDAG-LABEL: v_log_f32_afn_dynamic:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_f32_afn_dynamic: ; SI-GISEL-LABEL: v_log_f32_afn_dynamic:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log_f32_afn_dynamic:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log_f32_afn_dynamic:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_afn_dynamic:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log_f32_afn_dynamic:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_afn_dynamic:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc1b17218, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3f317218, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_f32_afn_dynamic:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_afn_dynamic: ; R600-LABEL: v_log_f32_afn_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_afn_dynamic: ; CM-LABEL: v_log_f32_afn_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log.f32(float %in) %result = call afn float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_fabs_log_f32_afn(float %in) { define float @v_fabs_log_f32_afn(float %in) {
; GFX689-LABEL: v_fabs_log_f32_afn: ; SI-SDAG-LABEL: v_fabs_log_f32_afn:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e64 v0, |v0| ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_fabs_log_f32_afn: ; SI-GISEL-LABEL: v_fabs_log_f32_afn:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e64 v0, |v0| ; SI-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_fabs_log_f32_afn:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_fabs_log_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_fabs_log_f32_afn:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc1b17218
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317218
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_fabs_log_f32_afn:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_fabs_log_f32_afn:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc1b17218, s0
; GFX1100-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3f317218, v0
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_fabs_log_f32_afn:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e64 v1, |v0|
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, s0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_fabs_log_f32_afn: ; R600-LABEL: v_fabs_log_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_fabs_log_f32_afn: ; CM-LABEL: v_fabs_log_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
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llvm/test/CodeGen/AMDGPU/llvm.log10.ll

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; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fneg = fneg float %in %fneg = fneg float %in
%result = call float @llvm.log10.f32(float %fneg) %result = call float @llvm.log10.f32(float %fneg)
ret float %result ret float %result
} }
define float @v_log10_f32_fast(float %in) { define float @v_log10_f32_fast(float %in) {
; GFX689-LABEL: v_log10_f32_fast: ; SI-SDAG-LABEL: v_log10_f32_fast:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_f32_fast: ; SI-GISEL-LABEL: v_log10_f32_fast:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log10_f32_fast:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log10_f32_fast:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_fast:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log10_f32_fast:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_fast:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc11a209b, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_f32_fast:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_fast: ; R600-LABEL: v_log10_f32_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_fast: ; CM-LABEL: v_log10_f32_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call fast float @llvm.log10.f32(float %in) %result = call fast float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { define float @v_log10_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
; GFX689-LABEL: v_log10_f32_unsafe_math_attr: ; SI-SDAG-LABEL: v_log10_f32_unsafe_math_attr:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_f32_unsafe_math_attr: ; SI-GISEL-LABEL: v_log10_f32_unsafe_math_attr:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log10_f32_unsafe_math_attr:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log10_f32_unsafe_math_attr:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_unsafe_math_attr:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log10_f32_unsafe_math_attr:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_unsafe_math_attr:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc11a209b, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_f32_unsafe_math_attr:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_unsafe_math_attr: ; R600-LABEL: v_log10_f32_unsafe_math_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_unsafe_math_attr: ; CM-LABEL: v_log10_f32_unsafe_math_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log10.f32(float %in) %result = call float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" { define float @v_log10_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
; GFX689-LABEL: v_log10_f32_approx_fn_attr: ; SI-SDAG-LABEL: v_log10_f32_approx_fn_attr:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_f32_approx_fn_attr: ; SI-GISEL-LABEL: v_log10_f32_approx_fn_attr:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log10_f32_approx_fn_attr:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log10_f32_approx_fn_attr:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_approx_fn_attr:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log10_f32_approx_fn_attr:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_approx_fn_attr:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc11a209b, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_f32_approx_fn_attr:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_approx_fn_attr: ; R600-LABEL: v_log10_f32_approx_fn_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_approx_fn_attr: ; CM-LABEL: v_log10_f32_approx_fn_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log10.f32(float %in) %result = call ninf float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_afn(float %in) { define float @v_log10_f32_afn(float %in) {
; GFX689-LABEL: v_log10_f32_afn: ; SI-SDAG-LABEL: v_log10_f32_afn:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_f32_afn: ; SI-GISEL-LABEL: v_log10_f32_afn:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log10_f32_afn:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log10_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_afn:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log10_f32_afn:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_afn:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc11a209b, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_f32_afn:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_afn: ; R600-LABEL: v_log10_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_afn: ; CM-LABEL: v_log10_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
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; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log10.f32(float %in) %result = call afn float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_afn_dynamic(float %in) #1 { define float @v_log10_f32_afn_dynamic(float %in) #1 {
; GFX689-LABEL: v_log10_f32_afn_dynamic: ; SI-SDAG-LABEL: v_log10_f32_afn_dynamic:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e32 v0, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_f32_afn_dynamic: ; SI-GISEL-LABEL: v_log10_f32_afn_dynamic:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log10_f32_afn_dynamic:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_log10_f32_afn_dynamic:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_afn_dynamic:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_log10_f32_afn_dynamic:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_afn_dynamic:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc11a209b, vcc_lo
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_f32_afn_dynamic:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_afn_dynamic: ; R600-LABEL: v_log10_f32_afn_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_afn_dynamic: ; CM-LABEL: v_log10_f32_afn_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log10.f32(float %in) %result = call afn float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_fabs_log10_f32_afn(float %in) { define float @v_fabs_log10_f32_afn(float %in) {
; GFX689-LABEL: v_fabs_log10_f32_afn: ; SI-SDAG-LABEL: v_fabs_log10_f32_afn:
; GFX689: ; %bb.0: ; SI-SDAG: ; %bb.0:
; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX689-NEXT: v_log_f32_e64 v0, |v0| ; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX689-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; SI-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2
; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_fabs_log10_f32_afn: ; SI-GISEL-LABEL: v_fabs_log10_f32_afn:
; GFX1100: ; %bb.0: ; SI-GISEL: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e64 v0, |v0| ; SI-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX1100-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_fabs_log10_f32_afn:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; VI-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2
; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_fabs_log10_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_fabs_log10_f32_afn:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; GFX900-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2
; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xc11a209b
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209b
; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_fabs_log10_f32_afn:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_fabs_log10_f32_afn:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0
; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0xc11a209b, s0
; GFX1100-SDAG-NEXT: v_mul_f32_e64 v0, |v0|, v2
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_fmac_f32_e32 v1, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_fabs_log10_f32_afn:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e64 v1, |v0|
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, s0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_fabs_log10_f32_afn: ; R600-LABEL: v_fabs_log10_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_fabs_log10_f32_afn: ; CM-LABEL: v_fabs_log10_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
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