[RISCV][GISel] Make G_SELECT of pointers legal

[arsenm]

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

80

might want to add something like legalIf(isPointer(0)) to cover all the address spaces

[craig.topper]

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

80

Is AMDGPU the only target that uses multiple address spaces in GlobalISel today? I only see p0 in AArch64 for example.

[arsenm]

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

80

Probably. I know code in the wild is relying on the non-0 address spaces implicitly treated as 0 in SelectionDAG on x86

[jrtc27]

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

80

We use non-zero downstream for CHERI capabilities

[craig.topper]

I think I'd prefer to deal with non-zero address space in the future.

[reames]

LGTM - I am explicitly okay with the incrementalism for address spaces.

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
 
   getActionDefinitionsBuilder(G_ICMP)
       .legalFor({{XLenLLT, XLenLLT}})
       .widenScalarToNextPow2(1)
       .clampScalar(1, XLenLLT, XLenLLT)
       .clampScalar(0, XLenLLT, XLenLLT);
 
   getActionDefinitionsBuilder(G_SELECT)
-      .legalFor({{XLenLLT, XLenLLT}})
+      .legalFor({{XLenLLT, XLenLLT}, {p0, XLenLLT}})
       .widenScalarToNextPow2(0)
       .clampScalar(0, XLenLLT, XLenLLT)
       .clampScalar(1, XLenLLT, XLenLLT);
 
   getActionDefinitionsBuilder(G_BRCOND)
       .legalFor({XLenLLT})
       .minScalar(0, XLenLLT);
 
   getActionDefinitionsBuilder(G_PHI)
       .legalFor({p0, XLenLLT})
       .widenScalarToNextPow2(0)
       .clampScalar(0, XLenLLT, XLenLLT);
 
   getLegacyLegalizerInfo().computeTables();
 }

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-select.mir

bb.0.entry:
     %z:_(s96) = G_SELECT %c(s1), %x(s96), %y
     %zhi:_(s32), %zmid:_(s32), %zlo:_(s32) = G_UNMERGE_VALUES %y(s96)
     $x10 = COPY %zhi(s32)
     $x11 = COPY %zmid(s32)
     $x12 = COPY %zlo(s32)
     PseudoRET implicit $x10, implicit $x11, implicit $x12
 
 ...
+---
+name:            select_ptr
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: select_ptr
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x10 = COPY [[SELECT]](p0)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(p0) = COPY $x11
+    %2:_(s32) = COPY $x12
+    %3:_(s1) = G_TRUNC %2(s32)
+    %4:_(p0) = G_SELECT %3(s1), %0(p0), %1(p0)
+    $x10 = COPY %4(p0)
+    PseudoRET implicit $x10
+
+...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-select.mir

bb.0.entry:
     %z:_(s192) = G_SELECT %c(s1), %x(s192), %y
     %zhi:_(s64), %zmid:_(s64), %zlo:_(s64) = G_UNMERGE_VALUES %y(s192)
     $x10 = COPY %zhi(s64)
     $x11 = COPY %zmid(s64)
     $x12 = COPY %zlo(s64)
     PseudoRET implicit $x10, implicit $x11, implicit $x12
 
 ...
+---
+name:            select_ptr
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: select_ptr
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s64), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x10 = COPY [[SELECT]](p0)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(p0) = COPY $x11
+    %2:_(s64) = COPY $x12
+    %3:_(s1) = G_TRUNC %2(s64)
+    %4:_(p0) = G_SELECT %3(s1), %0(p0), %1(p0)
+    $x10 = COPY %4(p0)
+    PseudoRET implicit $x10
+
+...