[GlobalISel] Also set dead flags of implicit defs added by BuildMI

[Pierre-vh]

Summary

BuildMI automatically adds the implicit operands of the
instruction. This meant we couldn''t set the dead flag on
dead implicit defs in that case.

Fix it by introducing an opcode to mark a given implicit
def as dead.

Fixes #64565

[Pierre-vh]

Remove useless new testcase

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

989

There should be an implicit_defs() that needs no conditions inside the loop

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir

99

Lost comment

575

More lost comments

[Pierre-vh]

Address comments

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

348

Alternatively could give the operand index directly, it should know

llvm/utils/TableGen/GlobalISelMatchTable.cpp

1973–1974

namespace defined twice identically?

1976

Could just emit the operand index, can do that in a follow up if you want

[Pierre-vh]

Use implicit op idx

I don't use the true op idx because it's hard (impossible?) to tell from TableGen, considering we can have complex renderers & such.

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

enum {
   /// - InsnID - Instruction ID to modify
   /// - RegNum - The register to add
   GIR_AddImplicitUse,
   /// Add an register to the specified instruction
   /// - InsnID - Instruction ID to modify
   /// - RegNum - The register to add
   GIR_AddRegister,
 
+  /// Marks the implicit def of a register as dead.
+  /// - InsnID - Instruction ID to modify
+  /// - OpIdx - The implicit def operand index
+  ///
+  /// OpIdx starts at 0 for the first implicit def.
+  GIR_SetImplicitDefDead,
+
   /// Add a temporary register to the specified instruction
   /// - InsnID - Instruction ID to modify
   /// - TempRegID - The temporary register ID to add
   /// - TempRegFlags - The register flags to set
   GIR_AddTempRegister,
 
   /// Add a temporary register to the specified instruction
   /// - InsnID - Instruction ID to modify

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

case GIR_AddRegister: {
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       OutMIs[InsnID].addReg(RegNum, RegFlags);
       DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs()
                           << CurrentIdx << ": GIR_AddRegister(OutMIs[" << InsnID
                           << "], " << RegNum << ", " << RegFlags << ")\n");
       break;
     }
-
+    case GIR_SetImplicitDefDead: {
+      int64_t InsnID = MatchTable[CurrentIdx++];
+      int64_t OpIdx = MatchTable[CurrentIdx++];
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
+                      dbgs() << CurrentIdx << ": GIR_SetImplicitDefDead(OutMIs["
+                             << InsnID << "], OpIdx=" << OpIdx << ")\n");
+      MachineInstr *MI = OutMIs[InsnID];
+      assert(MI && "Modifying undefined instruction");
+      MI->getOperand(MI->getNumExplicitOperands() + OpIdx).setIsDead();
+      break;
+    }
     case GIR_AddTempRegister:
     case GIR_AddTempSubRegister: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t TempRegID = MatchTable[CurrentIdx++];
       uint64_t TempRegFlags = MatchTable[CurrentIdx++];
       unsigned SubReg = 0;
       if (MatcherOpcode == GIR_AddTempSubRegister)
         SubReg = MatchTable[CurrentIdx++];

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir

bb.0:
     ; LOWER: liveins: $x0, $x1
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %reg:_(s64) = COPY $x0
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_sextinreg_lhs
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %reg:gpr64all = COPY $x0
     ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
     ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
     ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
     ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv
bb.0:
     ; LOWER: liveins: $x0, $x1
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %reg0:_(s64) = COPY $x0
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg0, 8
     ; LOWER-NEXT: %add:_(s64) = G_ADD %cmp_lhs, %reg0
     ; LOWER-NEXT: %cmp2:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %add
     ; LOWER-NEXT: $w0 = COPY %cmp2(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: dont_swap_more_than_one_use
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
     ; SELECT-NEXT: %cmp_lhs:gpr64 = SBFMXri %reg0, 0, 7
     ; SELECT-NEXT: %add:gpr64 = ADDXrr %cmp_lhs, %reg0
     ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %add, implicit-def $nzcv
     ; SELECT-NEXT: %cmp2:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv

 ...
 ---
 name:            dont_swap_legal_arith_immed_on_rhs
 legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; Arithmetic immediates can be folded into compares. If we have one, then
     ; don't bother changing anything.
 
     ; LOWER-LABEL: name: dont_swap_legal_arith_immed_on_rhs
     ; LOWER: liveins: $x0, $x1
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %reg:_(s64) = COPY $x0
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
     ; LOWER-NEXT: %cmp_rhs:_(s64) = G_CONSTANT i64 12
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: dont_swap_legal_arith_immed_on_rhs
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %reg:gpr64 = COPY $x0
     ; SELECT-NEXT: %cmp_lhs:gpr64common = SBFMXri %reg, 0, 7
     ; SELECT-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %cmp_lhs, 12, 0, implicit-def $nzcv
     ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
     ; SELECT-NEXT: $w0 = COPY %cmp
bb.0:
     ; LOWER: liveins: $x0, $x1
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %reg:_(s64) = COPY $x0
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SEXT_INREG %reg, 8
     ; LOWER-NEXT: %cmp_rhs:_(s64) = G_CONSTANT i64 1234567
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_non_arith_immed_on_rhs
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %reg:gpr64all = COPY $x0
     ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
     ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
     ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234567
     ; SELECT-NEXT: %cmp_rhs:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
bb.0:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 255
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_and_lhs_0xFF
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
     ; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
     ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
     ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
     ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 0, implicit-def $nzcv
bb.0:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 65535
     ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_and_lhs_0xFFFF
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
     ; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
     ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
     ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
     ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 8, implicit-def $nzcv
bb.0:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 4294967295
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %cst
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sle), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_and_lhs_0xFFFFFFFF
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
     ; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
     ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
     ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
     ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 16, implicit-def $nzcv
bb.0:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %and_lhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %not_an_extend_mask:_(s64) = G_CONSTANT i64 7
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_AND %and_lhs, %not_an_extend_mask
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sge), %cmp_lhs(s64), %cmp_rhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: dont_swap_and_lhs_wrong_mask
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
     ; SELECT-NEXT: %and_lhs:gpr64 = COPY $x0
     ; SELECT-NEXT: %cmp_lhs:gpr64common = ANDXri %and_lhs, 4098
     ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
     ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
bb.0:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_shl_lhs
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
     ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0
     ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %shl_lhs, 1, implicit-def $nzcv
     ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; SELECT-NEXT: $w0 = COPY %cmp
bb.0:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %ashr_lhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_ASHR %ashr_lhs, %cst(s64)
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_ashr_lhs
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
     ; SELECT-NEXT: %ashr_lhs:gpr64 = COPY $x0
     ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %ashr_lhs, 129, implicit-def $nzcv
     ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; SELECT-NEXT: $w0 = COPY %cmp
bb.0:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %lshr_lhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 1
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_LSHR %lshr_lhs, %cst(s64)
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(sgt), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_lshr_lhs
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
     ; SELECT-NEXT: %lshr_lhs:gpr64 = COPY $x0
     ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_rhs, %lshr_lhs, 65, implicit-def $nzcv
     ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; SELECT-NEXT: $w0 = COPY %cmp
bb.0:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %too_large:_(s64) = G_CONSTANT i64 64
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %shl_lhs, %too_large(s64)
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: dont_swap_shift_s64_cst_too_large
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
     ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0
     ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 64
     ; SELECT-NEXT: %too_large:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
     ; SELECT-NEXT: %cmp_lhs:gpr64 = LSLVXr %shl_lhs, %too_large
bb.0:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s32) = COPY $w1
     ; LOWER-NEXT: %shl_lhs:_(s32) = COPY $w0
     ; LOWER-NEXT: %cst:_(s32) = G_CONSTANT i32 32
     ; LOWER-NEXT: %cmp_lhs:_(s32) = G_SHL %shl_lhs, %cst(s32)
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s32), %cmp_rhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: dont_swap_shift_s32_cst_too_large
     ; SELECT: liveins: $w0, $w1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr32 = COPY $w1
     ; SELECT-NEXT: %shl_lhs:gpr32 = COPY $w0
     ; SELECT-NEXT: %cst:gpr32 = MOVi32imm 32
     ; SELECT-NEXT: %cmp_lhs:gpr32 = LSLVWr %shl_lhs, %cst
     ; SELECT-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
bb.0.entry:
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %sub_rhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_lhs(s64), %cmp_rhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: dont_swap_cmn_lhs_no_folding_opportunities
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
     ; SELECT-NEXT: %sub_rhs:gpr64 = COPY $x0
     ; SELECT-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %sub_rhs, %cmp_rhs, implicit-def $nzcv
     ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
     ; SELECT-NEXT: $w0 = COPY %cmp

 ---
 name:            swap_cmn_lhs
 legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $x0, $x1
 
     ; Swap when we can see a constant folding opportunity through the sub on
     ; the LHS.
 
 
     ; LOWER-LABEL: name: swap_cmn_lhs
     ; LOWER: liveins: $x0, $x1
     ; LOWER-NEXT: {{  $}}
     ; LOWER-NEXT: %cmp_rhs:_(s64) = COPY $x1
     ; LOWER-NEXT: %shl_lhs:_(s64) = COPY $x0
     ; LOWER-NEXT: %zero:_(s64) = G_CONSTANT i64 0
     ; LOWER-NEXT: %cst:_(s64) = G_CONSTANT i64 63
     ; LOWER-NEXT: %sub_rhs:_(s64) = G_SHL %shl_lhs, %cst(s64)
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SUB %zero, %sub_rhs
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(ne), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_cmn_lhs
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1
     ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0
     ; SELECT-NEXT: [[ADDSXrs:%[0-9]+]]:gpr64 = ADDSXrs %cmp_rhs, %shl_lhs, 63, implicit-def $nzcv
     ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
     ; SELECT-NEXT: $w0 = COPY %cmp
bb.0.entry:
     ; LOWER-NEXT: %reg1:_(s64) = COPY $x1
     ; LOWER-NEXT: %sext_in_reg:_(s64) = G_SEXT_INREG %reg1, 1
     ; LOWER-NEXT: %ashr_cst:_(s64) = G_CONSTANT i64 3
     ; LOWER-NEXT: %ashr:_(s64) = G_ASHR %sext_in_reg, %ashr_cst(s64)
     ; LOWER-NEXT: %cmp_rhs:_(s64) = G_SUB %zero, %ashr
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: dont_swap_cmn_lhs_when_rhs_more_profitable
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %zero:gpr64 = COPY $xzr
     ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
     ; SELECT-NEXT: %shl:gpr64 = UBFMXri %reg0, 1, 0
     ; SELECT-NEXT: %reg1:gpr64 = COPY $x1
     ; SELECT-NEXT: %sext_in_reg:gpr64 = SBFMXri %reg1, 0, 0
-    ; SELECT-NEXT: %cmp_rhs:gpr64 = SUBSXrs %zero, %sext_in_reg, 131, implicit-def $nzcv
+    ; SELECT-NEXT: %cmp_rhs:gpr64 = SUBSXrs %zero, %sext_in_reg, 131, implicit-def dead $nzcv
     ; SELECT-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr %shl, %cmp_rhs, implicit-def $nzcv
     ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; SELECT-NEXT: $w0 = COPY %cmp
     ; SELECT-NEXT: RET_ReallyLR implicit $w0
     %zero:_(s64) = G_CONSTANT i64 0
 
     %reg0:_(s64) = COPY $x0
     %shl_cst:_(s64) = G_CONSTANT i64 63
bb.0:
     ; LOWER-NEXT: %reg1:_(s64) = COPY $x1
     ; LOWER-NEXT: %and_mask:_(s64) = G_CONSTANT i64 255
     ; LOWER-NEXT: %and:_(s64) = G_AND %reg1, %and_mask
     ; LOWER-NEXT: %rhs_cst:_(s64) = G_CONSTANT i64 1
     ; LOWER-NEXT: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_lhs(s64), %cmp_rhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: dont_swap_rhs_with_supported_extend
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
     ; SELECT-NEXT: %cmp_lhs:gpr64 = UBFMXri %reg0, 63, 62
     ; SELECT-NEXT: %reg1:gpr64 = COPY $x1
     ; SELECT-NEXT: %and:gpr64common = ANDXri %reg1, 4103
     ; SELECT-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %cmp_lhs, %and, 129, implicit-def $nzcv
bb.0:
     ; LOWER-NEXT: %and:_(s64) = G_AND %reg0, %and_mask
     ; LOWER-NEXT: %lhs_cst:_(s64) = G_CONSTANT i64 1
     ; LOWER-NEXT: %cmp_lhs:_(s64) = G_SHL %and, %lhs_cst(s64)
     ; LOWER-NEXT: %rhs_cst:_(s64) = G_CONSTANT i64 5
     ; LOWER-NEXT: %cmp_rhs:_(s64) = G_ASHR %and, %rhs_cst(s64)
     ; LOWER-NEXT: %cmp:_(s32) = G_ICMP intpred(slt), %cmp_rhs(s64), %cmp_lhs
     ; LOWER-NEXT: $w0 = COPY %cmp(s32)
     ; LOWER-NEXT: RET_ReallyLR implicit $w0
+    ;
     ; SELECT-LABEL: name: swap_rhs_with_supported_extend
     ; SELECT: liveins: $x0, $x1
     ; SELECT-NEXT: {{  $}}
     ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
     ; SELECT-NEXT: %and:gpr64common = ANDXri %reg0, 4103
     ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg0.sub_32
     ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
     ; SELECT-NEXT: %cmp_rhs:gpr64common = SBFMXri %and, 5, 63

llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 ---
 name:            add_sext_s32_to_s64
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $x2
     ; CHECK-LABEL: name: add_sext_s32_to_s64
     ; CHECK: liveins: $w1, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr64sp = COPY $x2
-    ; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 48
-    ; CHECK: $x3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x2
+    ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 48
+    ; CHECK-NEXT: $x3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $x3
     %1:gpr(s32) = COPY $w1
     %ext:gpr(s64) = G_SEXT %1(s32)
     %add_lhs:gpr(s64) = COPY $x2
     %res:gpr(s64) = G_ADD %add_lhs, %ext
     $x3 = COPY %res(s64)
     RET_ReallyLR implicit $x3
 ...
 ---
 name:            add_and_s32_to_s64
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x1, $x2
     ; CHECK-LABEL: name: add_and_s32_to_s64
     ; CHECK: liveins: $x1, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x1
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
-    ; CHECK: %add_lhs:gpr64sp = COPY $x2
-    ; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16
-    ; CHECK: $x3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x1
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
+    ; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x2
+    ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16
+    ; CHECK-NEXT: $x3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $x3
     %1:gpr(s64) = COPY $x1
     %mask:gpr(s64) = G_CONSTANT i64 4294967295 ; 0xffff
     %ext:gpr(s64) = G_AND %1(s64), %mask
     %add_lhs:gpr(s64) = COPY $x2
     %res:gpr(s64) = G_ADD %add_lhs, %ext
     $x3 = COPY %res(s64)
     RET_ReallyLR implicit $x3
 ...
 ---
 name:            add_sext_s16_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_sext_s16_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 40
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 40
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s16) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_SEXT %1(s16)
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            add_zext_s16_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_zext_s16_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s16) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_ZEXT %1(s16)
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            add_anyext_s16_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_anyext_s16_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s16) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_ANYEXT %1(s16)
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            add_and_s16_to_s32_uxtb
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_and_s16_to_s32_uxtb
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %1:gpr(s32) = COPY $w1
     %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
     %ext:gpr(s32) = G_AND %1(s32), %mask
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            add_and_s16_to_s32_uxth
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_and_s16_to_s32_uxth
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %1:gpr(s32) = COPY $w1
     %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
     %ext:gpr(s32) = G_AND %1(s32), %mask
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            add_sext_s8_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_sext_s8_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s8) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_SEXT %1(s8)
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            add_zext_s8_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_zext_s8_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s8) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_ZEXT %1(s8)
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            add_anyext_s8_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_anyext_s8_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s8) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_ANYEXT %1(s8)
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            add_sext_with_shl
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_sext_with_shl
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s16) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_SEXT %1(s16)
     %imm:gpr(s32) = G_CONSTANT i32 3
     %shl:gpr(s32) = G_SHL %ext, %imm
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %shl
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            add_and_with_shl
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: add_and_with_shl
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: %add_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %1:gpr(s32) = COPY $w1
     %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
     %ext:gpr(s32) = G_AND %1(s32), %mask
     %imm:gpr(s32) = G_CONSTANT i32 3
     %shl:gpr(s32) = G_SHL %ext, %imm
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %shl
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            dont_fold_invalid_mask
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     ; Check that we only fold when we have a supported AND mask.
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: dont_fold_invalid_mask
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: %mask:gpr32 = MOVi32imm 42
-    ; CHECK: %ext:gpr32 = ANDWrr [[COPY]], %mask
-    ; CHECK: %add_lhs:gpr32 = COPY $w2
-    ; CHECK: %res:gpr32 = ADDWrr %add_lhs, %ext
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: %mask:gpr32 = MOVi32imm 42
+    ; CHECK-NEXT: %ext:gpr32 = ANDWrr [[COPY]], %mask
+    ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = ADDWrr %add_lhs, %ext
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %1:gpr(s32) = COPY $w1
     %mask:gpr(s32) = G_CONSTANT i32 42
     %ext:gpr(s32) = G_AND %1(s32), %mask
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            dont_fold_invalid_shl
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: dont_fold_invalid_shl
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %ext:gpr32 = SBFMWri %wide_1, 0, 15
-    ; CHECK: %add_lhs:gpr32 = COPY $w2
-    ; CHECK: %res:gpr32 = ADDWrs %add_lhs, %ext, 5
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %ext:gpr32 = SBFMWri %wide_1, 0, 15
+    ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = ADDWrs %add_lhs, %ext, 5
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s16) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_SEXT %1(s16)
     %imm:gpr(s32) = G_CONSTANT i32 5
     %shl:gpr(s32) = G_SHL %ext, %imm
     %add_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_ADD %add_lhs, %shl
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            sub_sext_s32_to_s64
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $x2
     ; CHECK-LABEL: name: sub_sext_s32_to_s64
     ; CHECK: liveins: $w1, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr64sp = COPY $x2
-    ; CHECK: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def $nzcv
-    ; CHECK: $x3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr64sp = COPY $x2
+    ; CHECK-NEXT: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def dead $nzcv
+    ; CHECK-NEXT: $x3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $x3
     %1:gpr(s32) = COPY $w1
     %ext:gpr(s64) = G_SEXT %1(s32)
     %sub_lhs:gpr(s64) = COPY $x2
     %res:gpr(s64) = G_SUB %sub_lhs, %ext
     $x3 = COPY %res(s64)
     RET_ReallyLR implicit $x3
 ...
 ---
 name:            sub_sext_s16_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: sub_sext_s16_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def $nzcv
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s16) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_SEXT %1(s16)
     %sub_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_SUB %sub_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            sub_zext_s16_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: sub_zext_s16_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def $nzcv
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s16) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_ZEXT %1(s16)
     %sub_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_SUB %sub_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            sub_anyext_s16_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: sub_anyext_s16_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def $nzcv
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s16) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_ANYEXT %1(s16)
     %sub_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_SUB %sub_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            sub_and_s16_to_s32_uxtb
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: sub_and_s16_to_s32_uxtb
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def $nzcv
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %1:gpr(s32) = COPY $w1
     %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
     %ext:gpr(s32) = G_AND %1(s32), %mask
     %sub_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_SUB %sub_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            sub_and_s16_to_s32_uxth
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: sub_and_s16_to_s32_uxth
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def $nzcv
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %1:gpr(s32) = COPY $w1
     %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
     %ext:gpr(s32) = G_AND %1(s32), %mask
     %sub_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_SUB %sub_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ---

 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: sub_zext_s8_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def $nzcv
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s8) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_ZEXT %1(s8)
     %sub_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_SUB %sub_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            sub_anyext_s8_to_s32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: sub_anyext_s8_to_s32
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def $nzcv
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s8) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_ANYEXT %1(s8)
     %sub_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_SUB %sub_lhs, %ext
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ---
 ...
 ---
 name:            sub_sext_with_shl
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: sub_sext_with_shl
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: %wide_1:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def $nzcv
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %wide_1:gpr(s32) = COPY $w1
     %1:gpr(s16) = G_TRUNC %wide_1
     %ext:gpr(s32) = G_SEXT %1(s16)
     %imm:gpr(s32) = G_CONSTANT i32 3
     %shl:gpr(s32) = G_SHL %ext, %imm
     %sub_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_SUB %sub_lhs, %shl
     $w3 = COPY %res(s32)
     RET_ReallyLR implicit $w3
 ...
 ---
 name:            sub_and_with_shl
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $w1, $w2, $x2
     ; CHECK-LABEL: name: sub_and_with_shl
     ; CHECK: liveins: $w1, $w2, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
-    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def $nzcv
-    ; CHECK: $w3 = COPY %res
-    ; CHECK: RET_ReallyLR implicit $w3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
+    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w3 = COPY %res
+    ; CHECK-NEXT: RET_ReallyLR implicit $w3
     %1:gpr(s32) = COPY $w1
     %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
     %ext:gpr(s32) = G_AND %1(s32), %mask
     %imm:gpr(s32) = G_CONSTANT i32 3
     %shl:gpr(s32) = G_SHL %ext, %imm
     %sub_lhs:gpr(s32) = COPY $w2
     %res:gpr(s32) = G_SUB %sub_lhs, %shl
     $w3 = COPY %res(s32)
liveins:
   - { reg: '$w1' }
   - { reg: '$x2' }
 body:             |
   bb.1.entry:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: store_16b_zext
     ; CHECK: liveins: $x0, $x1, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
-    ; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15
-    ; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
-    ; CHECK: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
-    ; CHECK: RET_ReallyLR
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
+    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
+    ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
+    ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
+    ; CHECK-NEXT: RET_ReallyLR
     %0:gpr(p0) = COPY $x0
     %1:gpr(s32) = COPY $w1
     %2:gpr(p0) = COPY $x2
     %small:gpr(s16) = G_TRUNC %1
     %zext:gpr(s64) = G_ZEXT %small(s16)
     %cst:gpr(s64) = G_CONSTANT i64 3
     %shl:gpr(s64) = G_SHL %zext, %cst(s64)
     %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
liveins:
   - { reg: '$w1' }
   - { reg: '$x2' }
 body:             |
   bb.1.entry:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: store_8b_zext
     ; CHECK: liveins: $x0, $x1, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
-    ; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7
-    ; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
-    ; CHECK: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
-    ; CHECK: RET_ReallyLR
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
+    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
+    ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
+    ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
+    ; CHECK-NEXT: RET_ReallyLR
     %0:gpr(p0) = COPY $x0
     %1:gpr(s32) = COPY $w1
     %2:gpr(p0) = COPY $x2
     %small:gpr(s8) = G_TRUNC %1
     %zext:gpr(s64) = G_ZEXT %small(s8)
     %cst:gpr(s64) = G_CONSTANT i64 3
     %shl:gpr(s64) = G_SHL %zext, %cst(s64)
     %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
liveins:
   - { reg: '$w1' }
   - { reg: '$x2' }
 body:             |
   bb.1.entry:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: store_16b_sext
     ; CHECK: liveins: $x0, $x1, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
-    ; CHECK: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15
-    ; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
-    ; CHECK: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
-    ; CHECK: RET_ReallyLR
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
+    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
+    ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
+    ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
+    ; CHECK-NEXT: RET_ReallyLR
     %0:gpr(p0) = COPY $x0
     %1:gpr(s32) = COPY $w1
     %2:gpr(p0) = COPY $x2
     %small:gpr(s16) = G_TRUNC %1
     %zext:gpr(s64) = G_SEXT %small(s16)
     %cst:gpr(s64) = G_CONSTANT i64 3
     %shl:gpr(s64) = G_SHL %zext, %cst(s64)
     %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
liveins:
   - { reg: '$w1' }
   - { reg: '$x2' }
 body:             |
   bb.1.entry:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: store_8b_sext
     ; CHECK: liveins: $x0, $x1, $x2
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
-    ; CHECK: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7
-    ; CHECK: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
-    ; CHECK: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
-    ; CHECK: RET_ReallyLR
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
+    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
+    ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
+    ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
+    ; CHECK-NEXT: RET_ReallyLR
     %0:gpr(p0) = COPY $x0
     %1:gpr(s32) = COPY $w1
     %2:gpr(p0) = COPY $x2
     %small:gpr(s8) = G_TRUNC %1
     %zext:gpr(s64) = G_SEXT %small(s8)
     %cst:gpr(s64) = G_CONSTANT i64 3
     %shl:gpr(s64) = G_SHL %zext, %cst(s64)
     %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
     G_STORE %2(p0), %gep(p0) :: (store (p0))
     RET_ReallyLR
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 ---
 name:            add_shl_s64_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: add_shl_s64_rhs
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 8
-    ; CHECK: $x0 = COPY [[ADDXrs]]
-    ; CHECK: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 8
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 8
     %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
     %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
     $x0 = COPY %3:gpr(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            add_shl_s64_lhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; CHECK-LABEL: name: add_shl_s64_lhs
     ; CHECK: liveins: $x0, $x1
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 8
-    ; CHECK: $x0 = COPY [[ADDXrs]]
-    ; CHECK: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 8
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %4:gpr(s64) = COPY $x1
     %1:gpr(s64) = G_CONSTANT i64 8
     %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
     %3:gpr(s64) = G_ADD %2, %4:gpr(s64)
     $x0 = COPY %3:gpr(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            sub_shl_s64_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: sub_shl_s64_rhs
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 8, implicit-def $nzcv
-    ; CHECK: $x0 = COPY [[SUBSXrs]]
-    ; CHECK: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv
+    ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 8
     %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
     %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
     $x0 = COPY %3:gpr(s64)
     RET_ReallyLR implicit $x0
 
 ---

 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; CHECK-LABEL: name: add_lshr_s64_lhs
     ; CHECK: liveins: $x0, $x1
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: %param2:gpr64 = COPY $x1
-    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 72
-    ; CHECK: $x0 = COPY [[ADDXrs]]
-    ; CHECK: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: %param2:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 72
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %param2:gpr(s64) = COPY $x1
     %1:gpr(s64) = G_CONSTANT i64 8
     %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
     %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)
     $x0 = COPY %3:gpr(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            sub_lshr_s64_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: sub_lshr_s64_rhs
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 72, implicit-def $nzcv
-    ; CHECK: $x0 = COPY [[SUBSXrs]]
-    ; CHECK: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv
+    ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 8
     %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
     %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
     $x0 = COPY %3:gpr(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            add_ashr_s64_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: add_ashr_s64_rhs
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 136
-    ; CHECK: $x0 = COPY [[ADDXrs]]
-    ; CHECK: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 136
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 8
     %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
     %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
     $x0 = COPY %3:gpr(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            add_ashr_s64_lhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; CHECK-LABEL: name: add_ashr_s64_lhs
     ; CHECK: liveins: $x0, $x1
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: %param2:gpr64 = COPY $x1
-    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 136
-    ; CHECK: $x0 = COPY [[ADDXrs]]
-    ; CHECK: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: %param2:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 136
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %param2:gpr(s64) = COPY $x1
     %1:gpr(s64) = G_CONSTANT i64 8
     %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
     %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)
     $x0 = COPY %3:gpr(s64)
     RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            sub_ashr_s64_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $x0
     ; CHECK-LABEL: name: sub_ashr_s64_rhs
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 136, implicit-def $nzcv
-    ; CHECK: $x0 = COPY [[SUBSXrs]]
-    ; CHECK: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv
+    ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 8
     %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
     %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
     $x0 = COPY %3:gpr(s64)
     RET_ReallyLR implicit $x0
 
 ---

 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: add_shl_s32_lhs
     ; CHECK: liveins: $w0, $w1
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: %param2:gpr32 = COPY $w1
-    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 8
-    ; CHECK: $w0 = COPY [[ADDWrs]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: %param2:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 8
+    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %param2:gpr(s32) = COPY $w1
     %1:gpr(s32) = G_CONSTANT i32 8
     %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
     %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
     $w0 = COPY %3:gpr(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            sub_shl_s32_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0
     ; CHECK-LABEL: name: sub_shl_s32_rhs
     ; CHECK: liveins: $w0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 8, implicit-def $nzcv
-    ; CHECK: $w0 = COPY [[SUBSWrs]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 8
     %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
     %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
     $w0 = COPY %3:gpr(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            add_lshr_s32_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0
     ; CHECK-LABEL: name: add_lshr_s32_rhs
     ; CHECK: liveins: $w0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 72
-    ; CHECK: $w0 = COPY [[ADDWrs]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 72
+    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 8
     %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
     %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
     $w0 = COPY %3:gpr(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            add_lshr_s32_lhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: add_lshr_s32_lhs
     ; CHECK: liveins: $w0, $w1
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: %param2:gpr32 = COPY $w1
-    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 72
-    ; CHECK: $w0 = COPY [[ADDWrs]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: %param2:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 72
+    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %param2:gpr(s32) = COPY $w1
     %1:gpr(s32) = G_CONSTANT i32 8
     %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
     %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
     $w0 = COPY %3:gpr(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            sub_lshr_s32_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0
     ; CHECK-LABEL: name: sub_lshr_s32_rhs
     ; CHECK: liveins: $w0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 72, implicit-def $nzcv
-    ; CHECK: $w0 = COPY [[SUBSWrs]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 8
     %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
     %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
     $w0 = COPY %3:gpr(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            add_ashr_s32_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0
     ; CHECK-LABEL: name: add_ashr_s32_rhs
     ; CHECK: liveins: $w0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 136
-    ; CHECK: $w0 = COPY [[ADDWrs]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 136
+    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 8
     %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
     %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
     $w0 = COPY %3:gpr(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            add_ashr_s32_lhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: add_ashr_s32_lhs
     ; CHECK: liveins: $w0, $w1
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: %param2:gpr32 = COPY $w1
-    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 136
-    ; CHECK: $w0 = COPY [[ADDWrs]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: %param2:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 136
+    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %param2:gpr(s32) = COPY $w1
     %1:gpr(s32) = G_CONSTANT i32 8
     %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
     %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
     $w0 = COPY %3:gpr(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            sub_ashr_s32_rhs
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0
     ; CHECK-LABEL: name: sub_ashr_s32_rhs
     ; CHECK: liveins: $w0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 136, implicit-def $nzcv
-    ; CHECK: $w0 = COPY [[SUBSWrs]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 8
     %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
     %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
     $w0 = COPY %3:gpr(s32)
     RET_ReallyLR implicit $w0

llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir

registers:
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: add_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
-    ; CHECK: $w0 = COPY [[ADDWrr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_ADD %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as add_s32_gpr, for 64-bit operations.
 name:            add_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: add_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[ADDXrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_ADD %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 name:            add_imm_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: add_imm_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-    ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
-    ; CHECK: $w0 = COPY [[ADDWri]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
+    ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
+    ; CHECK-NEXT: $w0 = COPY [[ADDWri]]
     %0(s32) = COPY $w0
     %1(s32) = G_CONSTANT i32 1
     %2(s32) = G_ADD %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 name:            add_imm_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $w1
 
     ; CHECK-LABEL: name: add_imm_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
-    ; CHECK: $x0 = COPY [[ADDXri]]
+    ; CHECK: liveins: $x0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
+    ; CHECK-NEXT: $x0 = COPY [[ADDXri]]
     %0(s64) = COPY $x0
     %1(s64) = G_CONSTANT i64 1
     %2(s64) = G_ADD %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 name:            add_neg_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w1, $w2
     ; We should be able to turn the ADD into a SUB.
     ; CHECK-LABEL: name: add_neg_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w1
-    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
-    ; CHECK: $w2 = COPY [[SUBSWri]]
+    ; CHECK: liveins: $w1, $w2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w1
+    ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def dead $nzcv
+    ; CHECK-NEXT: $w2 = COPY [[SUBSWri]]
     %0(s32) = COPY $w1
     %1(s32) = G_CONSTANT i32 -1
     %2(s32) = G_ADD %0, %1
     $w2 = COPY %2(s32)
 ...
 
 ---
 name:            add_neg_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; We should be able to turn the ADD into a SUB.
     ; CHECK-LABEL: name: add_neg_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 0, implicit-def $nzcv
-    ; CHECK: $x0 = COPY [[SUBSXri]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 0, implicit-def dead $nzcv
+    ; CHECK-NEXT: $x0 = COPY [[SUBSXri]]
     %0(s64) = COPY $x0
     %1(s64) = G_CONSTANT i64 -1
     %2(s64) = G_ADD %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 name:            add_neg_invalid_immed_s32
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; We can't select this if the value is out of range.
     ; CHECK-LABEL: name: add_neg_invalid_immed_s32
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000
-    ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]
-    ; CHECK: $x0 = COPY [[ADDXrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000
+    ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
     %0(s64) = COPY $x0
     %1(s64) = G_CONSTANT i64 -5000
     %2(s64) = G_ADD %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 name:            add_neg_invalid_immed_s64
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; We can't select this if the value is out of range.
     ; CHECK-LABEL: name: add_neg_invalid_immed_s64
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000
-    ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]
-    ; CHECK: $x0 = COPY [[ADDXrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000
+    ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
     %0(s64) = COPY $x0
     %1(s64) = G_CONSTANT i64 -5000
     %2(s64) = G_ADD %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 name:            add_imm_0_s32
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; We shouldn't get a SUB here, because "cmp wN, $0" and "cmp wN, #0" have
     ; opposite effects on the C flag.
     ; CHECK-LABEL: name: add_imm_0_s32
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0
-    ; CHECK: $x0 = COPY [[ADDXri]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0
+    ; CHECK-NEXT: $x0 = COPY [[ADDXri]]
     %0(s64) = COPY $x0
     %1(s64) = G_CONSTANT i64 0
     %2(s64) = G_ADD %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 name:            add_imm_0_s64
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
     ; We shouldn't get a SUB here, because "cmp xN, $0" and "cmp xN, #0" have
     ; opposite effects on the C flag.
     ; CHECK-LABEL: name: add_imm_0_s64
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0
-    ; CHECK: $x0 = COPY [[ADDXri]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0
+    ; CHECK-NEXT: $x0 = COPY [[ADDXri]]
     %0(s64) = COPY $x0
     %1(s64) = G_CONSTANT i64 0
     %2(s64) = G_ADD %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 name:            add_imm_s32_gpr_bb
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   ; CHECK-LABEL: name: add_imm_s32_gpr_bb
   ; CHECK: bb.0:
-  ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-  ; CHECK:   B %bb.1
-  ; CHECK: bb.1:
-  ; CHECK:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
-  ; CHECK:   $w0 = COPY [[ADDWri]]
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $w0, $w1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
+  ; CHECK-NEXT:   $w0 = COPY [[ADDWri]]
   bb.0:
     liveins: $w0, $w1
     successors: %bb.1
 
     %0(s32) = COPY $w0
     %1(s32) = G_CONSTANT i32 1
     G_BR %bb.1
 
registers:
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sub_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
-    ; CHECK: $w0 = COPY [[SUBSWrr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
+    ; CHECK-NEXT: $w0 = COPY [[SUBSWrr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_SUB %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as add_s64_gpr, for G_SUB operations.
 name:            sub_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: sub_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
-    ; CHECK: $x0 = COPY [[SUBSXrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv
+    ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_SUB %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 # Same as add_s32_gpr, for G_OR operations.
 name:            or_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: or_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]
-    ; CHECK: $w0 = COPY [[ORRWrr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $w0 = COPY [[ORRWrr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_OR %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as add_s64_gpr, for G_OR operations.
 name:            or_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: or_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[ORRXrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[ORRXrr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_OR %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 # 64-bit G_OR on vector registers.
 name:            or_v2s32_fpr
 legalized:       true
 regBankSelected: true
 #
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 # The actual OR does not matter as long as it is operating
 # on 64-bit width vector.
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: or_v2s32_fpr
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
-    ; CHECK: $d0 = COPY [[ORRv8i8_]]
+    ; CHECK: liveins: $d0, $d1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]]
       %0(<2 x s32>) = COPY $d0
       %1(<2 x s32>) = COPY $d1
       %2(<2 x s32>) = G_OR %0, %1
       $d0 = COPY %2(<2 x s32>)
 ...
 
 ---
 # Same as add_s32_gpr, for G_AND operations.
 name:            and_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: and_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]
-    ; CHECK: $w0 = COPY [[ANDWrr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $w0 = COPY [[ANDWrr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_AND %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as add_s64_gpr, for G_AND operations.
 name:            and_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: and_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[ANDXrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[ANDXrr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_AND %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 # Same as add_s32_gpr, for G_SHL operations.
 name:            shl_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: shl_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]
-    ; CHECK: $w0 = COPY [[LSLVWr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $w0 = COPY [[LSLVWr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_SHL %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 name:            shl_s32_64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $x1
 
     ; CHECK-LABEL: name: shl_s32_64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x1
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32
-    ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]]
-    ; CHECK: $w0 = COPY [[LSLVWr]]
+    ; CHECK: liveins: $w0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $x1
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32
+    ; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]]
+    ; CHECK-NEXT: $w0 = COPY [[LSLVWr]]
     %0(s32) = COPY $w0
     %1(s64) = COPY $x1
     %2(s32) = G_SHL %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as add_s64_gpr, for G_SHL operations.
 name:            shl_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: shl_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[LSLVXr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[LSLVXr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_SHL %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 # Same as add_s32_gpr, for G_LSHR operations.
 name:            lshr_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: lshr_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
-    ; CHECK: $w0 = COPY [[LSRVWr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $w0 = COPY [[LSRVWr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_LSHR %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as add_s64_gpr, for G_LSHR operations.
 name:            lshr_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: lshr_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[LSRVXr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[LSRVXr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_LSHR %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 # Same as add_s32_gpr, for G_ASHR operations.
 name:            ashr_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ashr_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
-    ; CHECK: $w0 = COPY [[ASRVWr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $w0 = COPY [[ASRVWr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_ASHR %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as add_s64_gpr, for G_ASHR operations.
 name:            ashr_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: ashr_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[ASRVXr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[ASRVXr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_ASHR %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 # Check that we select s32 GPR G_MUL. This is trickier than other binops because
 # there is only MADDWrrr, and we have to use the WZR physreg.
 name:            mul_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: mul_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
-    ; CHECK: $w0 = COPY [[MADDWrrr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr
+    ; CHECK-NEXT: $w0 = COPY [[MADDWrrr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_MUL %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as mul_s32_gpr for the s64 type.
 name:            mul_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: mul_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr
-    ; CHECK: $x0 = COPY [[MADDXrrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr
+    ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_MUL %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 # Same as mul_s32_gpr for the s64 type.
 name:            mulh_s64_gpr
 legalized:       true
 regBankSelected: true
 
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: mulh_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]]
-    ; CHECK: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[SMULHrr]]
-    ; CHECK: $x0 = COPY [[UMULHrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[SMULHrr]]
+    ; CHECK-NEXT: $x0 = COPY [[UMULHrr]]
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
     %2:gpr(s64) = G_SMULH %0, %1
     %3:gpr(s64) = G_UMULH %0, %1
     $x0 = COPY %2(s64)
     $x0 = COPY %3(s64)
 ...
 
 ---
 # Same as add_s32_gpr, for G_SDIV operations.
 name:            sdiv_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sdiv_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
-    ; CHECK: $w0 = COPY [[SDIVWr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $w0 = COPY [[SDIVWr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_SDIV %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as add_s64_gpr, for G_SDIV operations.
 name:            sdiv_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: sdiv_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[SDIVXr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[SDIVXr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_SDIV %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 # Same as add_s32_gpr, for G_UDIV operations.
 name:            udiv_s32_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: udiv_s32_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]
-    ; CHECK: $w0 = COPY [[UDIVWr]]
+    ; CHECK: liveins: $w0, $w1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+    ; CHECK-NEXT: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $w0 = COPY [[UDIVWr]]
     %0(s32) = COPY $w0
     %1(s32) = COPY $w1
     %2(s32) = G_UDIV %0, %1
     $w0 = COPY %2(s32)
 ...
 
 ---
 # Same as add_s64_gpr, for G_UDIV operations.
 name:            udiv_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: udiv_s64_gpr
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[UDIVXr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[UDIVXr]]
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = G_UDIV %0, %1
     $x0 = COPY %2(s64)
 ...
 
 ---
 # Check that we select a s32 FPR G_FADD into FADDSrr.
 name:            fadd_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fadd_s32_fpr
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]]
-    ; CHECK: $s0 = COPY [[FADDSrr]]
+    ; CHECK: liveins: $s0, $s1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: $s0 = COPY [[FADDSrr]]
     %0(s32) = COPY $s0
     %1(s32) = COPY $s1
     %2(s32) = G_FADD %0, %1
     $s0 = COPY %2(s32)
 ...
 
 ---
 name:            fadd_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: fadd_s64_fpr
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]]
-    ; CHECK: $d0 = COPY [[FADDDrr]]
+    ; CHECK: liveins: $d0, $d1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: $d0 = COPY [[FADDDrr]]
     %0(s64) = COPY $d0
     %1(s64) = COPY $d1
     %2(s64) = G_FADD %0, %1
     $d0 = COPY %2(s64)
 ...
 
 ---
 name:            fsub_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fsub_s32_fpr
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]]
-    ; CHECK: $s0 = COPY [[FSUBSrr]]
+    ; CHECK: liveins: $s0, $s1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; CHECK-NEXT: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: $s0 = COPY [[FSUBSrr]]
     %0(s32) = COPY $s0
     %1(s32) = COPY $s1
     %2(s32) = G_FSUB %0, %1
     $s0 = COPY %2(s32)
 ...
 
 ---
 name:            fsub_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: fsub_s64_fpr
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]]
-    ; CHECK: $d0 = COPY [[FSUBDrr]]
+    ; CHECK: liveins: $d0, $d1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; CHECK-NEXT: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: $d0 = COPY [[FSUBDrr]]
     %0(s64) = COPY $d0
     %1(s64) = COPY $d1
     %2(s64) = G_FSUB %0, %1
     $d0 = COPY %2(s64)
 ...
 
 ---
 name:            fmul_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fmul_s32_fpr
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]]
-    ; CHECK: $s0 = COPY [[FMULSrr]]
+    ; CHECK: liveins: $s0, $s1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; CHECK-NEXT: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: $s0 = COPY [[FMULSrr]]
     %0(s32) = COPY $s0
     %1(s32) = COPY $s1
     %2(s32) = G_FMUL %0, %1
     $s0 = COPY %2(s32)
 ...
 
 ---
 name:            fmul_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: fmul_s64_fpr
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]]
-    ; CHECK: $d0 = COPY [[FMULDrr]]
+    ; CHECK: liveins: $d0, $d1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; CHECK-NEXT: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: $d0 = COPY [[FMULDrr]]
     %0(s64) = COPY $d0
     %1(s64) = COPY $d1
     %2(s64) = G_FMUL %0, %1
     $d0 = COPY %2(s64)
 ...
 
 ---
 name:            fdiv_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $s0, $s1
 
     ; CHECK-LABEL: name: fdiv_s32_fpr
-    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
-    ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]]
-    ; CHECK: $s0 = COPY [[FDIVSrr]]
+    ; CHECK: liveins: $s0, $s1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
+    ; CHECK-NEXT: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: $s0 = COPY [[FDIVSrr]]
     %0(s32) = COPY $s0
     %1(s32) = COPY $s1
     %2(s32) = G_FDIV %0, %1
     $s0 = COPY %2(s32)
 ...
 
 ---
 name:            fdiv_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: fdiv_s64_fpr
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]]
-    ; CHECK: $d0 = COPY [[FDIVDrr]]
+    ; CHECK: liveins: $d0, $d1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; CHECK-NEXT: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]], implicit $fpcr
+    ; CHECK-NEXT: $d0 = COPY [[FDIVDrr]]
     %0(s64) = COPY $d0
     %1(s64) = COPY $d1
     %2(s64) = G_FDIV %0, %1
     $d0 = COPY %2(s64)
 ...
 ---
 name:            add_v8i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 machineFunctionInfo: {}
 body:             |
   bb.1:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: add_v8i16
     ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY]], [[COPY1]]
-    ; CHECK: $q0 = COPY [[ADDv8i16_]]
-    ; CHECK: RET_ReallyLR implicit $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[ADDv8i16_]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %0:fpr(<8 x s16>) = COPY $q0
     %1:fpr(<8 x s16>) = COPY $q1
     %2:fpr(<8 x s16>) = G_ADD %0, %1
     $q0 = COPY %2(<8 x s16>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            add_v16i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 machineFunctionInfo: {}
 body:             |
   bb.1:
     liveins: $q0, $q1
 
     ; CHECK-LABEL: name: add_v16i8
     ; CHECK: liveins: $q0, $q1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY]], [[COPY1]]
-    ; CHECK: $q0 = COPY [[ADDv16i8_]]
-    ; CHECK: RET_ReallyLR implicit $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[ADDv16i8_]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %0:fpr(<16 x s8>) = COPY $q0
     %1:fpr(<16 x s8>) = COPY $q1
     %2:fpr(<16 x s8>) = G_ADD %0, %1
     $q0 = COPY %2(<16 x s8>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            add_v4i16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: add_v4i16
     ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY]], [[COPY1]]
-    ; CHECK: $d0 = COPY [[ADDv4i16_]]
-    ; CHECK: RET_ReallyLR implicit $d0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $d0 = COPY [[ADDv4i16_]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = COPY $d1
     %2:fpr(<4 x s16>) = G_ADD %0, %1
     $d0 = COPY %2(<4 x s16>)
     RET_ReallyLR implicit $d0
 ...
 ---
 name:            or_v4i16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: or_v4i16
     ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
-    ; CHECK: $d0 = COPY [[ORRv8i8_]]
-    ; CHECK: RET_ReallyLR implicit $d0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = COPY $d1
     %2:fpr(<4 x s16>) = G_OR %0, %1
     $d0 = COPY %2(<4 x s16>)
     RET_ReallyLR implicit $d0
 ...
 ---
 name:            xor_v4i16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: xor_v4i16
     ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY]], [[COPY1]]
-    ; CHECK: $d0 = COPY [[EORv8i8_]]
-    ; CHECK: RET_ReallyLR implicit $d0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $d0 = COPY [[EORv8i8_]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = COPY $d1
     %2:fpr(<4 x s16>) = G_XOR %0, %1
     $d0 = COPY %2(<4 x s16>)
     RET_ReallyLR implicit $d0
 ...
 ---
 name:            mul_v4i16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $d0, $d1
 
     ; CHECK-LABEL: name: mul_v4i16
     ; CHECK: liveins: $d0, $d1
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
-    ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY]], [[COPY1]]
-    ; CHECK: $d0 = COPY [[MULv4i16_]]
-    ; CHECK: RET_ReallyLR implicit $d0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
+    ; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $d0 = COPY [[MULv4i16_]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $d0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = COPY $d1
     %2:fpr(<4 x s16>) = G_MUL %0, %1
     $d0 = COPY %2(<4 x s16>)
     RET_ReallyLR implicit $d0
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir

 body:             |
   ; CHECK-LABEL: name: jt_test
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.4(0x40000000), %bb.1(0x40000000)
   ; CHECK-NEXT:   liveins: $w0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
-  ; CHECK-NEXT:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv
+  ; CHECK-NEXT:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def dead $nzcv
   ; CHECK-NEXT:   [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[SUBSWri]], 0
   ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
   ; CHECK-NEXT:   [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv
   ; CHECK-NEXT:   Bcc 8, %bb.4, implicit $nzcv
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.entry:
   ; CHECK-NEXT:   successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
   ; CHECK-NEXT: {{  $}}

llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK
 ---
 name:            ptr_add
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
       liveins: $x0
     ; CHECK-LABEL: name: ptr_add
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
-    ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 42, 0
-    ; CHECK: $x0 = COPY [[ADDXri]]
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
+    ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 42, 0
+    ; CHECK-NEXT: $x0 = COPY [[ADDXri]]
     %0:gpr(p0) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 42
     %2:gpr(p0) = G_PTR_ADD %0, %1(s64)
     $x0 = COPY %2(p0)
 ...
 
 ---
 name:            ptr_add_no_constant
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
       liveins: $x0, $x1
     ; CHECK-LABEL: name: ptr_add_no_constant
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
-    ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
-    ; CHECK: $x0 = COPY [[ADDXrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
     %0:gpr(p0) = COPY $x0
     %1:gpr(s64) = COPY $x1
     %2:gpr(p0) = G_PTR_ADD %0, %1(s64)
     $x0 = COPY %2(p0)
 ...
 
 ---
 name:            ptr_add_bad_imm
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
       liveins: $x0, $x1
     ; CHECK-LABEL: name: ptr_add_bad_imm
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10000
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
-    ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[SUBREG_TO_REG]]
-    ; CHECK: $x0 = COPY [[ADDXrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10000
+    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
+    ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[SUBREG_TO_REG]]
+    ; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
     %0:gpr(p0) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 10000
     %2:gpr(p0) = G_PTR_ADD %0, %1(s64)
     $x0 = COPY %2(p0)
 ...
 
 ---
 name:            ptr_add_vec
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
       liveins: $q0, $q1
     ; CHECK-LABEL: name: ptr_add_vec
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[ADDv2i64_:%[0-9]+]]:fpr128 = ADDv2i64 [[COPY]], [[COPY1]]
-    ; CHECK: $q0 = COPY [[ADDv2i64_]]
+    ; CHECK: liveins: $q0, $q1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; CHECK-NEXT: [[ADDv2i64_:%[0-9]+]]:fpr128 = ADDv2i64 [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[ADDv2i64_]]
     %0:fpr(<2 x p0>) = COPY $q0
     %1:fpr(<2 x s64>) = COPY $q1
     %3:fpr(<2 x p0>) = G_PTR_ADD %0, %1(<2 x s64>)
     $q0 = COPY %3(<2 x p0>)
 ...
 ---
 name:            ptr_add_neg_imm
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
       liveins: $x0
     ; CHECK-LABEL: name: ptr_add_neg_imm
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
-    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY1]], 10, 0, implicit-def $nzcv
-    ; CHECK: $x0 = COPY [[SUBSXri]]
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
+    ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY1]], 10, 0, implicit-def dead $nzcv
+    ; CHECK-NEXT: $x0 = COPY [[SUBSXri]]
     %0:gpr(p0) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 -10
     %2:gpr(p0) = G_PTR_ADD %0, %1(s64)
     $x0 = COPY %2(p0)
 ...
 ---
 name:            ptr_add_arith_extended
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
       liveins: $x0
     ; CHECK-LABEL: name: ptr_add_arith_extended
-    ; CHECK: %reg0:gpr32 = COPY $w0
-    ; CHECK: %ptr:gpr64 = COPY $x1
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY %ptr
-    ; CHECK: %ptr_add:gpr64sp = ADDXrx [[COPY]], %reg0, 18
-    ; CHECK: $x0 = COPY %ptr_add
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
+    ; CHECK-NEXT: %ptr:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY %ptr
+    ; CHECK-NEXT: %ptr_add:gpr64sp = ADDXrx [[COPY]], %reg0, 18
+    ; CHECK-NEXT: $x0 = COPY %ptr_add
     %reg0:gpr(s32) = COPY $w0
     %ptr:gpr(p0) = COPY $x1
     %ext:gpr(s64) = G_ZEXT %reg0(s32)
     %cst:gpr(s64) = G_CONSTANT i64 2
     %shift:gpr(s64) = G_SHL %ext, %cst(s64)
     %ptr_add:gpr(p0) = G_PTR_ADD %ptr, %shift(s64)
     $x0 = COPY %ptr_add(p0)
 ...
 ---
 name:            ptr_add_negated_reg
 legalized:       true
 regBankSelected: true
 body:             |
   bb.0:
       liveins: $x0, $x1
     ; CHECK-LABEL: name: ptr_add_negated_reg
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
-    ; CHECK: %src:gpr64 = COPY $x1
-    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], %src, implicit-def dead $nzcv
-    ; CHECK: $x0 = COPY [[SUBSXrr]]
+    ; CHECK: liveins: $x0, $x1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK-NEXT: %src:gpr64 = COPY $x1
+    ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], %src, implicit-def dead $nzcv
+    ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
     %0:gpr(p0) = COPY $x0
     %src:gpr(s64) = COPY $x1
     %1:gpr(s64) = G_CONSTANT i64 0
     %neg:gpr(s64) = G_SUB %1, %src
     %2:gpr(p0) = G_PTR_ADD %0, %neg(s64)
     $x0 = COPY %2(p0)
 ...

llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir

stack:
   - { id: 0, name: ptr.addr, size: 8, alignment: 8 }
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $x0
 
     ; CHECK-LABEL: name: check_sext_not_lost
     ; CHECK: liveins: $x0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
-    ; CHECK: STRXui [[COPY1]], %stack.0.ptr.addr, 0 :: (store (p0) into %ir.ptr.addr)
-    ; CHECK: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load (p0) from %ir.ptr.addr)
-    ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x
-    ; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load (s32) from @x)
-    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = nsw SUBSWri [[LDRWui]], 8, 12, implicit-def $nzcv
-    ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[SUBSWri]], %subreg.sub_32
-    ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 15
-    ; CHECK: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[LDRXui]], [[SBFMXri]], 0, 1 :: (load (s32) from %ir.arrayidx)
-    ; CHECK: $w0 = COPY [[LDRWroX]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; CHECK-NEXT: STRXui [[COPY1]], %stack.0.ptr.addr, 0 :: (store (p0) into %ir.ptr.addr)
+    ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load (p0) from %ir.ptr.addr)
+    ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x
+    ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load (s32) from @x)
+    ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = nsw SUBSWri [[LDRWui]], 8, 12, implicit-def dead $nzcv
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
+    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[SUBSWri]], %subreg.sub_32
+    ; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 15
+    ; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[LDRXui]], [[SBFMXri]], 0, 1 :: (load (s32) from %ir.arrayidx)
+    ; CHECK-NEXT: $w0 = COPY [[LDRWroX]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:gpr(p0) = COPY $x0
     %1:gpr(p0) = G_FRAME_INDEX %stack.0.ptr.addr
     G_STORE %0(p0), %1(p0) :: (store (p0) into %ir.ptr.addr)
     %2:gpr(p0) = G_LOAD %1(p0) :: (dereferenceable load (p0) from %ir.ptr.addr)
     %15:gpr64(p0) = ADRP target-flags(aarch64-page) @x
     %4:gpr(p0) = G_ADD_LOW %15(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
     %3:gpr(s32) = G_LOAD %4(p0) :: (dereferenceable load (s32) from @x)
     %5:gpr(s32) = G_CONSTANT i32 32768

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir

 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GFX6-LABEL: name: smax_neg_abs_pattern_s32_ss
     ; GFX6: liveins: $sgpr0
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: %src0:sreg_32 = COPY $sgpr0
-    ; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
+    ; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc
     ; GFX6-NEXT: S_ENDPGM 0, implicit %smax
+    ;
     ; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss
     ; GFX9: liveins: $sgpr0
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: %src0:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
+    ; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc
     ; GFX9-NEXT: S_ENDPGM 0, implicit %smax
     %src0:sgpr(s32) = COPY $sgpr0
     %zero:sgpr(s32) = G_CONSTANT i32 0
     %ineg:sgpr(s32) = G_SUB %zero, %src0
     %smax:sgpr(s32) = G_SMAX %src0, %ineg
     S_ENDPGM 0, implicit %smax
 ...
 
 ---
 name: smax_neg_abs_pattern_s32_ss_commute
 legalized: true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GFX6-LABEL: name: smax_neg_abs_pattern_s32_ss_commute
     ; GFX6: liveins: $sgpr0
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: %src0:sreg_32 = COPY $sgpr0
-    ; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
+    ; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc
     ; GFX6-NEXT: S_ENDPGM 0, implicit %smax
+    ;
     ; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss_commute
     ; GFX9: liveins: $sgpr0
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: %src0:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
+    ; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def dead $scc
     ; GFX9-NEXT: S_ENDPGM 0, implicit %smax
     %src0:sgpr(s32) = COPY $sgpr0
     %zero:sgpr(s32) = G_CONSTANT i32 0
     %ineg:sgpr(s32) = G_SUB %zero, %src0
     %smax:sgpr(s32) = G_SMAX %ineg, %src0
     S_ENDPGM 0, implicit %smax
 ...
 
bb.0:
     ; GFX6-LABEL: name: smax_neg_abs_pattern_s32_vv
     ; GFX6: liveins: $vgpr0
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: %src0:vgpr_32 = COPY $vgpr0
     ; GFX6-NEXT: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     ; GFX6-NEXT: %ineg:vgpr_32, dead %4:sreg_64 = V_SUB_CO_U32_e64 %zero, %src0, 0, implicit $exec
     ; GFX6-NEXT: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
     ; GFX6-NEXT: S_ENDPGM 0, implicit %smax
+    ;
     ; GFX9-LABEL: name: smax_neg_abs_pattern_s32_vv
     ; GFX9: liveins: $vgpr0
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: %src0:vgpr_32 = COPY $vgpr0
     ; GFX9-NEXT: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     ; GFX9-NEXT: %ineg:vgpr_32 = V_SUB_U32_e64 %zero, %src0, 0, implicit $exec
     ; GFX9-NEXT: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
     ; GFX9-NEXT: S_ENDPGM 0, implicit %smax

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
     ; GFX6: liveins: $sgpr0
     ; GFX6-NEXT: {{  $}}
     ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX6-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
+    ; GFX6-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def dead $scc
     ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]]
     ;
     ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
     ; GFX9: liveins: $sgpr0
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GFX9-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
+    ; GFX9-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def dead $scc
     ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_CONSTANT i32 -64
     %2:sgpr(s32) = G_ADD %0, %1
     S_ENDPGM 0, implicit %2
 
 ...
 

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir

body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s16
     ; GCN: liveins: $sgpr0
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
-    ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def $scc
+    ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc
     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s1) = G_TRUNC %0
     %2:sgpr(s16) = G_ANYEXT %1
     %3:sgpr(s32) = G_ZEXT %2
     $sgpr0 = COPY %3
 ...
 

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir

 
 body: |
   bb.0:
 
     ; GFX9PLUS-LABEL: name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant
     ; GFX9PLUS: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
     ; GFX9PLUS-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
     ; GFX9PLUS-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
-    ; GFX9PLUS-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_1]], [[DEF]], implicit-def $scc
+    ; GFX9PLUS-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_1]], [[DEF]], implicit-def dead $scc
     ; GFX9PLUS-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
-    ; GFX9PLUS-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_2]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9PLUS-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_2]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9PLUS-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_AND_B32_]], [[S_AND_B32_1]]
     ; GFX9PLUS-NEXT: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
     %0:sgpr(s16) = G_IMPLICIT_DEF
     %1:sgpr(s16) = G_CONSTANT i16 123
     %2:sgpr(s32) = G_ZEXT %0
     %3:sgpr(s32) = G_ZEXT %1
     %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
     S_ENDPGM 0, implicit %4

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir

 body: |
   bb.0:
     liveins: $sgpr0
     ; SI-LABEL: name: fabs_s32_ss
     ; SI: liveins: $sgpr0
     ; SI-NEXT: {{  $}}
     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
-    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     ;
     ; VI-LABEL: name: fabs_s32_ss
     ; VI: liveins: $sgpr0
     ; VI-NEXT: {{  $}}
     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
-    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     ;
     ; GFX9-LABEL: name: fabs_s32_ss
     ; GFX9: liveins: $sgpr0
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
-    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     ;
     ; GFX10-LABEL: name: fabs_s32_ss
     ; GFX10: liveins: $sgpr0
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
-    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_FABS %0
     $sgpr0 = COPY %1
 ...
 
 ---
 name: fabs_s32_vv

 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
     ; SI-LABEL: name: fabs_v2s16_ss
     ; SI: liveins: $sgpr0_sgpr1
     ; SI-NEXT: {{  $}}
     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
-    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     ;
     ; VI-LABEL: name: fabs_v2s16_ss
     ; VI: liveins: $sgpr0_sgpr1
     ; VI-NEXT: {{  $}}
     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
-    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     ;
     ; GFX9-LABEL: name: fabs_v2s16_ss
     ; GFX9: liveins: $sgpr0_sgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
-    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     ;
     ; GFX10-LABEL: name: fabs_v2s16_ss
     ; GFX10: liveins: $sgpr0_sgpr1
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
-    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     %0:sgpr(<2 x s16>) = COPY $sgpr0
     %1:sgpr(<2 x s16>) = G_FABS %0
     $sgpr0 = COPY %1
 ...
 
 ---
 name: fabs_s16_ss
 legalized: true
 regBankSelected: true
 tracksRegLiveness: true
 
 body: |
   bb.0:
     liveins: $sgpr0
     ; SI-LABEL: name: fabs_s16_ss
     ; SI: liveins: $sgpr0
     ; SI-NEXT: {{  $}}
     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
-    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     ;
     ; VI-LABEL: name: fabs_s16_ss
     ; VI: liveins: $sgpr0
     ; VI-NEXT: {{  $}}
     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
-    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     ;
     ; GFX9-LABEL: name: fabs_s16_ss
     ; GFX9: liveins: $sgpr0
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
-    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     ;
     ; GFX10-LABEL: name: fabs_s16_ss
     ; GFX10: liveins: $sgpr0
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
-    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s16) = G_TRUNC %0
     %2:sgpr(s16) = G_FABS %1
     %3:sgpr(s32) = G_ANYEXT %2
     $sgpr0 = COPY %3
 ...
 

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir

 body: |
   bb.0:
     liveins: $sgpr0
     ; SI-LABEL: name: fneg_s32_ss
     ; SI: liveins: $sgpr0
     ; SI-NEXT: {{  $}}
     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; SI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     ;
     ; VI-LABEL: name: fneg_s32_ss
     ; VI: liveins: $sgpr0
     ; VI-NEXT: {{  $}}
     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; VI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     ;
     ; GFX9-LABEL: name: fneg_s32_ss
     ; GFX9: liveins: $sgpr0
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     ;
     ; GFX10-LABEL: name: fneg_s32_ss
     ; GFX10: liveins: $sgpr0
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX10-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_FNEG %0
     $sgpr0 = COPY %1
 ...
 
 ---
 name: fneg_s32_vv

 body: |
   bb.0:
     liveins: $sgpr0
     ; SI-LABEL: name: fneg_s16_ss
     ; SI: liveins: $sgpr0
     ; SI-NEXT: {{  $}}
     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
-    ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; SI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     ;
     ; VI-LABEL: name: fneg_s16_ss
     ; VI: liveins: $sgpr0
     ; VI-NEXT: {{  $}}
     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
-    ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; VI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     ;
     ; GFX9-LABEL: name: fneg_s16_ss
     ; GFX9: liveins: $sgpr0
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
-    ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     ;
     ; GFX10-LABEL: name: fneg_s16_ss
     ; GFX10: liveins: $sgpr0
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
-    ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX10-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s16) = G_TRUNC %0
     %2:sgpr(s16) = G_FNEG %1
     %3:sgpr(s32) = G_ANYEXT %2
     $sgpr0 = COPY %3
 ...
 

 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
     ; SI-LABEL: name: fneg_v2s16_ss
     ; SI: liveins: $sgpr0_sgpr1
     ; SI-NEXT: {{  $}}
     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
-    ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; SI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     ;
     ; VI-LABEL: name: fneg_v2s16_ss
     ; VI: liveins: $sgpr0_sgpr1
     ; VI-NEXT: {{  $}}
     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
-    ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; VI-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     ;
     ; GFX9-LABEL: name: fneg_v2s16_ss
     ; GFX9: liveins: $sgpr0_sgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
-    ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     ;
     ; GFX10-LABEL: name: fneg_v2s16_ss
     ; GFX10: liveins: $sgpr0_sgpr1
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
-    ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX10-NEXT: $sgpr0 = COPY [[S_XOR_B32_]]
     %0:sgpr(<2 x s16>) = COPY $sgpr0
     %1:sgpr(<2 x s16>) = G_FNEG %0
     $sgpr0 = COPY %1
 ...
 
 ---
 name: fneg_v2s16_vv

 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
     ; SI-LABEL: name: fneg_fabs_s32_ss
     ; SI: liveins: $sgpr0_sgpr1
     ; SI-NEXT: {{  $}}
     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; SI-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
     ;
     ; VI-LABEL: name: fneg_fabs_s32_ss
     ; VI: liveins: $sgpr0_sgpr1
     ; VI-NEXT: {{  $}}
     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; VI-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
     ;
     ; GFX9-LABEL: name: fneg_fabs_s32_ss
     ; GFX9: liveins: $sgpr0_sgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
     ;
     ; GFX10-LABEL: name: fneg_fabs_s32_ss
     ; GFX10: liveins: $sgpr0_sgpr1
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX10-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = G_FABS %0
     %2:sgpr(s32) = G_FNEG %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---

 body: |
   bb.0:
     liveins: $sgpr0
     ; SI-LABEL: name: fneg_fabs_s16_ss
     ; SI: liveins: $sgpr0
     ; SI-NEXT: {{  $}}
     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
-    ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; SI-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
     ;
     ; VI-LABEL: name: fneg_fabs_s16_ss
     ; VI: liveins: $sgpr0
     ; VI-NEXT: {{  $}}
     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
-    ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; VI-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
     ;
     ; GFX9-LABEL: name: fneg_fabs_s16_ss
     ; GFX9: liveins: $sgpr0
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
-    ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
     ;
     ; GFX10-LABEL: name: fneg_fabs_s16_ss
     ; GFX10: liveins: $sgpr0
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
-    ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX10-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s16) = G_TRUNC %0
     %2:sgpr(s16) = G_FABS %1
     %3:sgpr(s16) = G_FNEG %2
     %4:sgpr(s32) = G_ANYEXT %3
     $sgpr0 = COPY %4
 ...

 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
     ; SI-LABEL: name: fneg_fabs_v2s16_ss
     ; SI: liveins: $sgpr0_sgpr1
     ; SI-NEXT: {{  $}}
     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
-    ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; SI-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
     ;
     ; VI-LABEL: name: fneg_fabs_v2s16_ss
     ; VI: liveins: $sgpr0_sgpr1
     ; VI-NEXT: {{  $}}
     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
-    ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; VI-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
     ;
     ; GFX9-LABEL: name: fneg_fabs_v2s16_ss
     ; GFX9: liveins: $sgpr0_sgpr1
     ; GFX9-NEXT: {{  $}}
     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
-    ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX9-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
     ;
     ; GFX10-LABEL: name: fneg_fabs_v2s16_ss
     ; GFX10: liveins: $sgpr0_sgpr1
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147516416
-    ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
+    ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GFX10-NEXT: $sgpr0 = COPY [[S_OR_B32_]]
     %0:sgpr(<2 x s16>) = COPY $sgpr0
     %1:sgpr(<2 x s16>) = G_FABS %0
     %2:sgpr(<2 x s16>) = G_FNEG %1
     $sgpr0 = COPY %2
 ...
 
 ---

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir

bb.0:
     ; GCN-LABEL: name: select_s32_scc_fneg_lhs
     ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
     ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
     ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
+    ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
     ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
     ; GCN-NEXT: $scc = COPY [[COPY4]]
     ; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_XOR_B32_]], [[COPY3]], implicit $scc
     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = COPY $sgpr2
bb.0:
     ; GCN-LABEL: name: select_s32_scc_fneg_rhs
     ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
     ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
     ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
-    ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def $scc
+    ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def dead $scc
     ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
     ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
     ; GCN-NEXT: $scc = COPY [[COPY4]]
     ; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[S_XOR_B32_]], implicit $scc
     ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
     %2:sgpr(s32) = COPY $sgpr2
     %3:sgpr(s32) = COPY $sgpr3
     %4:sgpr(s32) = G_FNEG %3
     %5:sgpr(s32) = G_ICMP intpred(eq), %0, %1
     %6:sgpr(s32) = G_SELECT %5, %2, %4
     S_ENDPGM 0, implicit %6
 
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir

bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s16
     ; GCN: liveins: $sgpr0
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GCN-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
-    ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[S_BFE_I32_]], implicit-def $scc
+    ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[S_BFE_I32_]], implicit-def dead $scc
     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s1) = G_TRUNC %0
     %2:sgpr(s16) = G_SEXT %1
     %3:sgpr(s32) = G_ZEXT %2
     $sgpr0 = COPY %3
 ...
 

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
     ; GCN: liveins: $sgpr0
     ; GCN-NEXT: {{  $}}
     ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
     ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
-    ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def $scc
+    ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc
     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s16) = G_TRUNC %0
     %2:sgpr(s32) = G_ZEXT %1
     $sgpr0 = COPY %2
 
 ...
 

llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; ALL-LABEL: name: test_ashr_i64
     ; ALL: liveins: $rdi, $rsi
-    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
-    ; ALL: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
-    ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY2]]
-    ; ALL: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def $eflags, implicit $cl
-    ; ALL: $rax = COPY [[SAR64rCL]]
-    ; ALL: RET 0, implicit $rax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY2]]
+    ; ALL-NEXT: [[SAR64rCL:%[0-9]+]]:gr64 = SAR64rCL [[COPY]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $rax = COPY [[SAR64rCL]]
+    ; ALL-NEXT: RET 0, implicit $rax
     %0(s64) = COPY $rdi
     %1(s64) = COPY $rsi
     %2(s8) = G_TRUNC %1
     %3(s64) = G_ASHR %0, %2
     $rax = COPY %3(s64)
     RET 0, implicit $rax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi
 
     ; ALL-LABEL: name: test_ashr_i64_imm
     ; ALL: liveins: $rdi
-    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
-    ; ALL: [[SAR64ri:%[0-9]+]]:gr64 = SAR64ri [[COPY]], 5, implicit-def $eflags
-    ; ALL: $rax = COPY [[SAR64ri]]
-    ; ALL: RET 0, implicit $rax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; ALL-NEXT: [[SAR64ri:%[0-9]+]]:gr64 = SAR64ri [[COPY]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $rax = COPY [[SAR64ri]]
+    ; ALL-NEXT: RET 0, implicit $rax
     %0(s64) = COPY $rdi
     %1(s8) = G_CONSTANT i8 5
     %2(s64) = G_ASHR %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; ALL-LABEL: name: test_ashr_i32
     ; ALL: liveins: $edi, $esi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY2]]
-    ; ALL: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def $eflags, implicit $cl
-    ; ALL: $eax = COPY [[SAR32rCL]]
-    ; ALL: RET 0, implicit $eax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY2]]
+    ; ALL-NEXT: [[SAR32rCL:%[0-9]+]]:gr32 = SAR32rCL [[COPY]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $eax = COPY [[SAR32rCL]]
+    ; ALL-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s8) = G_TRUNC %1
     %3(s32) = G_ASHR %0, %2
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_ashr_i32_imm
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[SAR32ri:%[0-9]+]]:gr32 = SAR32ri [[COPY]], 5, implicit-def $eflags
-    ; ALL: $eax = COPY [[SAR32ri]]
-    ; ALL: RET 0, implicit $eax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[SAR32ri:%[0-9]+]]:gr32 = SAR32ri [[COPY]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $eax = COPY [[SAR32ri]]
+    ; ALL-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s8) = G_CONSTANT i8 5
     %2(s32) = G_ASHR %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; ALL-LABEL: name: test_ashr_i16
     ; ALL: liveins: $edi, $esi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY3]]
-    ; ALL: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY2]], implicit-def $eflags, implicit $cl
-    ; ALL: $ax = COPY [[SAR16rCL]]
-    ; ALL: RET 0, implicit $ax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY3]]
+    ; ALL-NEXT: [[SAR16rCL:%[0-9]+]]:gr16 = SAR16rCL [[COPY2]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $ax = COPY [[SAR16rCL]]
+    ; ALL-NEXT: RET 0, implicit $ax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s16) = G_TRUNC %0(s32)
     %3(s8) = G_TRUNC %1(s32)
     %4(s16) = G_ASHR %2, %3
     $ax = COPY %4(s16)
     RET 0, implicit $ax
 

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_ashr_i16_imm
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; ALL: [[SAR16ri:%[0-9]+]]:gr16 = SAR16ri [[COPY1]], 5, implicit-def $eflags
-    ; ALL: $ax = COPY [[SAR16ri]]
-    ; ALL: RET 0, implicit $ax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; ALL-NEXT: [[SAR16ri:%[0-9]+]]:gr16 = SAR16ri [[COPY1]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $ax = COPY [[SAR16ri]]
+    ; ALL-NEXT: RET 0, implicit $ax
     %0(s32) = COPY $edi
     %2(s8) = G_CONSTANT i8 5
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_ASHR %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; ALL-LABEL: name: test_ashr_i8
     ; ALL: liveins: $edi, $esi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
-    ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY3]]
-    ; ALL: [[SAR8rCL:%[0-9]+]]:gr8 = SAR8rCL [[COPY2]], implicit-def $eflags, implicit $cl
-    ; ALL: $al = COPY [[SAR8rCL]]
-    ; ALL: RET 0, implicit $al
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY3]]
+    ; ALL-NEXT: [[SAR8rCL:%[0-9]+]]:gr8 = SAR8rCL [[COPY2]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $al = COPY [[SAR8rCL]]
+    ; ALL-NEXT: RET 0, implicit $al
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s8) = G_TRUNC %0(s32)
     %3(s8) = G_TRUNC %1(s32)
     %4(s8) = G_ASHR %2, %3
     $al = COPY %4(s8)
     RET 0, implicit $al
 

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_ashr_i8_imm
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
-    ; ALL: [[SAR8ri:%[0-9]+]]:gr8 = SAR8ri [[COPY1]], 5, implicit-def $eflags
-    ; ALL: $al = COPY [[SAR8ri]]
-    ; ALL: RET 0, implicit $al
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; ALL-NEXT: [[SAR8ri:%[0-9]+]]:gr8 = SAR8ri [[COPY1]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $al = COPY [[SAR8ri]]
+    ; ALL-NEXT: RET 0, implicit $al
     %0(s32) = COPY $edi
     %2(s8) = G_CONSTANT i8 5
     %1(s8) = G_TRUNC %0(s32)
     %3(s8) = G_ASHR %1, %2
     $al = COPY %3(s8)
     RET 0, implicit $al
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir

 body:             |
   bb.1:
     liveins: $edi
 
     ; CHECK-LABEL: name: test_blsi32rr
     ; CHECK: liveins: $edi
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+    ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
     ; CHECK-NEXT: [[SUB32rr:%[0-9]+]]:gr32 = SUB32rr [[MOV32r0_]], [[COPY]], implicit-def dead $eflags
     ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[SUB32rr]], [[COPY]], implicit-def dead $eflags
     ; CHECK-NEXT: $edi = COPY [[AND32rr]]
     %0(s32) = COPY $edi
     %1(s32) = G_CONSTANT i32 0
     %2(s32) = G_SUB %1, %0
     %3(s32) = G_AND %2, %0
     $edi = COPY %3

 body:             |
   bb.1:
     liveins: $edi
 
     ; CHECK-LABEL: name: test_blsi32rr_nomatch
     ; CHECK: liveins: $edi
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
-    ; CHECK-NEXT: [[SUB32ri:%[0-9]+]]:gr32 = SUB32ri [[MOV32r0_]], 0, implicit-def $eflags
+    ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
+    ; CHECK-NEXT: [[SUB32ri:%[0-9]+]]:gr32 = SUB32ri [[MOV32r0_]], 0, implicit-def dead $eflags
     ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[SUB32ri]], [[COPY]], implicit-def dead $eflags
     ; CHECK-NEXT: $edi = COPY [[AND32rr]]
     %0(s32) = COPY $edi
     %1(s32) = G_CONSTANT i32 0
     %2(s32) = G_SUB %1, %1
     %3(s32) = G_AND %2, %0
     $edi = COPY %3
 ...

llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir

 body:             |
   bb.1:
     liveins: $edi
 
     ; CHECK-LABEL: name: test_blsr32rr
     ; CHECK: liveins: $edi
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[COPY]], implicit-def $eflags
+    ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[COPY]], implicit-def dead $eflags
     ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def dead $eflags
     ; CHECK-NEXT: $edi = COPY [[AND32rr]]
     %0(s32) = COPY $edi
     %1(s32) = G_CONSTANT i32 -1
     %2(s32) = G_ADD %0, %1
     %3(s32) = G_AND %2, %0
     $edi = COPY %3
 
body:             |
   bb.1:
     liveins: $edi
 
     ; CHECK-LABEL: name: test_blsr32rr_nomatch
     ; CHECK: liveins: $edi
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri -1
-    ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[MOV32ri]], implicit-def $eflags
+    ; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[MOV32ri]], implicit-def dead $eflags
     ; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def dead $eflags
     ; CHECK-NEXT: $edi = COPY [[AND32rr]]
     %0(s32) = COPY $edi
     %1(s32) = G_CONSTANT i32 -1
     %2(s32) = G_ADD %1, %1
     %3(s32) = G_AND %2, %0
     $edi = COPY %3
 ...

llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir

 regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
   - { id: 3, class: gpr, preferred-register: '' }
 # X64:           %0:gr32 = COPY $edi
 # X32:           %0:gr32_abcd = COPY $edi
-# CHECK-NEXT:    %2:gr32 = MOV32r0 implicit-def $eflags
+# CHECK-NEXT:    %2:gr32 = MOV32r0 implicit-def dead $eflags
 # CHECK-NEXT:    %3:gr32 = MOV32ri 1
 # CHECK-NEXT:    %1:gr8 = COPY %0.sub_8bit
 # CHECK-NEXT:    TEST8ri %1, 1, implicit-def $eflags
 # CHECK-NEXT:    JCC_1 %[[TRUE:bb.[0-9]+]], 5, implicit $eflags
 # CHECK-NEXT:    JMP_1 %[[FALSE:bb.[0-9]+]]
 # CHECK:      [[TRUE]].{{[a-zA-Z0-9]+}}:
 # CHECK-NEXT:    $eax = COPY %2
 # CHECK-NEXT:    RET 0, implicit $eax

llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir

registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i8
-    ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $dil
-    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY $sil
-    ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY $sil
+    ; CHECK-NEXT: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s8) = COPY $dil
     %1(s8) = COPY $sil
     %4(s8) = G_ICMP intpred(eq), %0(s8), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i16
-    ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $di
-    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY $si
-    ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si
+    ; CHECK-NEXT: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s16) = COPY $di
     %1(s16) = COPY $si
     %4(s8) = G_ICMP intpred(eq), %0(s16), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; CHECK-LABEL: name: test_icmp_eq_i64
-    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
-    ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $rdi, $rsi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+    ; CHECK-NEXT: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s64) = COPY $rdi
     %1(s64) = COPY $rsi
     %4(s8) = G_ICMP intpred(eq), %0(s64), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(eq), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ne_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(ne), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ugt_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(ugt), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_uge_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(uge), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ult_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(ult), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ule_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(ule), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_sgt_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(sgt), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_sge_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(sge), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_slt_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(slt), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_sle_i32
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
-    ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: liveins: $edi, $esi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
+    ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[MOVZX32rr8_]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %4(s8) = G_ICMP intpred(sle), %0(s32), %1
     %5(s32) = G_CONSTANT i32 1
     %6(s32) = G_ANYEXT %4(s8)
     %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-constant.mir

 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i8
     ; CHECK: [[MOV8ri:%[0-9]+]]:gr8 = MOV8ri 2
-    ; CHECK: $al = COPY [[MOV8ri]]
-    ; CHECK: RET 0, implicit $al
+    ; CHECK-NEXT: $al = COPY [[MOV8ri]]
+    ; CHECK-NEXT: RET 0, implicit $al
     %0(s8) = G_CONSTANT i8 2
     $al = COPY %0(s8)
     RET 0, implicit $al
 
 ...
 ---
 name:            const_i16
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i16
     ; CHECK: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 3
-    ; CHECK: $ax = COPY [[MOV16ri]]
-    ; CHECK: RET 0, implicit $ax
+    ; CHECK-NEXT: $ax = COPY [[MOV16ri]]
+    ; CHECK-NEXT: RET 0, implicit $ax
     %0(s16) = G_CONSTANT i16 3
     $ax = COPY %0(s16)
     RET 0, implicit $ax
 
 ...
 ---
 name:            const_i32
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32
     ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 4
-    ; CHECK: $eax = COPY [[MOV32ri]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK-NEXT: $eax = COPY [[MOV32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = G_CONSTANT i32 4
     $eax = COPY %0(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            const_i32_0
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_0
-    ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
-    ; CHECK: $eax = COPY [[MOV32r0_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[MOV32r0_]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = G_CONSTANT i32 0
     $eax = COPY %0(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            const_i64
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i64
     ; CHECK: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri 68719476720
-    ; CHECK: $rax = COPY [[MOV64ri]]
-    ; CHECK: RET 0, implicit $rax
+    ; CHECK-NEXT: $rax = COPY [[MOV64ri]]
+    ; CHECK-NEXT: RET 0, implicit $rax
     %0(s64) = G_CONSTANT i64 68719476720
     $rax = COPY %0(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            const_i64_u32
 alignment:       16
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i64_u32
     ; CHECK: [[MOV32ri64_:%[0-9]+]]:gr64 = MOV32ri64 1879048192
-    ; CHECK: $rax = COPY [[MOV32ri64_]]
-    ; CHECK: RET 0, implicit $rax
+    ; CHECK-NEXT: $rax = COPY [[MOV32ri64_]]
+    ; CHECK-NEXT: RET 0, implicit $rax
     %0(s64) = G_CONSTANT i64 1879048192
     $rax = COPY %0(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            const_i64_i32
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i64_i32
     ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 -1
-    ; CHECK: $rax = COPY [[MOV64ri32_]]
-    ; CHECK: RET 0, implicit $rax
+    ; CHECK-NEXT: $rax = COPY [[MOV64ri32_]]
+    ; CHECK-NEXT: RET 0, implicit $rax
     %0(s64) = G_CONSTANT i64 -1
     $rax = COPY %0(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            main
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi
 
     ; CHECK-LABEL: name: main
-    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
-    ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 0
-    ; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[MOV64ri32_]] :: (store (p0) into %ir.data)
-    ; CHECK: RET 0
+    ; CHECK: liveins: $rdi
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; CHECK-NEXT: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 0
+    ; CHECK-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[MOV64ri32_]] :: (store (p0) into %ir.data)
+    ; CHECK-NEXT: RET 0
     %0(p0) = COPY $rdi
     %1(p0) = G_CONSTANT i64 0
     G_STORE %1(p0), %0(p0) :: (store (p0) into %ir.data)
     RET 0
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir

 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_1
     ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
-    ; CHECK: $eax = COPY [[MOV32ri]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK-NEXT: $eax = COPY [[MOV32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = G_CONSTANT i32 1
     $eax = COPY %0(s32)
     RET 0, implicit $eax
 ...
 ---
 name:            const_i32_1_optsize
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_1_optsize
-    ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def $eflags
-    ; CHECK: $eax = COPY [[MOV32r1_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[MOV32r1_]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = G_CONSTANT i32 1
     $eax = COPY %0(s32)
     RET 0, implicit $eax
 ...
 ---
 name:            const_i32_1b
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_1b
     ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
-    ; CHECK: $eax = COPY [[MOV32ri]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK-NEXT: $eax = COPY [[MOV32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = G_CONSTANT i32 1
     $eax = COPY %0(s32)
     RET 0, implicit $eax
 ...
 ---
 name:            const_i32_1_optsizeb
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
   - { id: 0, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_1_optsizeb
-    ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def $eflags
-    ; CHECK: $eax = COPY [[MOV32r1_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[MOV32r1_]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %0(s32) = G_CONSTANT i32 1
     $eax = COPY %0(s32)
     RET 0, implicit $eax
 ...

llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; ALL-LABEL: name: test_lshr_i64
     ; ALL: liveins: $rdi, $rsi
-    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
-    ; ALL: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
-    ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY2]]
-    ; ALL: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def $eflags, implicit $cl
-    ; ALL: $rax = COPY [[SHR64rCL]]
-    ; ALL: RET 0, implicit $rax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY2]]
+    ; ALL-NEXT: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $rax = COPY [[SHR64rCL]]
+    ; ALL-NEXT: RET 0, implicit $rax
     %0(s64) = COPY $rdi
     %1(s64) = COPY $rsi
     %2(s8) = G_TRUNC %1
     %3(s64) = G_LSHR %0, %2
     $rax = COPY %3(s64)
     RET 0, implicit $rax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi
 
     ; ALL-LABEL: name: test_lshr_i64_imm
     ; ALL: liveins: $rdi
-    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
-    ; ALL: [[SHR64ri:%[0-9]+]]:gr64 = SHR64ri [[COPY]], 5, implicit-def $eflags
-    ; ALL: $rax = COPY [[SHR64ri]]
-    ; ALL: RET 0, implicit $rax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; ALL-NEXT: [[SHR64ri:%[0-9]+]]:gr64 = SHR64ri [[COPY]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $rax = COPY [[SHR64ri]]
+    ; ALL-NEXT: RET 0, implicit $rax
     %0(s64) = COPY $rdi
     %1(s8) = G_CONSTANT i8 5
     %2(s64) = G_LSHR %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; ALL-LABEL: name: test_lshr_i32
     ; ALL: liveins: $edi, $esi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY2]]
-    ; ALL: [[SHR32rCL:%[0-9]+]]:gr32 = SHR32rCL [[COPY]], implicit-def $eflags, implicit $cl
-    ; ALL: $eax = COPY [[SHR32rCL]]
-    ; ALL: RET 0, implicit $eax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY2]]
+    ; ALL-NEXT: [[SHR32rCL:%[0-9]+]]:gr32 = SHR32rCL [[COPY]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $eax = COPY [[SHR32rCL]]
+    ; ALL-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s8) = G_TRUNC %1
     %3(s32) = G_LSHR %0, %2
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_lshr_i32_imm
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 5, implicit-def $eflags
-    ; ALL: $eax = COPY [[SHR32ri]]
-    ; ALL: RET 0, implicit $eax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $eax = COPY [[SHR32ri]]
+    ; ALL-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s8) = G_CONSTANT i8 5
     %2(s32) = G_LSHR %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; ALL-LABEL: name: test_lshr_i16
     ; ALL: liveins: $edi, $esi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY3]]
-    ; ALL: [[SHR16rCL:%[0-9]+]]:gr16 = SHR16rCL [[COPY2]], implicit-def $eflags, implicit $cl
-    ; ALL: $ax = COPY [[SHR16rCL]]
-    ; ALL: RET 0, implicit $ax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY3]]
+    ; ALL-NEXT: [[SHR16rCL:%[0-9]+]]:gr16 = SHR16rCL [[COPY2]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $ax = COPY [[SHR16rCL]]
+    ; ALL-NEXT: RET 0, implicit $ax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s16) = G_TRUNC %0(s32)
     %3(s8) = G_TRUNC %1(s32)
     %4(s16) = G_LSHR %2, %3
     $ax = COPY %4(s16)
     RET 0, implicit $ax
 

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_lshr_i16_imm
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; ALL: [[SHR16ri:%[0-9]+]]:gr16 = SHR16ri [[COPY1]], 5, implicit-def $eflags
-    ; ALL: $ax = COPY [[SHR16ri]]
-    ; ALL: RET 0, implicit $ax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; ALL-NEXT: [[SHR16ri:%[0-9]+]]:gr16 = SHR16ri [[COPY1]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $ax = COPY [[SHR16ri]]
+    ; ALL-NEXT: RET 0, implicit $ax
     %0(s32) = COPY $edi
     %2(s8) = G_CONSTANT i8 5
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_LSHR %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; ALL-LABEL: name: test_lshr_i8
     ; ALL: liveins: $edi, $esi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
-    ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY3]]
-    ; ALL: [[SHR8rCL:%[0-9]+]]:gr8 = SHR8rCL [[COPY2]], implicit-def $eflags, implicit $cl
-    ; ALL: $al = COPY [[SHR8rCL]]
-    ; ALL: RET 0, implicit $al
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY3]]
+    ; ALL-NEXT: [[SHR8rCL:%[0-9]+]]:gr8 = SHR8rCL [[COPY2]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $al = COPY [[SHR8rCL]]
+    ; ALL-NEXT: RET 0, implicit $al
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s8) = G_TRUNC %0(s32)
     %3(s8) = G_TRUNC %1(s32)
     %4(s8) = G_LSHR %2, %3
     $al = COPY %4(s8)
     RET 0, implicit $al
 

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_lshr_i8_imm
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
-    ; ALL: [[SHR8ri:%[0-9]+]]:gr8 = SHR8ri [[COPY1]], 5, implicit-def $eflags
-    ; ALL: $al = COPY [[SHR8ri]]
-    ; ALL: RET 0, implicit $al
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; ALL-NEXT: [[SHR8ri:%[0-9]+]]:gr8 = SHR8ri [[COPY1]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $al = COPY [[SHR8ri]]
+    ; ALL-NEXT: RET 0, implicit $al
     %0(s32) = COPY $edi
     %2(s8) = G_CONSTANT i8 5
     %1(s8) = G_TRUNC %0(s32)
     %3(s8) = G_LSHR %1, %2
     $al = COPY %3(s8)
     RET 0, implicit $al
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-phi.mir

body:             |
   ; ALL-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; ALL-NEXT:   liveins: $edi, $edx, $esi
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL-NEXT:   [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
   ; ALL-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY $edx
   ; ALL-NEXT:   [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit
-  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
   ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL-NEXT:   JCC_1 %bb.2, 5, implicit $eflags
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT: bb.1.cond.false:
   ; ALL-NEXT:   successors: %bb.2(0x80000000)
   ; ALL-NEXT: {{  $}}
body:             |
   ; ALL-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; ALL-NEXT:   liveins: $edi, $edx, $esi
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL-NEXT:   [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
   ; ALL-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY $edx
   ; ALL-NEXT:   [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit
-  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
   ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL-NEXT:   JCC_1 %bb.2, 5, implicit $eflags
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT: bb.1.cond.false:
   ; ALL-NEXT:   successors: %bb.2(0x80000000)
   ; ALL-NEXT: {{  $}}
body:             |
   ; ALL-LABEL: name: test_i32
   ; ALL: bb.0.entry:
   ; ALL-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; ALL-NEXT:   liveins: $edi, $edx, $esi
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY $edx
-  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
   ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL-NEXT:   JCC_1 %bb.1, 5, implicit $eflags
   ; ALL-NEXT:   JMP_1 %bb.2
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT: bb.1.cond.true:
   ; ALL-NEXT:   successors: %bb.3(0x80000000)
body:             |
   ; ALL-LABEL: name: test_i64
   ; ALL: bb.0.entry:
   ; ALL-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; ALL-NEXT:   liveins: $edi, $rdx, $rsi
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL-NEXT:   [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
   ; ALL-NEXT:   [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
-  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
   ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL-NEXT:   JCC_1 %bb.1, 5, implicit $eflags
   ; ALL-NEXT:   JMP_1 %bb.2
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT: bb.1.cond.true:
   ; ALL-NEXT:   successors: %bb.3(0x80000000)
body:             |
   ; ALL-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; ALL-NEXT:   liveins: $edi, $xmm0, $xmm1
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL-NEXT:   [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
   ; ALL-NEXT:   [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
   ; ALL-NEXT:   [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
   ; ALL-NEXT:   [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
-  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
   ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL-NEXT:   JCC_1 %bb.2, 5, implicit $eflags
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT: bb.1.cond.false:
   ; ALL-NEXT:   successors: %bb.2(0x80000000)
   ; ALL-NEXT: {{  $}}
body:             |
   ; ALL-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; ALL-NEXT:   liveins: $edi, $xmm0, $xmm1
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL-NEXT:   [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
   ; ALL-NEXT:   [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
   ; ALL-NEXT:   [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
   ; ALL-NEXT:   [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
-  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
   ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
   ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
   ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
   ; ALL-NEXT:   JCC_1 %bb.2, 5, implicit $eflags
   ; ALL-NEXT: {{  $}}
   ; ALL-NEXT: bb.1.cond.false:
   ; ALL-NEXT:   successors: %bb.2(0x80000000)
   ; ALL-NEXT: {{  $}}

llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; ALL-LABEL: name: test_shl_i64
     ; ALL: liveins: $rdi, $rsi
-    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
-    ; ALL: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
-    ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY2]]
-    ; ALL: [[SHL64rCL:%[0-9]+]]:gr64 = SHL64rCL [[COPY]], implicit-def $eflags, implicit $cl
-    ; ALL: $rax = COPY [[SHL64rCL]]
-    ; ALL: RET 0, implicit $rax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY2]]
+    ; ALL-NEXT: [[SHL64rCL:%[0-9]+]]:gr64 = SHL64rCL [[COPY]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $rax = COPY [[SHL64rCL]]
+    ; ALL-NEXT: RET 0, implicit $rax
     %0(s64) = COPY $rdi
     %1(s64) = COPY $rsi
     %2(s8) = G_TRUNC %1
     %3(s64) = G_SHL %0, %2
     $rax = COPY %3(s64)
     RET 0, implicit $rax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi
 
     ; ALL-LABEL: name: test_shl_i64_imm
     ; ALL: liveins: $rdi
-    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
-    ; ALL: [[SHL64ri:%[0-9]+]]:gr64 = SHL64ri [[COPY]], 5, implicit-def $eflags
-    ; ALL: $rax = COPY [[SHL64ri]]
-    ; ALL: RET 0, implicit $rax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; ALL-NEXT: [[SHL64ri:%[0-9]+]]:gr64 = SHL64ri [[COPY]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $rax = COPY [[SHL64ri]]
+    ; ALL-NEXT: RET 0, implicit $rax
     %0(s64) = COPY $rdi
     %1(s8) = G_CONSTANT i8 5
     %2(s64) = G_SHL %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi
 
     ; ALL-LABEL: name: test_shl_i64_imm1
     ; ALL: liveins: $rdi
-    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
-    ; ALL: [[ADD64rr:%[0-9]+]]:gr64 = ADD64rr [[COPY]], [[COPY]], implicit-def $eflags
-    ; ALL: $rax = COPY [[ADD64rr]]
-    ; ALL: RET 0, implicit $rax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+    ; ALL-NEXT: [[ADD64rr:%[0-9]+]]:gr64 = ADD64rr [[COPY]], [[COPY]], implicit-def dead $eflags
+    ; ALL-NEXT: $rax = COPY [[ADD64rr]]
+    ; ALL-NEXT: RET 0, implicit $rax
     %0(s64) = COPY $rdi
     %1(s8) = G_CONSTANT i8 1
     %2(s64) = G_SHL %0, %1
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; ALL-LABEL: name: test_shl_i32
     ; ALL: liveins: $edi, $esi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY2]]
-    ; ALL: [[SHL32rCL:%[0-9]+]]:gr32 = SHL32rCL [[COPY]], implicit-def $eflags, implicit $cl
-    ; ALL: $eax = COPY [[SHL32rCL]]
-    ; ALL: RET 0, implicit $eax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY2]]
+    ; ALL-NEXT: [[SHL32rCL:%[0-9]+]]:gr32 = SHL32rCL [[COPY]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $eax = COPY [[SHL32rCL]]
+    ; ALL-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s8) = G_TRUNC %1
     %3(s32) = G_SHL %0, %2
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_shl_i32_imm
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[COPY]], 5, implicit-def $eflags
-    ; ALL: $eax = COPY [[SHL32ri]]
-    ; ALL: RET 0, implicit $eax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[SHL32ri:%[0-9]+]]:gr32 = SHL32ri [[COPY]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $eax = COPY [[SHL32ri]]
+    ; ALL-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s8) = G_CONSTANT i8 5
     %2(s32) = G_SHL %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_shl_i32_imm1
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[COPY]], [[COPY]], implicit-def $eflags
-    ; ALL: $eax = COPY [[ADD32rr]]
-    ; ALL: RET 0, implicit $eax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[COPY]], [[COPY]], implicit-def dead $eflags
+    ; ALL-NEXT: $eax = COPY [[ADD32rr]]
+    ; ALL-NEXT: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s8) = G_CONSTANT i8 1
     %2(s32) = G_SHL %0, %1
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
 ---

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; ALL-LABEL: name: test_shl_i16
     ; ALL: liveins: $edi, $esi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY3]]
-    ; ALL: [[SHL16rCL:%[0-9]+]]:gr16 = SHL16rCL [[COPY2]], implicit-def $eflags, implicit $cl
-    ; ALL: $ax = COPY [[SHL16rCL]]
-    ; ALL: RET 0, implicit $ax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY3]]
+    ; ALL-NEXT: [[SHL16rCL:%[0-9]+]]:gr16 = SHL16rCL [[COPY2]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $ax = COPY [[SHL16rCL]]
+    ; ALL-NEXT: RET 0, implicit $ax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s16) = G_TRUNC %0(s32)
     %3(s8) = G_TRUNC %1(s32)
     %4(s16) = G_SHL %2, %3
     $ax = COPY %4(s16)
     RET 0, implicit $ax
 

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_shl_i16_imm
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; ALL: [[SHL16ri:%[0-9]+]]:gr16 = SHL16ri [[COPY1]], 5, implicit-def $eflags
-    ; ALL: $ax = COPY [[SHL16ri]]
-    ; ALL: RET 0, implicit $ax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; ALL-NEXT: [[SHL16ri:%[0-9]+]]:gr16 = SHL16ri [[COPY1]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $ax = COPY [[SHL16ri]]
+    ; ALL-NEXT: RET 0, implicit $ax
     %0(s32) = COPY $edi
     %2(s8) = G_CONSTANT i8 5
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_SHL %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_shl_i16_imm1
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; ALL: [[ADD16rr:%[0-9]+]]:gr16 = ADD16rr [[COPY1]], [[COPY1]], implicit-def $eflags
-    ; ALL: $ax = COPY [[ADD16rr]]
-    ; ALL: RET 0, implicit $ax
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; ALL-NEXT: [[ADD16rr:%[0-9]+]]:gr16 = ADD16rr [[COPY1]], [[COPY1]], implicit-def dead $eflags
+    ; ALL-NEXT: $ax = COPY [[ADD16rr]]
+    ; ALL-NEXT: RET 0, implicit $ax
     %0(s32) = COPY $edi
     %2(s8) = G_CONSTANT i8 1
     %1(s16) = G_TRUNC %0(s32)
     %3(s16) = G_SHL %1, %2
     $ax = COPY %3(s16)
     RET 0, implicit $ax
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; ALL-LABEL: name: test_shl_i8
     ; ALL: liveins: $edi, $esi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
-    ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
-    ; ALL: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; ALL: $cl = COPY [[COPY3]]
-    ; ALL: [[SHL8rCL:%[0-9]+]]:gr8 = SHL8rCL [[COPY2]], implicit-def $eflags, implicit $cl
-    ; ALL: $al = COPY [[SHL8rCL]]
-    ; ALL: RET 0, implicit $al
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+    ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; ALL-NEXT: $cl = COPY [[COPY3]]
+    ; ALL-NEXT: [[SHL8rCL:%[0-9]+]]:gr8 = SHL8rCL [[COPY2]], implicit-def dead $eflags, implicit $cl
+    ; ALL-NEXT: $al = COPY [[SHL8rCL]]
+    ; ALL-NEXT: RET 0, implicit $al
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s8) = G_TRUNC %0(s32)
     %3(s8) = G_TRUNC %1(s32)
     %4(s8) = G_SHL %2, %3
     $al = COPY %4(s8)
     RET 0, implicit $al
 

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_shl_i8_imm
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
-    ; ALL: [[SHL8ri:%[0-9]+]]:gr8 = SHL8ri [[COPY1]], 5, implicit-def $eflags
-    ; ALL: $al = COPY [[SHL8ri]]
-    ; ALL: RET 0, implicit $al
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; ALL-NEXT: [[SHL8ri:%[0-9]+]]:gr8 = SHL8ri [[COPY1]], 5, implicit-def dead $eflags
+    ; ALL-NEXT: $al = COPY [[SHL8ri]]
+    ; ALL-NEXT: RET 0, implicit $al
     %0(s32) = COPY $edi
     %2(s8) = G_CONSTANT i8 5
     %1(s8) = G_TRUNC %0(s32)
     %3(s8) = G_SHL %1, %2
     $al = COPY %3(s8)
     RET 0, implicit $al
 
 ...

 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; ALL-LABEL: name: test_shl_i8_imm1
     ; ALL: liveins: $edi
-    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
-    ; ALL: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY1]], [[COPY1]], implicit-def $eflags
-    ; ALL: $al = COPY [[ADD8rr]]
-    ; ALL: RET 0, implicit $al
+    ; ALL-NEXT: {{  $}}
+    ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; ALL-NEXT: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY1]], [[COPY1]], implicit-def dead $eflags
+    ; ALL-NEXT: $al = COPY [[ADD8rr]]
+    ; ALL-NEXT: RET 0, implicit $al
     %0(s32) = COPY $edi
     %2(s8) = G_CONSTANT i8 1
     %1(s8) = G_TRUNC %0(s32)
     %3(s8) = G_SHL %1, %2
     $al = COPY %3(s8)
     RET 0, implicit $al
 
 ...

llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir

registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i1_to_i8
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
-    ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
-    ; CHECK: $al = COPY [[AND8ri]]
-    ; CHECK: RET 0, implicit $al
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; CHECK-NEXT: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $al = COPY [[AND8ri]]
+    ; CHECK-NEXT: RET 0, implicit $al
     %1:gpr(s32) = COPY $edi
     %3:gpr(s8) = G_CONSTANT i8 1
     %4:gpr(s8) = G_TRUNC %1(s32)
     %2:gpr(s8) = G_AND %4, %3
     $al = COPY %2(s8)
     RET 0, implicit $al
 
 ...
registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i1_to_i16
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; CHECK: [[AND16ri_:%[0-9]+]]:gr16 = AND16ri [[COPY1]], 1, implicit-def $eflags
-    ; CHECK: $ax = COPY [[AND16ri_]]
-    ; CHECK: RET 0, implicit $ax
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; CHECK-NEXT: [[AND16ri:%[0-9]+]]:gr16 = AND16ri [[COPY1]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $ax = COPY [[AND16ri]]
+    ; CHECK-NEXT: RET 0, implicit $ax
     %1:gpr(s32) = COPY $edi
     %3:gpr(s16) = G_CONSTANT i16 1
     %4:gpr(s16) = G_TRUNC %1(s32)
     %2:gpr(s16) = G_AND %4, %3
     $ax = COPY %2(s16)
     RET 0, implicit $ax
 
 ...
registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i1_to_i32
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[COPY]], 1, implicit-def $eflags
-    ; CHECK: $eax = COPY [[AND32ri_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $eax = COPY [[AND32ri]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %1:gpr(s32) = COPY $edi
     %3:gpr(s32) = G_CONSTANT i32 1
     %4:gpr(s32) = COPY %1(s32)
     %2:gpr(s32) = G_AND %4, %3
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i1_to_i64
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
-    ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def $eflags
-    ; CHECK: $rax = COPY [[AND64ri32_]]
-    ; CHECK: RET 0, implicit $rax
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
+    ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def dead $eflags
+    ; CHECK-NEXT: $rax = COPY [[AND64ri32_]]
+    ; CHECK-NEXT: RET 0, implicit $rax
     %1:gpr(s32) = COPY $edi
     %3:gpr(s64) = G_CONSTANT i64 1
     %4:gpr(s64) = G_ANYEXT %1(s32)
     %2:gpr(s64) = G_AND %4, %3
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i8_to_i16
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
-    ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
-    ; CHECK: $ax = COPY [[COPY3]]
-    ; CHECK: RET 0, implicit $ax
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
+    ; CHECK-NEXT: $ax = COPY [[COPY3]]
+    ; CHECK-NEXT: RET 0, implicit $ax
     %1:gpr(s32) = COPY $edi
     %3:gpr(s16) = G_CONSTANT i16 255
     %4:gpr(s16) = G_TRUNC %1(s32)
     %2:gpr(s16) = G_AND %4, %3
     $ax = COPY %2(s16)
     RET 0, implicit $ax
 
 ...
registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i8_to_i32
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
-    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
-    ; CHECK: $eax = COPY [[MOVZX32rr8_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
+    ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %1:gpr(s32) = COPY $edi
     %3:gpr(s32) = G_CONSTANT i32 255
     %4:gpr(s32) = COPY %1(s32)
     %2:gpr(s32) = G_AND %4, %3
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i8_to_i64
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
-    ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def $eflags
-    ; CHECK: $rax = COPY [[AND64ri32_]]
-    ; CHECK: RET 0, implicit $rax
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
+    ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def dead $eflags
+    ; CHECK-NEXT: $rax = COPY [[AND64ri32_]]
+    ; CHECK-NEXT: RET 0, implicit $rax
     %1:gpr(s32) = COPY $edi
     %3:gpr(s64) = G_CONSTANT i64 255
     %4:gpr(s64) = G_ANYEXT %1(s32)
     %2:gpr(s64) = G_AND %4, %3
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i16_to_i32
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
-    ; CHECK: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
-    ; CHECK: $eax = COPY [[MOVZX32rr16_]]
-    ; CHECK: RET 0, implicit $eax
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; CHECK-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
+    ; CHECK-NEXT: $eax = COPY [[MOVZX32rr16_]]
+    ; CHECK-NEXT: RET 0, implicit $eax
     %1:gpr(s32) = COPY $edi
     %3:gpr(s32) = G_CONSTANT i32 65535
     %4:gpr(s32) = COPY %1(s32)
     %2:gpr(s32) = G_AND %4, %3
     $eax = COPY %2(s32)
     RET 0, implicit $eax
 
 ...
registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i16_to_i64
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
-    ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def $eflags
-    ; CHECK: $rax = COPY [[AND64ri32_]]
-    ; CHECK: RET 0, implicit $rax
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
+    ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def dead $eflags
+    ; CHECK-NEXT: $rax = COPY [[AND64ri32_]]
+    ; CHECK-NEXT: RET 0, implicit $rax
     %1:gpr(s32) = COPY $edi
     %3:gpr(s64) = G_CONSTANT i64 65535
     %4:gpr(s64) = G_ANYEXT %1(s32)
     %2:gpr(s64) = G_AND %4, %3
     $rax = COPY %2(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            zext_i32_to_i64
 alignment:       16
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     ; CHECK-LABEL: name: zext_i32_to_i64
     ; CHECK: liveins: $edi
-    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
-    ; CHECK: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]]
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit
-    ; CHECK: $rax = COPY [[SUBREG_TO_REG]]
-    ; CHECK: RET 0, implicit $rax
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]]
+    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit
+    ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]]
+    ; CHECK-NEXT: RET 0, implicit $rax
     %0:gpr(s32) = COPY $edi
     %1:gpr(s64) = G_ZEXT %0(s32)
     $rax = COPY %1(s64)
     RET 0, implicit $rax
 
 ...

llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll

 ; CHECK-SDISEL:   RET 0, $eax
 
 
 ; CHECK-GISEL: bb.1 (%ir-block.1):
 ; CHECK-GISEL:   successors: %bb.5(0x80000000); %bb.5(100.00%)
 ; CHECK-GISEL:   liveins: $edi
 ; CHECK-GISEL:   %0:gr32 = COPY $edi
 ; CHECK-GISEL:   %10:gr32 = MOV32ri 1
-; CHECK-GISEL:   %11:gr32 = MOV32r0 implicit-def $eflags
-; CHECK-GISEL:   %2:gr32 = SUB32ri %0:gr32(tied-def 0), 0, implicit-def $eflags
+; CHECK-GISEL:   %11:gr32 = MOV32r0 implicit-def dead $eflags
+; CHECK-GISEL:   %2:gr32 = SUB32ri %0:gr32(tied-def 0), 0, implicit-def dead $eflags
 ; CHECK-GISEL: bb.5 (%ir-block.1):
 ; CHECK-GISEL: ; predecessors: %bb.1
 ; CHECK-GISEL:   successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab); %bb.4(66.67%), %bb.2(33.33%)
 ; CHECK-GISEL:   %3:gr32 = MOV32ri 1
 ; CHECK-GISEL:   %13:gr8 = COPY %2.sub_8bit:gr32
 ; CHECK-GISEL:   $cl = COPY %13:gr8
-; CHECK-GISEL:   %4:gr32 = SHL32rCL %3:gr32(tied-def 0), implicit-def $eflags, implicit $cl
-; CHECK-GISEL:   %6:gr32 = AND32ri %4:gr32(tied-def 0), 13056, implicit-def $eflags
-; CHECK-GISEL:   %7:gr32 = MOV32r0 implicit-def $eflags
+; CHECK-GISEL:   %4:gr32 = SHL32rCL %3:gr32(tied-def 0), implicit-def dead $eflags, implicit $cl
+; CHECK-GISEL:   %6:gr32 = AND32ri %4:gr32(tied-def 0), 13056, implicit-def dead $eflags
+; CHECK-GISEL:   %7:gr32 = MOV32r0 implicit-def dead $eflags
 ; CHECK-GISEL:   CMP32rr %6:gr32, %7:gr32, implicit-def $eflags
 ; CHECK-GISEL:   %12:gr8 = SETCCr 5, implicit $eflags
 ; CHECK-GISEL:   TEST8ri %12:gr8, 1, implicit-def $eflags
 ; CHECK-GISEL:   JCC_1 %bb.4, 5, implicit $eflags
 ; CHECK-GISEL:   JMP_1 %bb.2
 ; CHECK-GISEL: bb.6 (%ir-block.1):
 ; CHECK-GISEL: bb.2.sw.epilog8:
 ; CHECK-GISEL: ; predecessors: %bb.5

llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected

registers:
   - { id: 3, class: gpr, preferred-register: '' }
 body:             |
   ; CHECK-LABEL: name: test
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK-NEXT:   liveins: $edi
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
-  ; CHECK-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+  ; CHECK-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
   ; CHECK-NEXT:   [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
   ; CHECK-NEXT:   TEST8ri [[COPY1]], 1, implicit-def $eflags
   ; CHECK-NEXT:   JCC_1 %bb.1, 5, implicit $eflags
   ; CHECK-NEXT:   JMP_1 %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.true:
   ; CHECK-NEXT:   $eax = COPY [[MOV32r0_]]

llvm/utils/TableGen/GlobalISelMatchTable.cpp

void BuildMIAction::emitActionOpcodes(MatchTable &Table,
 
   Table << MatchTable::Opcode("GIR_BuildMI") << MatchTable::Comment("InsnID")
         << MatchTable::IntValue(InsnID) << MatchTable::Comment("Opcode")
         << MatchTable::NamedValue(I->Namespace, I->TheDef->getName())
         << MatchTable::LineBreak;
   for (const auto &Renderer : OperandRenderers)
     Renderer->emitRenderOpcodes(Table, Rule);
 
+  for (auto [OpIdx, Def] : enumerate(I->ImplicitDefs)) {
+    auto Namespace =
+        Def->getValue("Namespace") ? Def->getValueAsString("Namespace") : "";
+    if (DeadImplicitDefs.contains(Def)) {
+      Table
+          << MatchTable::Opcode("GIR_SetImplicitDefDead")
+          << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)
+          << MatchTable::Comment(
+                 ("OpIdx for " + Namespace + "::" + Def->getName() + "").str())
+          << MatchTable::IntValue(OpIdx) << MatchTable::LineBreak;
+    }
+  }
+
   if (I->mayLoad || I->mayStore) {
     Table << MatchTable::Opcode("GIR_MergeMemOperands")
           << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)
           << MatchTable::Comment("MergeInsnID's");
     // Emit the ID's for all the instructions that are matched by this rule.
     // TODO: Limit this to matched instructions that mayLoad/mayStore or have
     //       some other means of having a memoperand. Also limit this to
     //       emitted instructions that expect to have a memoperand too. For