[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions

[zbuljan]

Summary

The patch adds CodeGen support for microMIPS32r6 MUL* and microMIPS64r6 DMUL* instructions:

• updated mul.ll with tests for microMIPSr6 MUL* and DMUL* instruction selection
• separated microMIPSr6 MUL* and DMUL* instructions from equivalent MIPS instructions using NotInMicroMips predicate
• added DAG patterns to description classes for proper selection of MUL* and DMUL* instructions
• implemented DMUL, DMUH, DMULU and DMUHU instructions for microMIPS64r6 and added tests for the standard encodings

[zbuljan]

Rebased to work with top of the tree.
Updated mul.ll with test for microMIPS32r3.

[sdardis]

Can you rebase and repost?

Thanks.

lib/Target/Mips/MicroMips32r6InstrInfo.td

259 ↗

(On Diff #45679)

Is there any reason why this one is not changed?

lib/Target/Mips/Mips32r6InstrInfo.td

723–732 ↗

(On Diff #45679)

These two blocks can be joined together but leave a blank line between the fp msubfs and the integer multiplies.

lib/Target/Mips/Mips64InstrInfo.td

385 ↗

(On Diff #45679)

This is the Octeon multiply, you're looking to change DMULT I believe.

test/MC/Mips/micromips64r6/valid.s

153–160 ↗

(On Diff #45679)

Line up the "# encoding.." parts with the rest of the file.

[zbuljan]

Rebased to work with TOT.
Updated according to comments received from sdardis.

[sdardis]

LGTM.

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
-class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
-class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
-class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
-class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
+class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
+class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
+class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
+class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
 
 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
   dag InOperandList = (ins opnd:$offset);
   dag OutOperandList = (outs);
   string AsmString = !strconcat(instr_asm, "\t$offset");
   bit isBarrier = 1;
 }

llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td

 class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
 class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
 class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
 class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
 class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
 class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
 class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
 class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
+class DMUL_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmul", 0b000011000>;
+class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0b001011000>;
+class DMULU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmulu", 0b010011000>;
+class DMUHU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuhu", 0b011011000>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
   let isReMaterializable = 1;
   let TwoOperandAliasConstraint = "$rd = $rs";
 }
 class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
 class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
 
 class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
 
+class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
+                           InstrItinClass Itin = NoItinerary,
+                           SDPatternOperator Op = null_frag> : MipsR6Inst {
+  dag OutOperandList = (outs GPROpnd:$rd);
+  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
+  string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
+  InstrItinClass Itinerary = Itin;
+  list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
+}
+
+class DMUL_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
+class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH,
+                                              mulhs>;
+class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>;
+class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU,
+                                               mulhu>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
   def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
let DecoderNamespace = "MicroMipsR6" in {
   def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def LDPC_MM64R6 :  R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
                      ISA_MICROMIPS64R6;
   def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
+  def DMUL_MM64R6 : R6MMR6Rel, DMUL_MM64R6_DESC, DMUL_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DMUH_MM64R6 : R6MMR6Rel, DMUH_MM64R6_DESC, DMUH_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DMULU_MM64R6 : R6MMR6Rel, DMULU_MM64R6_DESC, DMULU_MM64R6_ENC,
+                     ISA_MICROMIPS64R6;
+  def DMUHU_MM64R6 : R6MMR6Rel, DMUHU_MM64R6_DESC, DMUHU_MM64R6_ENC,
+                     ISA_MICROMIPS64R6;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // Arbitrary patterns that map to one or more instructions
 //
 //===----------------------------------------------------------------------===//
 

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

let AdditionalPredicates = [NotInMicroMips] in {
   def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
-}
-let AdditionalPredicates = [NotInMicroMips] in {
+
   def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
   def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
-}
-let AdditionalPredicates = [NotInMicroMips] in {
+
   def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
-}
+
   def MUH    : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
   def MUHU   : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
   def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
   def MULU   : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
+}
 def NAL; // BAL with rd=0
 def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
   def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
 }

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

let isCodeGenOnly = 1 in {
   def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
   def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
 }
 
 def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
 
 /// Multiply and Divide Instructions.
+let AdditionalPredicates = [NotInMicroMips] in {
   def DMULT  : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
                MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
   def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
                MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
+}
 def PseudoDMULT  : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
                                  II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
                                  II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
               MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
   def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,

llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td

 def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
   def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
   def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
   def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
 }
 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
   def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
   def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
   def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
   def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
+}
 def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
   def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
   def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
 }
 let isCodeGenOnly = 1 in {

llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN:    -check-prefix=MM32 -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN:    -check-prefix=MM32 -check-prefix=MM32R6
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN:    -check-prefix=64R6
 
 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: mul_i1:
 
   ; M2:         mult    $4, $5
   ; M2:         mflo    $[[T0:[0-9]+]]
   ; M2:         sll     $[[T0]], $[[T0]], 31
; ALL-LABEL: mul_i1:
   ; 64R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
   ; 64R1-R5:    sll     $[[T0]], $[[T0]], 31
   ; 64R1-R5:    sra     $2, $[[T0]], 31
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       sll     $[[T0]], $[[T0]], 31
   ; 64R6:       sra     $2, $[[T0]], 31
 
+  ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
+  ; MM32:       sll     $[[T0]], $[[T0]], 31
+  ; MM32:       sra     $2, $[[T0]], 31
+
   %r = mul i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: mul_i8:
 
; ALL-LABEL: mul_i8:
   ; 64R1:       sll     $[[T0]], $[[T0]], 24
   ; 64R1:       sra     $2, $[[T0]], 24
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seb     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seb     $2, $[[T0]]
+
+  ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
+  ; MM32:       seb     $2, $[[T0]]
+
   %r = mul i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: mul_i16:
 
; ALL-LABEL: mul_i16:
   ; 64R1:       sll     $[[T0]], $[[T0]], 16
   ; 64R1:       sra     $2, $[[T0]], 16
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seh     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seh     $2, $[[T0]]
+
+  ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
+  ; MM32:       seh     $2, $[[T0]]
+
   %r = mul i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: mul_i32:
 
   ; M2:         mult    $4, $5
   ; M2:         mflo    $2
 
   ; 32R1-R5:    mul     $2, $4, $5
   ; 32R6:       mul     $2, $4, $5
 
   ; 64R1-R5:    mul     $2, $4, $5
   ; 64R6:       mul     $2, $4, $5
+
+  ; MM32:       mul     $2, $4, $5
+
   %r = mul i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: mul_i64:
 
; ALL-LABEL: mul_i64:
   ; M4:         dmult   $4, $5
   ; M4:         mflo    $2
 
   ; 64R1-R5:    dmult   $4, $5
   ; 64R1-R5:    mflo    $2
 
   ; 64R6:       dmul    $2, $4, $5
 
+  ; MM32R3:     multu   $[[T0:[0-9]+]], $7
+  ; MM32R3:     mflo    $[[T1:[0-9]+]]
+  ; MM32R3:     mfhi    $[[T2:[0-9]+]]
+  ; MM32R3:     mul     $[[T3:[0-9]+]], $4, $7
+  ; MM32R3:     mul     $[[T0]], $[[T0]], $6
+  ; MM32R3:     addu16  $[[T2]], $[[T2]], $[[T0]]
+  ; MM32R3:     addu16  $2, $[[T2]], $[[T3]]
+
+  ; MM32R6:     mul     $[[T0:[0-9]+]], $5, $7
+  ; MM32R6:     mul     $[[T1:[0-9]+]], $4, $7
+  ; MM32R6:     mul     $[[T2:[0-9]+]], $5, $6
+  ; MM32R6:     muhu    $[[T3:[0-9]+]], $5, $7
+  ; MM32R6:     addu16  $[[T2]], $[[T3]], $[[T2]]
+  ; MM32R6:     addu16  $2, $[[T2]], $[[T1]]
+
   %r = mul i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: mul_i128:
 
; ALL-LABEL: mul_i128:
 
   ; 64R6-DAG:       dmul    $3, $5, $7
   ; 64R6-DAG:       dmul    $[[T0:[0-9]+]], $4, $7
   ; 64R6-DAG:       dmul    $[[T1:[0-9]+]], $5, $6
   ; 64R6:           dmuhu   $[[T2:[0-9]+]], $5, $7
   ; 64R6:           daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; 64R6:           daddu   $2, $[[T1]], $[[T0]]
 
+  ; MM32:           lw      $25, %call16(__multi3)($2)
+
   %r = mul i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
 0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
 0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3
 0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15
 0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15
 0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10
 0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11
 0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5
+0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
+0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
+0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5
+0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
+0x58 0xa4 0x18 0x18 # CHECK: dmul $3, $4, $5
+0x58 0xa4 0x18 0x58 # CHECK: dmuh $3, $4, $5
+0x58 0xa4 0x18 0x98 # CHECK: dmulu $3, $4, $5
+0x58 0xa4 0x18 0xd8 # CHECK: dmuhu $3, $4, $5

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

a:
         sra $3, 7                # CHECK: sra $3, $3, 7           # encoding: [0x00,0x63,0x38,0x80]
         srl $3, 7                # CHECK: srl $3, $3, 7           # encoding: [0x00,0x63,0x38,0x40]
         dsub $1, $2, $3          # CHECK: dsub $1, $2, $3         # encoding: [0x58,0x62,0x09,0x90]
         dsubu $3, $7, $15        # CHECK: dsubu $3, $7, $15       # encoding: [0x59,0xe7,0x19,0xd0]
         dneg $7, $15             # CHECK: dneg $7, $15            # encoding: [0x59,0xe0,0x39,0x90]
         dneg $10                 # CHECK: dneg $10, $10           # encoding: [0x59,0x40,0x51,0x90]
         dnegu $1, $11            # CHECK: dnegu $1, $11           # encoding: [0x59,0x60,0x09,0xd0]
         dnegu $5                 # CHECK: dnegu $5, $5            # encoding: [0x58,0xa0,0x29,0xd0]
+        mul $3, $4, $5           # CHECK mul $3, $4, $5           # encoding: [0x00,0xa4,0x18,0x18]
+        muh $3, $4, $5           # CHECK muh $3, $4, $5           # encoding: [0x00,0xa4,0x18,0x58]
+        mulu $3, $4, $5          # CHECK mulu $3, $4, $5          # encoding: [0x00,0xa4,0x18,0x98]
+        muhu $3, $4, $5          # CHECK muhu $3, $4, $5          # encoding: [0x00,0xa4,0x18,0xd8]
+        dmul $3, $4, $5          # CHECK dmul $3, $4, $5          # encoding: [0x58,0xa4,0x18,0x18]
+        dmuh $3, $4, $5          # CHECK dmuh $3, $4, $5          # encoding: [0x58,0xa4,0x18,0x58]
+        dmulu $3, $4, $5         # CHECK dmulu $3, $4, $5         # encoding: [0x58,0xa4,0x18,0x98]
+        dmuhu $3, $4, $5         # CHECK dmuhu $3, $4, $5         # encoding: [0x58,0xa4,0x18,0xd8]
 
 1: