[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions

[zbuljan]

Summary

The patch adds CodeGen support for microMIPS32r6 MUL* and microMIPS64r6 DMUL* instructions:

• updated mul.ll with tests for microMIPSr6 MUL* and DMUL* instruction selection
• separated microMIPSr6 MUL* and DMUL* instructions from equivalent MIPS instructions using NotInMicroMips predicate
• added DAG patterns to description classes for proper selection of MUL* and DMUL* instructions
• implemented DMUL, DMUH, DMULU and DMUHU instructions for microMIPS64r6 and added tests for the standard encodings

[zbuljan]

Rebased to work with top of the tree.
Updated mul.ll with test for microMIPS32r3.

[sdardis]

Can you rebase and repost?

Thanks.

lib/Target/Mips/MicroMips32r6InstrInfo.td

259

Is there any reason why this one is not changed?

lib/Target/Mips/Mips32r6InstrInfo.td

723–732

These two blocks can be joined together but leave a blank line between the fp msubfs and the integer multiplies.

lib/Target/Mips/Mips64InstrInfo.td

385

This is the Octeon multiply, you're looking to change DMULT I believe.

test/MC/Mips/micromips64r6/valid.s

153–160

Line up the "# encoding.." parts with the rest of the file.

[zbuljan]

Rebased to work with TOT.
Updated according to comments received from sdardis.

[sdardis]

LGTM.

lib/Target/Mips/MicroMips32r6InstrInfo.td

 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
-class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
-class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
+class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
+class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUL, mulhs>;
 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
-class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
+class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUL, mulhu>;
 
 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
   dag InOperandList = (ins opnd:$offset);
   dag OutOperandList = (outs);
   string AsmString = !strconcat(instr_asm, "\t$offset");
   bit isBarrier = 1;
 }

lib/Target/Mips/MicroMips64r6InstrFormats.td

class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct>
 
   let Inst{31-26} = 0b010110;
   let Inst{25-21} = rd;
   let Inst{20-16} = rs;
   let Inst{15-11} = rt;
   let Inst{10-9}  = 0b00;
   let Inst{8-0}  = funct;
 }
+
+class POOL32S_ARITH_FM_MMR6<string opstr, bits<9> funct>
+    : MMR6Arch<opstr>, MipsR6Inst {
+  bits<5> rt;
+  bits<5> rs;
+  bits<5> rd;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10-9}  = 0b00;
+  let Inst{8-0}   = funct;
+}

lib/Target/Mips/MicroMips64r6InstrInfo.td

 class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
 class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
 class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
 class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
 class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
 class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
 class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
 class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
+class DMUL_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmul", 0x18>;
+class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0x58>;
+class DMULU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmulu", 0x98>;
+class DMUHU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuhu", 0xd8>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>

 
 class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
 
 class DDIV_MM64R6_DESC : ArithLogicR<"ddiv", GPR32Opnd>;
 class DMOD_MM64R6_DESC : ArithLogicR<"dmod", GPR32Opnd>;
 class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
 class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
 
+class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
+                           SDPatternOperator Op = null_frag> {
+  dag OutOperandList = (outs GPROpnd:$rd);
+  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
+  string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
+  list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
+}
+
+class DMUL_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
+class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
+class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd>;
+class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
   def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
let DecoderNamespace = "MicroMipsR6" in {
   def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
   def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
+  def DMUL_MM64R6: R6MMR6Rel, DMUL_MM64R6_ENC, DMUL_MM64R6_DESC,
+                   ISA_MICROMIPS64R6;
+  def DMUH_MM64R6: R6MMR6Rel, DMUH_MM64R6_ENC, DMUH_MM64R6_DESC,
+                   ISA_MICROMIPS64R6;
+  def DMULU_MM64R6: R6MMR6Rel, DMULU_MM64R6_ENC, DMULU_MM64R6_DESC,
+                    ISA_MICROMIPS64R6;
+  def DMUHU_MM64R6: R6MMR6Rel, DMUHU_MM64R6_ENC, DMUHU_MM64R6_DESC,
+                    ISA_MICROMIPS64R6;
 }

lib/Target/Mips/Mips32r6InstrInfo.td

let AdditionalPredicates = [NotInMicroMips] in {
   def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
 }
 def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
 def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
 }
+let AdditionalPredicates = [NotInMicroMips] in {
   def MUH    : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
   def MUHU   : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
   def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
   def MULU   : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
+}
 def NAL; // BAL with rd=0
 def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
 }
 def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
 let AdditionalPredicates = [NotInMicroMips] in {

lib/Target/Mips/Mips64InstrInfo.td

 // Branch on Bit Set /+32
 def BBIT1  : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
                            uimm5_64_report_uimm6>, BBIT_FM<0x3a>;
 def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64,
                            0x100000000>, BBIT_FM<0x3e>;
 
 // Multiply Doubleword to GPR
 let Defs = [HI0, LO0, P0, P1, P2] in
   def DMUL  : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
-                              ADD_FM<0x1c, 0x03>;
+              ADD_FM<0x1c, 0x03>, ISA_NOT_MICROMIPS_NOT_64R6;
 
 // Extract a signed bit field /+32
 def EXTS  : ExtsCins<"exts">, EXTS_FM<0x3a>;
 def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
 
 // Clear and insert a bit field /+32
 def CINS  : ExtsCins<"cins">, EXTS_FM<0x32>;
 def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;

lib/Target/Mips/Mips64r6InstrInfo.td

 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
 def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
 def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
   def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
   def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
   def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
   def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
+}
 def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
   def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
   def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
 }
 

lib/Target/Mips/MipsInstrInfo.td

 }
 
 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
 // It can be used only on instructions that doesn't inherit PredicateControl.
 class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
   let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
 }
 
+class ISA_NOT_MICROMIPS_NOT_64R6 {
+  list<Predicate> InsnPredicates = [NotInMicroMips, NotMips64r6];
+}
+
 //===----------------------------------------------------------------------===//
 
 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
   let EncodingPredicates = [HasStdEnc];
 }
 
 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
   InstAlias<Asm, Result, Emit>, PredicateControl;

test/CodeGen/Mips/llvm-ir/mul.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM32 -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=MM32 -check-prefix=MM32R6
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=64R6
 
 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: mul_i1:
 
   ; M2:         mult    $4, $5
   ; M2:         mflo    $[[T0:[0-9]+]]
   ; M2:         sll     $[[T0]], $[[T0]], 31
; ALL-LABEL: mul_i1:
   ; 64R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
   ; 64R1-R5:    sll     $[[T0]], $[[T0]], 31
   ; 64R1-R5:    sra     $2, $[[T0]], 31
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       sll     $[[T0]], $[[T0]], 31
   ; 64R6:       sra     $2, $[[T0]], 31
 
+  ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
+  ; MM32:       sll     $[[T0]], $[[T0]], 31
+  ; MM32:       sra     $2, $[[T0]], 31
+
   %r = mul i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: mul_i8:
 
; ALL-LABEL: mul_i8:
   ; 64R1:       sll     $[[T0]], $[[T0]], 24
   ; 64R1:       sra     $2, $[[T0]], 24
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seb     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seb     $2, $[[T0]]
+
+  ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
+  ; MM32:       seb     $2, $[[T0]]
+
   %r = mul i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: mul_i16:
 
; ALL-LABEL: mul_i16:
   ; 64R1:       sll     $[[T0]], $[[T0]], 16
   ; 64R1:       sra     $2, $[[T0]], 16
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seh     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seh     $2, $[[T0]]
+
+  ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
+  ; MM32:       seh     $2, $[[T0]]
+
   %r = mul i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: mul_i32:
 
   ; M2:         mult    $4, $5
   ; M2:         mflo    $2
 
   ; 32R1-R5:    mul     $2, $4, $5
   ; 32R6:       mul     $2, $4, $5
 
   ; 64R1-R5:    mul     $2, $4, $5
   ; 64R6:       mul     $2, $4, $5
+
+  ; MM32:       mul     $2, $4, $5
+
   %r = mul i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: mul_i64:
 
; ALL-LABEL: mul_i64:
   ; M4:         dmult   $4, $5
   ; M4:         mflo    $2
 
   ; 64R1-R5:    dmult   $4, $5
   ; 64R1-R5:    mflo    $2
 
   ; 64R6:       dmul    $2, $4, $5
 
+  ; MM32R3:     multu   $[[T0:[0-9]+]], $7
+  ; MM32R3:     mflo    $[[T1:[0-9]+]]
+  ; MM32R3:     mfhi    $[[T2:[0-9]+]]
+  ; MM32R3:     mul     $[[T3:[0-9]+]], $4, $7
+  ; MM32R3:     mul     $[[T0]], $[[T0]], $6
+  ; MM32R3:     addu16  $[[T2]], $[[T2]], $[[T0]]
+  ; MM32R3:     addu16  $2, $[[T2]], $[[T3]]
+
+  ; MM32R6:     mul     $[[T0:[0-9]+]], $5, $7
+  ; MM32R6:     mul     $[[T1:[0-9]+]], $4, $7
+  ; MM32R6:     mul     $[[T2:[0-9]+]], $5, $6
+  ; MM32R6:     muhu    $[[T3:[0-9]+]], $5, $7
+  ; MM32R6:     addu16  $[[T2]], $[[T3]], $[[T2]]
+  ; MM32R6:     addu16  $2, $[[T2]], $[[T1]]
+
   %r = mul i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: mul_i128:
 
; ALL-LABEL: mul_i128:
 
   ; 64R6:           dmul    $[[T0:[0-9]+]], $5, $6
   ; 64R6:           dmuhu   $[[T1:[0-9]+]], $5, $7
   ; 64R6:           daddu   $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; 64R6:           dmul    $[[T3:[0-9]+]], $4, $7
   ; 64R6:           daddu   $2, $[[T2]], $[[T3]]
   ; 64R6:           dmul    $3, $5, $7
 
+  ; MM32:           lw      $25, %call16(__multi3)($2)
+
   %r = mul i128 %a, %b
   ret i128 %r
 }

test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0xe3 0x7c # CHECK: deret
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
+0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
+0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5
+0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
+0x58 0xa4 0x18 0x18 # CHECK: dmul $3, $4, $5
+0x58 0xa4 0x18 0x58 # CHECK: dmuh $3, $4, $5
+0x58 0xa4 0x18 0x98 # CHECK: dmulu $3, $4, $5
+0x58 0xa4 0x18 0xd8 # CHECK: dmuhu $3, $4, $5

test/MC/Mips/micromips64r6/valid.s

a:
         selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3  # encoding: [0x54,0x62,0x08,0x78]
         selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8  # encoding: [0x55,0x04,0x12,0x78]
         class.s $f2, $f3         # CHECK: class.s $f2, $f3        # encoding: [0x54,0x62,0x00,0x60]
         class.d $f2, $f4         # CHECK: class.d $f2, $f4        # encoding: [0x54,0x82,0x02,0x60]
         deret                    # CHECK: deret                   # encoding: [0x00,0x00,0xe3,0x7c]
         di                       # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
         di $0                    # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
         di $15                   # CHECK: di $15                  # encoding: [0x00,0x0f,0x47,0x7c]
+        mul $3, $4, $5           # CHECK mul $3, $4, $5       # encoding: [0x00,0xa4,0x18,0x18]
+        muh $3, $4, $5           # CHECK muh $3, $4, $5       # encoding: [0x00,0xa4,0x18,0x58]
+        mulu $3, $4, $5          # CHECK mulu $3, $4, $5      # encoding: [0x00,0xa4,0x18,0x98]
+        muhu $3, $4, $5          # CHECK muhu $3, $4, $5      # encoding: [0x00,0xa4,0x18,0xd8]
+        dmul $3, $4, $5          # CHECK dmul $3, $4, $5      # encoding: [0x58,0xa4,0x18,0x18]
+        dmuh $3, $4, $5          # CHECK dmuh $3, $4, $5      # encoding: [0x58,0xa4,0x18,0x58]
+        dmulu $3, $4, $5         # CHECK dmulu $3, $4, $5     # encoding: [0x58,0xa4,0x18,0x98]
+        dmuhu $3, $4, $5         # CHECK dmuhu $3, $4, $5     # encoding: [0x58,0xa4,0x18,0xd8]
 
 1: