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Differential D15744

[mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions
ClosedPublic

Authored by zbuljan on Dec 23 2015, 5:44 AM.

Details

Reviewers
dsanders
sdardis
vkalintiris
zoran.jovanovic
hvarga
Commits
rL268714: [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions
Summary

The patch adds CodeGen support for microMIPS32r6 MUL* and microMIPS64r6 DMUL* instructions:

  • updated mul.ll with tests for microMIPSr6 MUL* and DMUL* instruction selection
  • separated microMIPSr6 MUL* and DMUL* instructions from equivalent MIPS instructions using NotInMicroMips predicate
  • added DAG patterns to description classes for proper selection of MUL* and DMUL* instructions
  • implemented DMUL, DMUH, DMULU and DMUHU instructions for microMIPS64r6 and added tests for the standard encodings

Diff Detail

Event Timeline

zbuljan updated this revision to Diff 43525.Dec 23 2015, 5:44 AM
zbuljan retitled this revision from to [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, zoran.jovanovic, hvarga.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptDec 23 2015, 5:44 AM
zbuljan updated this revision to Diff 45679.Jan 22 2016, 4:39 AM

Rebased to work with top of the tree.
Updated mul.ll with test for microMIPS32r3.

Herald added a reviewer: vkalintiris. · View Herald TranscriptJan 22 2016, 4:39 AM
sdardis added a reviewer: sdardis.Apr 21 2016, 4:47 AM
sdardis added a subscriber: sdardis.

Can you rebase and repost?

Thanks.

lib/Target/Mips/MicroMips32r6InstrInfo.td
306–307

Is there any reason why this one is not changed?

lib/Target/Mips/Mips32r6InstrInfo.td
781–790

These two blocks can be joined together but leave a blank line between the fp msubfs and the integer multiplies.

lib/Target/Mips/Mips64InstrInfo.td
390

This is the Octeon multiply, you're looking to change DMULT I believe.

test/MC/Mips/micromips64r6/valid.s
176–183

Line up the "# encoding.." parts with the rest of the file.

sdardis requested changes to this revision.Apr 21 2016, 4:47 AM
sdardis edited edge metadata.
This revision now requires changes to proceed.Apr 21 2016, 4:47 AM
zbuljan updated this revision to Diff 56242.May 5 2016, 1:06 AM
zbuljan edited edge metadata.

Rebased to work with TOT.
Updated according to comments received from sdardis.

sdardis accepted this revision.May 5 2016, 8:18 AM
sdardis edited edge metadata.

LGTM.

This revision is now accepted and ready to land.May 5 2016, 8:18 AM
Closed by commit rL268714: [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions (authored by zbuljan). · Explain WhyMay 6 2016, 1:30 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
8 lines
29 lines
15 lines
10 lines
10 lines
test/
CodeGen/
Mips/
llvm-ir/
38 lines
MC/
Disassembler/
Mips/
micromips64r6/
8 lines
Mips/
micromips64r6/
8 lines

Diff 56242

lib/Target/Mips/MicroMips32r6InstrInfo.td

Show First 20 Lines • Show All 297 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Descriptions // Instruction Descriptions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>; class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>; class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>; class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>; class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
sdardisUnsubmitted
Not Done
ReplyInline Actions

Is there any reason why this one is not changed?

sdardis: Is there any reason why this one is not changed?
class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>; class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>; class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>; class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd> class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
: BRANCH_DESC_BASE, MMR6Arch<instr_asm> { : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
dag InOperandList = (ins opnd:$offset); dag InOperandList = (ins opnd:$offset);
dag OutOperandList = (outs); dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$offset"); string AsmString = !strconcat(instr_asm, "\t$offset");
bit isBarrier = 1; bit isBarrier = 1;
} }
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lib/Target/Mips/MicroMips64r6InstrInfo.td

Show All 37 Lines
class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>; class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>; class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>; class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">; class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>; class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>; class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>; class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>; class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
class DMUL_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmul", 0b000011000>;
class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0b001011000>;
class DMULU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmulu", 0b010011000>;
class DMUHU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuhu", 0b011011000>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Descriptions // Instruction Descriptions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Linesclass DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
let isReMaterializable = 1; let isReMaterializable = 1;
let TwoOperandAliasConstraint = "$rd = $rs"; let TwoOperandAliasConstraint = "$rd = $rs";
} }
class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>; class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>; class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>; class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
InstrItinClass Itin = NoItinerary,
SDPatternOperator Op = null_frag> : MipsR6Inst {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
InstrItinClass Itinerary = Itin;
list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
}
class DMUL_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH,
mulhs>;
class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>;
class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU,
mulhu>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let DecoderNamespace = "MicroMipsR6" in { let DecoderNamespace = "MicroMipsR6" in {
def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6; def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
Show All 40 Lineslet DecoderNamespace = "MicroMipsR6" in {
def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC, def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC,
ISA_MICROMIPS64R6; ISA_MICROMIPS64R6;
def LDPC_MM64R6 : R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC, def LDPC_MM64R6 : R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
ISA_MICROMIPS64R6; ISA_MICROMIPS64R6;
def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC, def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
ISA_MICROMIPS64R6; ISA_MICROMIPS64R6;
def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC, def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
ISA_MICROMIPS64R6; ISA_MICROMIPS64R6;
def DMUL_MM64R6 : R6MMR6Rel, DMUL_MM64R6_DESC, DMUL_MM64R6_ENC,
ISA_MICROMIPS64R6;
def DMUH_MM64R6 : R6MMR6Rel, DMUH_MM64R6_DESC, DMUH_MM64R6_ENC,
ISA_MICROMIPS64R6;
def DMULU_MM64R6 : R6MMR6Rel, DMULU_MM64R6_DESC, DMULU_MM64R6_ENC,
ISA_MICROMIPS64R6;
def DMUHU_MM64R6 : R6MMR6Rel, DMUHU_MM64R6_DESC, DMUHU_MM64R6_ENC,
ISA_MICROMIPS64R6;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Arbitrary patterns that map to one or more instructions // Arbitrary patterns that map to one or more instructions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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lib/Target/Mips/Mips32r6InstrInfo.td

Show First 20 Lines • Show All 769 Lines • ▼ Show 20 Lineslet AdditionalPredicates = [NotInMicroMips] in {
def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
}
let AdditionalPredicates = [NotInMicroMips] in {
def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6; def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6; def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
}
let AdditionalPredicates = [NotInMicroMips] in {
def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
}
def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6; def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6; def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
}
def NAL; // BAL with rd=0 def NAL; // BAL with rd=0
sdardisUnsubmitted
Not Done
ReplyInline Actions

These two blocks can be joined together but leave a blank line between the fp msubfs and the integer multiplies.

sdardis: These two blocks can be joined together but leave a blank line between the fp msubfs and the…
def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6; def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
} }
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
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lib/Target/Mips/Mips64InstrInfo.td

Show First 20 Lines • Show All 214 Lines • ▼ Show 20 Lineslet isCodeGenOnly = 1 in {
def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>; def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
} }
def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>; def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
/// Multiply and Divide Instructions. /// Multiply and Divide Instructions.
let AdditionalPredicates = [NotInMicroMips] in {
def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>, def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6; MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>, def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6; MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
}
def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
II_DMULT>, ISA_MIPS3_NOT_32R6_64R6; II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6; II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>, def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6; MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>, def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS; uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS;
def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64, def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64,
0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS; 0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS;
// Multiply Doubleword to GPR // Multiply Doubleword to GPR
def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
ADD_FM<0x1c, 0x03>, ASE_CNMIPS { ADD_FM<0x1c, 0x03>, ASE_CNMIPS {
let Defs = [HI0, LO0, P0, P1, P2]; let Defs = [HI0, LO0, P0, P1, P2];
sdardisUnsubmitted
Not Done
ReplyInline Actions

This is the Octeon multiply, you're looking to change DMULT I believe.

sdardis: This is the Octeon multiply, you're looking to change DMULT I believe.
} }
// Extract a signed bit field /+32 // Extract a signed bit field /+32
def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>, ASE_CNMIPS; def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>, ASE_CNMIPS;
def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>, ASE_CNMIPS; def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>, ASE_CNMIPS;
// Clear and insert a bit field /+32 // Clear and insert a bit field /+32
def CINS : ExtsCins<"cins">, EXTS_FM<0x32>, ASE_CNMIPS; def CINS : ExtsCins<"cins">, EXTS_FM<0x32>, ASE_CNMIPS;
▲ Show 20 Lines • Show All 319 Lines • Show Last 20 Lines

lib/Target/Mips/Mips64r6InstrInfo.td

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6; def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6; def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6; def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6; def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
} }
def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6; def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
let AdditionalPredicates = [NotInMicroMips] in {
def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6; def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6; def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6; def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6; def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
}
def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6; def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6; def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6; def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
let DecoderNamespace = "Mips32r6_64r6_GP64" in { let DecoderNamespace = "Mips32r6_64r6_GP64" in {
def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64; def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64; def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
} }
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
▲ Show 20 Lines • Show All 116 Lines • Show Last 20 Lines

test/CodeGen/Mips/llvm-ir/mul.ll

Show All 16 Lines
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s -check-prefix=ALL \ ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s -check-prefix=ALL \
; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 ; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s -check-prefix=ALL \ ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s -check-prefix=ALL \
; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 ; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s -check-prefix=ALL \ ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s -check-prefix=ALL \
; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 ; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s -check-prefix=ALL \ ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s -check-prefix=ALL \
; RUN: -check-prefix=64R6 ; RUN: -check-prefix=64R6
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MM32 -check-prefix=MM32R3
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=MM32 -check-prefix=MM32R6
; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: -check-prefix=64R6
define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
entry: entry:
; ALL-LABEL: mul_i1: ; ALL-LABEL: mul_i1:
; M2: mult $4, $5 ; M2: mult $4, $5
; M2: mflo $[[T0:[0-9]+]] ; M2: mflo $[[T0:[0-9]+]]
; M2: sll $[[T0]], $[[T0]], 31 ; M2: sll $[[T0]], $[[T0]], 31
Show All 15 Lines; ALL-LABEL: mul_i1:
; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5 ; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5
; 64R1-R5: sll $[[T0]], $[[T0]], 31 ; 64R1-R5: sll $[[T0]], $[[T0]], 31
; 64R1-R5: sra $2, $[[T0]], 31 ; 64R1-R5: sra $2, $[[T0]], 31
; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: sll $[[T0]], $[[T0]], 31 ; 64R6: sll $[[T0]], $[[T0]], 31
; 64R6: sra $2, $[[T0]], 31 ; 64R6: sra $2, $[[T0]], 31
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: sll $[[T0]], $[[T0]], 31
; MM32: sra $2, $[[T0]], 31
%r = mul i1 %a, %b %r = mul i1 %a, %b
ret i1 %r ret i1 %r
} }
define signext i8 @mul_i8(i8 signext %a, i8 signext %b) { define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
entry: entry:
; ALL-LABEL: mul_i8: ; ALL-LABEL: mul_i8:
Show All 21 Lines; ALL-LABEL: mul_i8:
; 64R1: sll $[[T0]], $[[T0]], 24 ; 64R1: sll $[[T0]], $[[T0]], 24
; 64R1: sra $2, $[[T0]], 24 ; 64R1: sra $2, $[[T0]], 24
; 64R2: mul $[[T0:[0-9]+]], $4, $5 ; 64R2: mul $[[T0:[0-9]+]], $4, $5
; 64R2: seb $2, $[[T0]] ; 64R2: seb $2, $[[T0]]
; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seb $2, $[[T0]] ; 64R6: seb $2, $[[T0]]
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: seb $2, $[[T0]]
%r = mul i8 %a, %b %r = mul i8 %a, %b
ret i8 %r ret i8 %r
} }
define signext i16 @mul_i16(i16 signext %a, i16 signext %b) { define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
entry: entry:
; ALL-LABEL: mul_i16: ; ALL-LABEL: mul_i16:
Show All 21 Lines; ALL-LABEL: mul_i16:
; 64R1: sll $[[T0]], $[[T0]], 16 ; 64R1: sll $[[T0]], $[[T0]], 16
; 64R1: sra $2, $[[T0]], 16 ; 64R1: sra $2, $[[T0]], 16
; 64R2: mul $[[T0:[0-9]+]], $4, $5 ; 64R2: mul $[[T0:[0-9]+]], $4, $5
; 64R2: seh $2, $[[T0]] ; 64R2: seh $2, $[[T0]]
; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: seh $2, $[[T0]] ; 64R6: seh $2, $[[T0]]
; MM32: mul $[[T0:[0-9]+]], $4, $5
; MM32: seh $2, $[[T0]]
%r = mul i16 %a, %b %r = mul i16 %a, %b
ret i16 %r ret i16 %r
} }
define signext i32 @mul_i32(i32 signext %a, i32 signext %b) { define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
entry: entry:
; ALL-LABEL: mul_i32: ; ALL-LABEL: mul_i32:
; M2: mult $4, $5 ; M2: mult $4, $5
; M2: mflo $2 ; M2: mflo $2
; 32R1-R5: mul $2, $4, $5 ; 32R1-R5: mul $2, $4, $5
; 32R6: mul $2, $4, $5 ; 32R6: mul $2, $4, $5
; 64R1-R5: mul $2, $4, $5 ; 64R1-R5: mul $2, $4, $5
; 64R6: mul $2, $4, $5 ; 64R6: mul $2, $4, $5
; MM32: mul $2, $4, $5
%r = mul i32 %a, %b %r = mul i32 %a, %b
ret i32 %r ret i32 %r
} }
define signext i64 @mul_i64(i64 signext %a, i64 signext %b) { define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
entry: entry:
; ALL-LABEL: mul_i64: ; ALL-LABEL: mul_i64:
Show All 25 Lines; ALL-LABEL: mul_i64:
; M4: dmult $4, $5 ; M4: dmult $4, $5
; M4: mflo $2 ; M4: mflo $2
; 64R1-R5: dmult $4, $5 ; 64R1-R5: dmult $4, $5
; 64R1-R5: mflo $2 ; 64R1-R5: mflo $2
; 64R6: dmul $2, $4, $5 ; 64R6: dmul $2, $4, $5
; MM32R3: multu $[[T0:[0-9]+]], $7
; MM32R3: mflo $[[T1:[0-9]+]]
; MM32R3: mfhi $[[T2:[0-9]+]]
; MM32R3: mul $[[T3:[0-9]+]], $4, $7
; MM32R3: mul $[[T0]], $[[T0]], $6
; MM32R3: addu16 $[[T2]], $[[T2]], $[[T0]]
; MM32R3: addu16 $2, $[[T2]], $[[T3]]
; MM32R6: mul $[[T0:[0-9]+]], $5, $7
; MM32R6: mul $[[T1:[0-9]+]], $4, $7
; MM32R6: mul $[[T2:[0-9]+]], $5, $6
; MM32R6: muhu $[[T3:[0-9]+]], $5, $7
; MM32R6: addu16 $[[T2]], $[[T3]], $[[T2]]
; MM32R6: addu16 $2, $[[T2]], $[[T1]]
%r = mul i64 %a, %b %r = mul i64 %a, %b
ret i64 %r ret i64 %r
} }
define signext i128 @mul_i128(i128 signext %a, i128 signext %b) { define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: mul_i128: ; ALL-LABEL: mul_i128:
Show All 11 Lines; ALL-LABEL: mul_i128:
; 64R6-DAG: dmul $3, $5, $7 ; 64R6-DAG: dmul $3, $5, $7
; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6 ; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7 ; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7
; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; 64R6: daddu $2, $[[T1]], $[[T0]] ; 64R6: daddu $2, $[[T1]], $[[T0]]
; MM32: lw $25, %call16(__multi3)($2)
%r = mul i128 %a, %b %r = mul i128 %a, %b
ret i128 %r ret i128 %r
} }

test/MC/Disassembler/Mips/micromips64r6/valid.txt

Show First 20 Lines • Show All 242 Lines • ▼ Show 20 Lines
0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7 0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5 0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3 0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3
0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15 0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15
0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15 0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15
0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10 0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10
0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11 0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11
0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5 0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5
0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5
0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
0x58 0xa4 0x18 0x18 # CHECK: dmul $3, $4, $5
0x58 0xa4 0x18 0x58 # CHECK: dmuh $3, $4, $5
0x58 0xa4 0x18 0x98 # CHECK: dmulu $3, $4, $5
0x58 0xa4 0x18 0xd8 # CHECK: dmuhu $3, $4, $5

test/MC/Mips/micromips64r6/valid.s

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Linesa:
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78] selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78] selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c] di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c]
ceil.l.s $f1, $f3 # CHECK: ceil.l.s $f1, $f3 # encoding: [0x54,0x23,0x13,0x3b] ceil.l.s $f1, $f3 # CHECK: ceil.l.s $f1, $f3 # encoding: [0x54,0x23,0x13,0x3b]
ceil.l.d $f1, $f3 # CHECK: ceil.l.d $f1, $f3 # encoding: [0x54,0x23,0x53,0x3b] ceil.l.d $f1, $f3 # CHECK: ceil.l.d $f1, $f3 # encoding: [0x54,0x23,0x53,0x3b]
floor.l.s $f1, $f3 # CHECK: floor.l.s $f1, $f3 # encoding: [0x54,0x23,0x03,0x3b] floor.l.s $f1, $f3 # CHECK: floor.l.s $f1, $f3 # encoding: [0x54,0x23,0x03,0x3b]
floor.l.d $f1, $f3 # CHECK: floor.l.d $f1, $f3 # encoding: [0x54,0x23,0x43,0x3b] floor.l.d $f1, $f3 # CHECK: floor.l.d $f1, $f3 # encoding: [0x54,0x23,0x43,0x3b]
tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c] tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c]
tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c] tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c]
dinsu $4, $2, 32, 5 # CHECK: dinsu $4, $2, 32, 5 # encoding: [0x58,0x82,0x20,0x34] dinsu $4, $2, 32, 5 # CHECK: dinsu $4, $2, 32, 5 # encoding: [0x58,0x82,0x20,0x34]
dinsm $4, $2, 3, 5 # CHECK: dinsm $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xc4] dinsm $4, $2, 3, 5 # CHECK: dinsm $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xc4]
sdardisUnsubmitted
Not Done
ReplyInline Actions

Line up the "# encoding.." parts with the rest of the file.

sdardis: Line up the "# encoding.." parts with the rest of the file.
dins $4, $2, 3, 5 # CHECK: dins $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xcc] dins $4, $2, 3, 5 # CHECK: dins $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xcc]
mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc] mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc] mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b] mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b]
mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c] mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c]
mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4] mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4]
mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4]
mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesa:
sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80] sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40] srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
dsub $1, $2, $3 # CHECK: dsub $1, $2, $3 # encoding: [0x58,0x62,0x09,0x90] dsub $1, $2, $3 # CHECK: dsub $1, $2, $3 # encoding: [0x58,0x62,0x09,0x90]
dsubu $3, $7, $15 # CHECK: dsubu $3, $7, $15 # encoding: [0x59,0xe7,0x19,0xd0] dsubu $3, $7, $15 # CHECK: dsubu $3, $7, $15 # encoding: [0x59,0xe7,0x19,0xd0]
dneg $7, $15 # CHECK: dneg $7, $15 # encoding: [0x59,0xe0,0x39,0x90] dneg $7, $15 # CHECK: dneg $7, $15 # encoding: [0x59,0xe0,0x39,0x90]
dneg $10 # CHECK: dneg $10, $10 # encoding: [0x59,0x40,0x51,0x90] dneg $10 # CHECK: dneg $10, $10 # encoding: [0x59,0x40,0x51,0x90]
dnegu $1, $11 # CHECK: dnegu $1, $11 # encoding: [0x59,0x60,0x09,0xd0] dnegu $1, $11 # CHECK: dnegu $1, $11 # encoding: [0x59,0x60,0x09,0xd0]
dnegu $5 # CHECK: dnegu $5, $5 # encoding: [0x58,0xa0,0x29,0xd0] dnegu $5 # CHECK: dnegu $5, $5 # encoding: [0x58,0xa0,0x29,0xd0]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
dmul $3, $4, $5 # CHECK dmul $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x18]
dmuh $3, $4, $5 # CHECK dmuh $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x58]
dmulu $3, $4, $5 # CHECK dmulu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x98]
dmuhu $3, $4, $5 # CHECK dmuhu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0xd8]
1: 1: