[LegalizeTypes][RISCV] Correct FP_TO_{S,U}INT expansion when bf16 isn't a legal type

[asb]

Summary

As noted in D156990, the logic in ExpandIntRes_FP_TO_SINT assumes that if the type action for the float type is TypeSoftPromoteHalf, is must have been an f16 (half). However, the meaning of that type action has been overloaded and it is used for both f16 and bf16. This patch adds an appropriate check to ensure ISD::FP16_TO_FP or ISD::BF16_TO_FP is emitted as required.

[asb]

1. Rebase (all dependent patches are now committed)
2. Remove TODO comments that are fixed by this patch

[asb]

Apologies for the noise, the previous versions had a bug in that they were checking the type of Op.getValueType after Op = GetSoftPromotedHalf(Op). The patch now correctly gets the old FP VT before doing that call. This bug was caught by existing tests (I just hadn't seen that half-convert.ll failed) so no further test changes needed.

[joshua-arch1]

LGTM. That's exactly what I meant to do when commenting in D156990.

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
 
   bool IsStrict = N->isStrictFPOpcode();
   SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
   SDValue Op = N->getOperand(IsStrict ? 1 : 0);
   if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
     Op = GetPromotedFloat(Op);
 
   if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
-    EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
+    EVT OFPVT = Op.getValueType();
+    EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), OFPVT);
     Op = GetSoftPromotedHalf(Op);
-    Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
+    Op = DAG.getNode(OFPVT == MVT::f16 ? ISD::FP16_TO_FP : ISD::BF16_TO_FP, dl,
+                     NFPVT, Op);
     Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
     SplitInteger(Op, Lo, Hi);
     return;
   }
 
   if (Op.getValueType() == MVT::bf16) {
     // Extend to f32 as there is no bf16 libcall.
     Op = fpExtendHelper(Op, Chain, IsStrict, MVT::f32, dl, DAG);
void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
 
   bool IsStrict = N->isStrictFPOpcode();
   SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
   SDValue Op = N->getOperand(IsStrict ? 1 : 0);
   if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
     Op = GetPromotedFloat(Op);
 
   if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
-    EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
+    EVT OFPVT = Op.getValueType();
+    EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), OFPVT);
     Op = GetSoftPromotedHalf(Op);
-    Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
+    Op = DAG.getNode(OFPVT == MVT::f16 ? ISD::FP16_TO_FP : ISD::BF16_TO_FP, dl,
+                     NFPVT, Op);
     Op = DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op);
     SplitInteger(Op, Lo, Hi);
     return;
   }
 
   if (Op.getValueType() == MVT::bf16) {
     // Extend to f32 as there is no bf16 libcall.
     Op = fpExtendHelper(Op, Chain, IsStrict, MVT::f32, dl, DAG);

llvm/test/CodeGen/RISCV/bfloat-convert.ll

 ; RV64ID-NEXT:    srli a0, a0, 32
 ; RV64ID-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.bf16(bfloat %a)
   ret i32 %0
 }
 declare i32 @llvm.fptoui.sat.i32.bf16(bfloat)
 
-; TODO: An f16 libcall is incorrectly produced for RV32ID in the following
-; test.
-
 define i64 @fcvt_l_bf16(bfloat %a) nounwind {
 ; CHECK32ZFBFMIN-LABEL: fcvt_l_bf16:
 ; CHECK32ZFBFMIN:       # %bb.0:
 ; CHECK32ZFBFMIN-NEXT:    addi sp, sp, -16
 ; CHECK32ZFBFMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa0, fa0
 ; CHECK32ZFBFMIN-NEXT:    call __fixsfdi@plt
 ; CHECK32ZFBFMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; CHECK32ZFBFMIN-NEXT:    addi sp, sp, 16
 ; CHECK32ZFBFMIN-NEXT:    ret
 ;
 ; RV32ID-LABEL: fcvt_l_bf16:
 ; RV32ID:       # %bb.0:
 ; RV32ID-NEXT:    addi sp, sp, -16
 ; RV32ID-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32ID-NEXT:    call __extendhfsf2@plt
+; RV32ID-NEXT:    fmv.x.w a0, fa0
+; RV32ID-NEXT:    slli a0, a0, 16
+; RV32ID-NEXT:    fmv.w.x fa0, a0
 ; RV32ID-NEXT:    call __fixsfdi@plt
 ; RV32ID-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32ID-NEXT:    addi sp, sp, 16
 ; RV32ID-NEXT:    ret
 ;
 ; CHECK64ZFBFMIN-LABEL: fcvt_l_bf16:
 ; CHECK64ZFBFMIN:       # %bb.0:
 ; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne

 ; RV64ID-NEXT:    and a0, a1, a0
 ; RV64ID-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptosi.sat.i64.bf16(bfloat %a)
   ret i64 %0
 }
 declare i64 @llvm.fptosi.sat.i64.bf16(bfloat)
 
-; TODO: An f16 libcall is incorrectly produced for RV32ID in the following
-; test.
-
 define i64 @fcvt_lu_bf16(bfloat %a) nounwind {
 ; CHECK32ZFBFMIN-LABEL: fcvt_lu_bf16:
 ; CHECK32ZFBFMIN:       # %bb.0:
 ; CHECK32ZFBFMIN-NEXT:    addi sp, sp, -16
 ; CHECK32ZFBFMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa0, fa0
 ; CHECK32ZFBFMIN-NEXT:    call __fixunssfdi@plt
 ; CHECK32ZFBFMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; CHECK32ZFBFMIN-NEXT:    addi sp, sp, 16
 ; CHECK32ZFBFMIN-NEXT:    ret
 ;
 ; RV32ID-LABEL: fcvt_lu_bf16:
 ; RV32ID:       # %bb.0:
 ; RV32ID-NEXT:    addi sp, sp, -16
 ; RV32ID-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32ID-NEXT:    call __extendhfsf2@plt
+; RV32ID-NEXT:    fmv.x.w a0, fa0
+; RV32ID-NEXT:    slli a0, a0, 16
+; RV32ID-NEXT:    fmv.w.x fa0, a0
 ; RV32ID-NEXT:    call __fixunssfdi@plt
 ; RV32ID-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32ID-NEXT:    addi sp, sp, 16
 ; RV32ID-NEXT:    ret
 ;
 ; CHECK64ZFBFMIN-LABEL: fcvt_lu_bf16:
 ; CHECK64ZFBFMIN:       # %bb.0:
 ; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne