[SPARC][IAS] Add support for the full set of CAS instructions

[koakuma]

Summary

This completes the support for the CAS instructions.
Besides the base CASA and CASXA forms, on v9 the aliases CAS, CASX, CASL, and CASXL are also available.

Depends on D157233

[barannikov88]

Missing disassembler tests.

llvm/lib/Target/Sparc/SparcInstrInfo.td

55

59

HasCASA?

[koakuma]

Apply suggestions & fix disassembly issues.

[barannikov88]

llvm/lib/Target/Sparc/SparcInstrInfo.td

59

This should also derive from AssemblerPredicate so it can be used in assembly parser.

llvm/test/MC/Sparc/sparcv9-atomic-instructions.s

1

There should be RUN and CHECK lines for V8 and probably V8 leon.

[koakuma]

Apply suggestions, centralize CAS tests & add three-way V8/V9/LEON tests.

[barannikov88]

LGTM

[koakuma]

Refer to ASR3 directly rather than using its "ASI" alias in instruction definitions (to prevent further changes in D157231 from breaking compilation).

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
     return ResTy;
 
   if (getLexer().is(AsmToken::LBrac)) {
     // Memory operand
     Operands.push_back(SparcOperand::CreateToken("[",
                                                  Parser.getTok().getLoc()));
     Parser.Lex(); // Eat the [
 
-    if (Mnemonic == "cas" || Mnemonic == "casx" || Mnemonic == "casa") {
+    if (Mnemonic == "cas" || Mnemonic == "casl" || Mnemonic == "casa" ||
+        Mnemonic == "casx" || Mnemonic == "casxl" || Mnemonic == "casxa") {
       SMLoc S = Parser.getTok().getLoc();
       if (getLexer().getKind() != AsmToken::Percent)
         return MatchOperand_NoMatch;
       Parser.Lex(); // eat %
 
       MCRegister RegNo;
       unsigned RegKind;
       if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))

llvm/lib/Target/Sparc/SparcInstr64Bit.td

 let Predicates = [Is64Bit], isCodeGenOnly = 1 in {
 def SETHIXi : F2_1<0b100,
                    (outs IntRegs:$rd), (ins i64imm:$imm22),
                    "sethi $imm22, $rd",
                    [(set i64:$rd, SETHIimm:$imm22)]>;
 }
 
 // ATOMICS.
-let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
+let Predicates = [Is64Bit], Constraints = "$swap = $rd" in {
+  let asi = 0b10000000 in
     def CASXrr: F3_1_asi<3, 0b111110,
                 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
                                      I64Regs:$swap),
                  "casx [$rs1], $rs2, $rd",
                  [(set i64:$rd,
                      (atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>;
 
+  let asi = 0b10001000 in
+    def CASXLrr: F3_1_asi<3, 0b111110,
+                (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
+                                     I64Regs:$swap),
+                 "casxl [$rs1], $rs2, $rd",
+                 []>;
+
+  def CASXArr: F3_1_asi<3, 0b111110,
+                (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
+                                     I64Regs:$swap, ASITag:$asi),
+                 "casxa [$rs1] $asi, $rs2, $rd",
+                 []>;
+
+  def CASXAri: F3_1_cas_asi<3, 0b111110,
+                (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
+                                     I64Regs:$swap, ASRRegs:$asr),
+                 "casxa [$rs1] $asr, $rs2, $rd",
+                 []>;
 } // Predicates = [Is64Bit], Constraints = ...
 
 let Predicates = [Is64Bit] in {
 
 // atomic_load_64 addr -> load addr
 def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
 def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>;
 

llvm/lib/Target/Sparc/SparcInstrFormats.td

class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
   let op         = opVal;
   let op3        = op3val;
 
   let Inst{13}   = 0;     // i field = 0
   let Inst{12-5} = asi;   // address space identifier
   let Inst{4-0}  = rs2;
 }
 
+// CAS instructions does not use an immediate even when i=1
+class F3_1_cas_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
+           string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
+   : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> {
+  let asi = 0;
+  let Inst{13}   = 1;     // i field = 1
+}
+
 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
        list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
   : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> {
   let asi = 0;
 }
 
 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
            string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>

llvm/lib/Target/Sparc/SparcInstrInfo.td

def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
              AssemblerPredicate<(all_of FeatureVIS2)>;
 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
              AssemblerPredicate<(all_of FeatureVIS3)>;
 
 // HasHardQuad - This is true when the target processor supports quad floating
 // point instructions.
 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
 
-// HasLeonCASA - This is true when the target processor supports the CASA
+// HasLeonCASA - This is true when the target processor supports the Leon CASA
 // instruction
 def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">;
 
+// HasCAS - This is true when the target processor supports CASA instruction.
+def HasCAS : Predicate<"Subtarget->hasLeonCasa() || Subtarget->isV9()">;
+
 // HasPWRPSR - This is true when the target processor supports partial
 // writes to the PSR register that only affects the ET field.
 def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">,
                 AssemblerPredicate<(all_of FeaturePWRPSR)>;
 
 // HasUMAC_SMAC - This is true when the target processor supports the
 // UMAC and SMAC instructions
 def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13),
                     "membar $simm13", []>;
 
 let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in
   def SIR: F3_2<2, 0b110000, (outs),
                 (ins simm13Op:$simm13),
                  "sir $simm13", []>;
 
 // The CAS instruction, unlike other instructions, only comes in a
-// form which requires an ASI be provided. The ASI value hardcoded
-// here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.
-let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
+// form which requires an ASI be provided.
+let Predicates = [HasV9], Constraints = "$swap = $rd" in {
+  // The ASI value hardcoded here is ASI_PRIMARY, the default
+  // unprivileged ASI for SparcV9.
+  let asi = 0b10000000 in
     def CASrr: F3_1_asi<3, 0b111100,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                      IntRegs:$swap),
                  "cas [$rs1], $rs2, $rd",
                  [(set i32:$rd,
                      (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
 
+  // SparcV9 also specifies a CASL alias, which uses ASI_PRIMARY_LITTLE.
+  let asi = 0b10001000 in
+    def CASLrr: F3_1_asi<3, 0b111100,
+                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
+                                     IntRegs:$swap),
+                 "casl [$rs1], $rs2, $rd",
+                 []>;
+}
 
 // CASA is supported as an instruction on some LEON3 and all LEON4 processors.
 // This version can be automatically lowered from C code, selecting ASI 10
 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
   def CASAasi10: F3_1_asi<3, 0b111100,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                      IntRegs:$swap),
                  "casa [$rs1] 10, $rs2, $rd",
                  [(set i32:$rd,
                      (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
 
-// CASA supported on some LEON3 and all LEON4 processors. Same pattern as
-// CASrr, above, but with a different ASI. This version is supported for
-// inline assembly lowering only.
-let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in
+// CASA supported on all V9, some LEON3 and all LEON4 processors.
+// Same pattern as CASrr above, but with a different ASI.
+// This version is supported for inline assembly lowering only.
+let Predicates = [HasCAS], Constraints = "$swap = $rd" in
   def CASArr: F3_1_asi<3, 0b111100,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                      IntRegs:$swap, ASITag:$asi),
                  "casa [$rs1] $asi, $rs2, $rd", []>;
 
+// On the other hand, CASA that takes its ASI from a register
+// is only supported on V9 processors.
+let Predicates = [HasV9], Constraints = "$swap = $rd" in
+  def CASAri: F3_1_cas_asi<3, 0b111100,
+                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
+                                     IntRegs:$swap, ASRRegs:$asr),
+                 "casa [$rs1] $asr, $rs2, $rd", []>;
+
 // TODO: Add DAG sequence to lower these instructions. Currently, only provided
 // as inline assembler-supported instructions.
 let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in {
   def SMACrr :  F3_1<2, 0b111111,
                    (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
                    "smac $rs1, $rs2, $rd",
                    [], IIC_smac_umac>;
 

llvm/test/MC/Sparc/sparcv9-atomic-instructions.s

 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
 
         ! CHECK: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore  ! encoding: [0x81,0x43,0xe0,0x0f]
         membar 15
 
         ! CHECK: membar #LoadLoad  ! encoding: [0x81,0x43,0xe0,0x01]
         membar #LoadLoad
 
         ! CHECK: membar #LoadLoad | #StoreStore  ! encoding: [0x81,0x43,0xe0,0x09]
         membar #LoadLoad | #StoreStore
 
         ! CHECK: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore | #Lookaside | #MemIssue | #Sync  ! encoding: [0x81,0x43,0xe0,0x7f]
         membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore | #Lookaside | #MemIssue | #Sync
 
         ! CHECK: swapa [%i0+6] %asi, %o2   ! encoding: [0xd4,0xfe,0x20,0x06]
         swapa [%i0+6] %asi, %o2
 
         ! CHECK: ldstuba [%i0+2] %asi, %g1 ! encoding: [0xc2,0xee,0x20,0x02]
         ldstuba [%i0+2] %asi, %g1
 
         ! CHECK: cas [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
         cas [%i0], %l6, %o2
 
+        ! CHECK: casl [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x11,0x16]
+        casl [%i0], %l6, %o2
+
+        ! CHECK: casa [%i0] 128, %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
+        casa [%i0] 0x80, %l6, %o2
+
+        ! CHECK: casa [%i0] 128, %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
+        casa [%i0] (0x40+0x40), %l6, %o2
+
+        ! CHECK: casa [%i0] %asi, %l6, %o2   ! encoding: [0xd5,0xe6,0x20,0x16]
+        casa [%i0] %asi, %l6, %o2
+
         ! CHECK: casx [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x10,0x16]
         casx [%i0], %l6, %o2
+
+        ! CHECK: casxl [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x11,0x16]
+        casxl [%i0], %l6, %o2
+
+        ! CHECK: casxa [%i0] 128, %l6, %o2   ! encoding: [0xd5,0xf6,0x10,0x16]
+        casxa [%i0] 0x80, %l6, %o2
+
+        ! CHECK: casxa [%i0] 128, %l6, %o2   ! encoding: [0xd5,0xf6,0x10,0x16]
+        casxa [%i0] (0x40+0x40), %l6, %o2
+
+        ! CHECK: casxa [%i0] %asi, %l6, %o2   ! encoding: [0xd5,0xf6,0x20,0x16]
+        casxa [%i0] %asi, %l6, %o2