[SPARC][IAS] Add v9 encoding of %fq

[koakuma]

Summary

While both SPARCv7/v8 and v9 has a register named %fq, they encode it differently, so we need to differentiate between them.

Depends on D157231

[barannikov88]

There should be a disassembler test.

llvm/lib/Target/Sparc/SparcInstrInfo.td

1774

[koakuma]

Apply suggestions & add disassembly tests.

[barannikov88]

LGTM

[koakuma]

Improve tests; account for different interpretation of V8/V9 encoding for %fq.

[brad]

@barannikov88 Ping.

[barannikov88]

Still LGTM

llvm/lib/Target/Sparc/SparcInstrInfo.td

 
 
 // Section A.43 - Read Privileged Register Instructions
 let Predicates = [HasV9] in {
 let rs2 = 0 in
   def RDPR : F3_1<2, 0b101010,
                  (outs IntRegs:$rd), (ins PRRegs:$rs1),
                  "rdpr $rs1, $rd", []>;
+
+// Special case %fq as the register is also used in V8
+// (albeit with different instructions and encoding)
+// This allows us to reuse the register definition and
+// the "%fq" designation while giving it a different encoding.
+let Uses = [FQ], rs1 = 15, rs2 = 0 in
+  def RDFQ : F3_1<2, 0b101010,
+                 (outs IntRegs:$rd), (ins),
+                 "rdpr %fq, $rd", []>;
 }
 
 // Section A.62 - Write Privileged Register Instructions
 let Predicates = [HasV9] in {
   def WRPRrr : F3_1<2, 0b110010,
                    (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                    "wrpr $rs1, $rs2, $rd", []>;
   def WRPRri : F3_2<2, 0b110010,

llvm/test/MC/Sparc/sparcv9-instructions.s

! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
         ! V9: rdpr %otherwin, %i5       ! encoding: [0xbb,0x53,0x40,0x00]
         rdpr %otherwin,%i5
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: rdpr %wstate,%i5
         ! V9: rdpr %wstate, %i5         ! encoding: [0xbb,0x53,0x80,0x00]
         rdpr %wstate,%i5
 
         ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: rdpr %fq,%i5
+        ! V9: rdpr %fq, %i5             ! encoding: [0xbb,0x53,0xc0,0x00]
+        rdpr %fq,%i5
+        ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: rdpr %ver,%i5
         ! V9: rdpr %ver, %i5            ! encoding: [0xbb,0x57,0xc0,0x00]
         rdpr %ver,%i5
 
         ! V9: rd %pc, %o7               ! encoding: [0x9f,0x41,0x40,0x00]
         rd %pc, %o7
         ! V9: rd %asi, %g1              ! encoding: [0x83,0x40,0xc0,0x00]
         rd %asi, %g1